ide_ctrl.hh revision 1762
14776Sgblack@eecs.umich.edu/* 24776Sgblack@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 34776Sgblack@eecs.umich.edu * All rights reserved. 44776Sgblack@eecs.umich.edu * 54776Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64776Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 74776Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84776Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94776Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104776Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114776Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124776Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134776Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144776Sgblack@eecs.umich.edu * this software without specific prior written permission. 154776Sgblack@eecs.umich.edu * 164776Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174776Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184776Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194776Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204776Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214776Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224776Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234776Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244776Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254776Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264776Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274776Sgblack@eecs.umich.edu */ 284776Sgblack@eecs.umich.edu 294776Sgblack@eecs.umich.edu/** @file 304776Sgblack@eecs.umich.edu * Simple PCI IDE controller with bus mastering capability and UDMA 314776Sgblack@eecs.umich.edu * modeled after controller in the Intel PIIX4 chip 324776Sgblack@eecs.umich.edu */ 334776Sgblack@eecs.umich.edu 344776Sgblack@eecs.umich.edu#ifndef __IDE_CTRL_HH__ 354776Sgblack@eecs.umich.edu#define __IDE_CTRL_HH__ 364776Sgblack@eecs.umich.edu 374776Sgblack@eecs.umich.edu#include "dev/pcidev.hh" 384776Sgblack@eecs.umich.edu#include "dev/pcireg.h" 394776Sgblack@eecs.umich.edu#include "dev/io_device.hh" 404776Sgblack@eecs.umich.edu 414776Sgblack@eecs.umich.edu#define BMIC0 0x0 // Bus master IDE command register 424776Sgblack@eecs.umich.edu#define BMIS0 0x2 // Bus master IDE status register 434776Sgblack@eecs.umich.edu#define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register 444776Sgblack@eecs.umich.edu#define BMIC1 0x8 // Bus master IDE command register 454776Sgblack@eecs.umich.edu#define BMIS1 0xa // Bus master IDE status register 464776Sgblack@eecs.umich.edu#define BMIDTP1 0xc // Bus master IDE descriptor table pointer register 474776Sgblack@eecs.umich.edu 484776Sgblack@eecs.umich.edu// Bus master IDE command register bit fields 494776Sgblack@eecs.umich.edu#define RWCON 0x08 // Bus master read/write control 504776Sgblack@eecs.umich.edu#define SSBM 0x01 // Start/stop bus master 514776Sgblack@eecs.umich.edu 524776Sgblack@eecs.umich.edu// Bus master IDE status register bit fields 535523Snate@binkert.org#define DMA1CAP 0x40 // Drive 1 DMA capable 545523Snate@binkert.org#define DMA0CAP 0x20 // Drive 0 DMA capable 554776Sgblack@eecs.umich.edu#define IDEINTS 0x04 // IDE Interrupt Status 565523Snate@binkert.org#define IDEDMAE 0x02 // IDE DMA error 575523Snate@binkert.org#define BMIDEA 0x01 // Bus master IDE active 585523Snate@binkert.org 594776Sgblack@eecs.umich.edu// IDE Command byte fields 604776Sgblack@eecs.umich.edu#define IDE_SELECT_OFFSET (6) 614776Sgblack@eecs.umich.edu#define IDE_SELECT_DEV_BIT 0x10 624776Sgblack@eecs.umich.edu 634776Sgblack@eecs.umich.edu#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET 644776Sgblack@eecs.umich.edu#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET 654776Sgblack@eecs.umich.edu 664776Sgblack@eecs.umich.edu// PCI device specific register byte offsets 674830Sgblack@eecs.umich.edu#define PCI_IDE_TIMING 0x40 684830Sgblack@eecs.umich.edu#define PCI_SLAVE_TIMING 0x44 694776Sgblack@eecs.umich.edu#define PCI_UDMA33_CTRL 0x48 704776Sgblack@eecs.umich.edu#define PCI_UDMA33_TIMING 0x4a 714776Sgblack@eecs.umich.edu 724830Sgblack@eecs.umich.edu#define IDETIM (0) 734776Sgblack@eecs.umich.edu#define SIDETIM (4) 744830Sgblack@eecs.umich.edu#define UDMACTL (5) 754830Sgblack@eecs.umich.edu#define UDMATIM (6) 764830Sgblack@eecs.umich.edu 774830Sgblack@eecs.umich.edutypedef enum RegType { 784776Sgblack@eecs.umich.edu COMMAND_BLOCK = 0, 794776Sgblack@eecs.umich.edu CONTROL_BLOCK, 804776Sgblack@eecs.umich.edu BMI_BLOCK 814830Sgblack@eecs.umich.edu} RegType_t; 824830Sgblack@eecs.umich.edu 834776Sgblack@eecs.umich.educlass BaseInterface; 844830Sgblack@eecs.umich.educlass Bus; 854830Sgblack@eecs.umich.educlass HierParams; 864830Sgblack@eecs.umich.educlass IdeDisk; 874830Sgblack@eecs.umich.educlass IntrControl; 884776Sgblack@eecs.umich.educlass PciConfigAll; 894776Sgblack@eecs.umich.educlass PhysicalMemory; 904776Sgblack@eecs.umich.educlass Platform; 915049Sgblack@eecs.umich.edu 925049Sgblack@eecs.umich.edu/** 935049Sgblack@eecs.umich.edu * Device model for an Intel PIIX4 IDE controller 945049Sgblack@eecs.umich.edu */ 955049Sgblack@eecs.umich.edu 965049Sgblack@eecs.umich.educlass IdeController : public PciDev 975049Sgblack@eecs.umich.edu{ 985049Sgblack@eecs.umich.edu friend class IdeDisk; 995049Sgblack@eecs.umich.edu 1005049Sgblack@eecs.umich.edu private: 1015049Sgblack@eecs.umich.edu /** Primary command block registers */ 1025049Sgblack@eecs.umich.edu Addr pri_cmd_addr; 1035049Sgblack@eecs.umich.edu Addr pri_cmd_size; 1044776Sgblack@eecs.umich.edu /** Primary control block registers */ 1054776Sgblack@eecs.umich.edu Addr pri_ctrl_addr; 1064776Sgblack@eecs.umich.edu Addr pri_ctrl_size; 1074776Sgblack@eecs.umich.edu /** Secondary command block registers */ 1084776Sgblack@eecs.umich.edu Addr sec_cmd_addr; 1094776Sgblack@eecs.umich.edu Addr sec_cmd_size; 1104830Sgblack@eecs.umich.edu /** Secondary control block registers */ 1114830Sgblack@eecs.umich.edu Addr sec_ctrl_addr; 1124830Sgblack@eecs.umich.edu Addr sec_ctrl_size; 1134830Sgblack@eecs.umich.edu /** Bus master interface (BMI) registers */ 1144830Sgblack@eecs.umich.edu Addr bmi_addr; 1154830Sgblack@eecs.umich.edu Addr bmi_size; 1164830Sgblack@eecs.umich.edu 1174830Sgblack@eecs.umich.edu private: 1184830Sgblack@eecs.umich.edu /** Registers used for bus master interface */ 1194830Sgblack@eecs.umich.edu uint8_t bmi_regs[16]; 1204830Sgblack@eecs.umich.edu /** Shadows of the device select bit */ 1214776Sgblack@eecs.umich.edu uint8_t dev[2]; 1224830Sgblack@eecs.umich.edu /** Registers used in PCI configuration */ 1234830Sgblack@eecs.umich.edu uint8_t pci_regs[8]; 1244830Sgblack@eecs.umich.edu 1254830Sgblack@eecs.umich.edu // Internal management variables 1264830Sgblack@eecs.umich.edu bool io_enabled; 1274830Sgblack@eecs.umich.edu bool bm_enabled; 1284830Sgblack@eecs.umich.edu bool cmd_in_progress[4]; 1294830Sgblack@eecs.umich.edu 1304830Sgblack@eecs.umich.edu private: 1314830Sgblack@eecs.umich.edu /** IDE disks connected to controller */ 1324830Sgblack@eecs.umich.edu IdeDisk *disks[4]; 1334830Sgblack@eecs.umich.edu 1344830Sgblack@eecs.umich.edu private: 1354830Sgblack@eecs.umich.edu /** Parse the access address to pass on to device */ 1364830Sgblack@eecs.umich.edu void parseAddr(const Addr &addr, Addr &offset, bool &primary, 1374830Sgblack@eecs.umich.edu RegType_t &type); 1384830Sgblack@eecs.umich.edu 1394830Sgblack@eecs.umich.edu /** Select the disk based on the channel and device bit */ 1404830Sgblack@eecs.umich.edu int getDisk(bool primary); 1414830Sgblack@eecs.umich.edu 1424830Sgblack@eecs.umich.edu /** Select the disk based on a pointer */ 1434830Sgblack@eecs.umich.edu int getDisk(IdeDisk *diskPtr); 1444830Sgblack@eecs.umich.edu 1454830Sgblack@eecs.umich.edu public: 1464830Sgblack@eecs.umich.edu /** See if a disk is selected based on its pointer */ 1475049Sgblack@eecs.umich.edu bool isDiskSelected(IdeDisk *diskPtr); 1485049Sgblack@eecs.umich.edu 1495049Sgblack@eecs.umich.edu public: 1505049Sgblack@eecs.umich.edu struct Params : public PciDev::Params 1515049Sgblack@eecs.umich.edu { 1525049Sgblack@eecs.umich.edu /** Array of disk objects */ 1535049Sgblack@eecs.umich.edu std::vector<IdeDisk *> disks; 1545049Sgblack@eecs.umich.edu Bus *host_bus; 1555049Sgblack@eecs.umich.edu Tick pio_latency; 1565049Sgblack@eecs.umich.edu HierParams *hier; 1575049Sgblack@eecs.umich.edu }; 1585049Sgblack@eecs.umich.edu const Params *params() const { return (const Params *)_params; } 1595049Sgblack@eecs.umich.edu 1605049Sgblack@eecs.umich.edu public: 1615049Sgblack@eecs.umich.edu IdeController(Params *p); 1625049Sgblack@eecs.umich.edu ~IdeController(); 1634776Sgblack@eecs.umich.edu 1644830Sgblack@eecs.umich.edu virtual void WriteConfig(int offset, int size, uint32_t data); 1654830Sgblack@eecs.umich.edu virtual void ReadConfig(int offset, int size, uint8_t *data); 1664776Sgblack@eecs.umich.edu 1674776Sgblack@eecs.umich.edu void setDmaComplete(IdeDisk *disk); 1684776Sgblack@eecs.umich.edu 1694776Sgblack@eecs.umich.edu /** 1704776Sgblack@eecs.umich.edu * Read a done field for a given target. 1714830Sgblack@eecs.umich.edu * @param req Contains the address of the field to read. 1724776Sgblack@eecs.umich.edu * @param data Return the field read. 1734776Sgblack@eecs.umich.edu * @return The fault condition of the access. 1744830Sgblack@eecs.umich.edu */ 1754776Sgblack@eecs.umich.edu virtual Fault read(MemReqPtr &req, uint8_t *data); 1764830Sgblack@eecs.umich.edu 1774830Sgblack@eecs.umich.edu /** 1784830Sgblack@eecs.umich.edu * Write to the mmapped I/O control registers. 1794830Sgblack@eecs.umich.edu * @param req Contains the address to write to. 1804830Sgblack@eecs.umich.edu * @param data The data to write. 1814830Sgblack@eecs.umich.edu * @return The fault condition of the access. 1824830Sgblack@eecs.umich.edu */ 1834830Sgblack@eecs.umich.edu virtual Fault write(MemReqPtr &req, const uint8_t *data); 1844830Sgblack@eecs.umich.edu 1854830Sgblack@eecs.umich.edu /** 1864830Sgblack@eecs.umich.edu * Serialize this object to the given output stream. 1874830Sgblack@eecs.umich.edu * @param os The stream to serialize to. 1884830Sgblack@eecs.umich.edu */ 1894830Sgblack@eecs.umich.edu virtual void serialize(std::ostream &os); 1904830Sgblack@eecs.umich.edu 1914830Sgblack@eecs.umich.edu /** 1924830Sgblack@eecs.umich.edu * Reconstruct the state of this object from a checkpoint. 1934830Sgblack@eecs.umich.edu * @param cp The checkpoint use. 1944830Sgblack@eecs.umich.edu * @param section The section name of this object 1954830Sgblack@eecs.umich.edu */ 1964830Sgblack@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1974830Sgblack@eecs.umich.edu 1984830Sgblack@eecs.umich.edu /** 1994830Sgblack@eecs.umich.edu * Return how long this access will take. 2004830Sgblack@eecs.umich.edu * @param req the memory request to calcuate 2014830Sgblack@eecs.umich.edu * @return Tick when the request is done 2024830Sgblack@eecs.umich.edu */ 2034830Sgblack@eecs.umich.edu Tick cacheAccess(MemReqPtr &req); 2044830Sgblack@eecs.umich.edu}; 2054830Sgblack@eecs.umich.edu#endif // __IDE_CTRL_HH_ 2064830Sgblack@eecs.umich.edu