ide_ctrl.hh revision 11264:dc389d2d2f79 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Andrew Schultz
29 *          Miguel Serrano
30 */
31
32/** @file
33 * Simple PCI IDE controller with bus mastering capability and UDMA
34 * modeled after controller in the Intel PIIX4 chip
35 */
36
37#ifndef __DEV_STORAGE_IDE_CTRL_HH__
38#define __DEV_STORAGE_IDE_CTRL_HH__
39
40#include "base/bitunion.hh"
41#include "dev/io_device.hh"
42#include "dev/pci/device.hh"
43#include "params/IdeController.hh"
44
45class IdeDisk;
46
47/**
48 * Device model for an Intel PIIX4 IDE controller
49 */
50
51class IdeController : public PciDevice
52{
53  private:
54    // Bus master IDE status register bit fields
55    BitUnion8(BMIStatusReg)
56        Bitfield<6> dmaCap0;
57        Bitfield<5> dmaCap1;
58        Bitfield<2> intStatus;
59        Bitfield<1> dmaError;
60        Bitfield<0> active;
61    EndBitUnion(BMIStatusReg)
62
63    BitUnion8(BMICommandReg)
64        Bitfield<3> rw;
65        Bitfield<0> startStop;
66    EndBitUnion(BMICommandReg)
67
68    struct Channel
69    {
70        std::string _name;
71
72        const std::string
73        name()
74        {
75            return _name;
76        }
77
78        /** Command and control block registers */
79        Addr cmdAddr, cmdSize, ctrlAddr, ctrlSize;
80
81        /** Registers used for bus master interface */
82        struct BMIRegs
83        {
84            BMICommandReg command;
85            uint8_t reserved0;
86            BMIStatusReg status;
87            uint8_t reserved1;
88            uint32_t bmidtp;
89        } bmiRegs;
90
91        /** IDE disks connected to this controller */
92        IdeDisk *master, *slave;
93
94        /** Currently selected disk */
95        IdeDisk *selected;
96
97        bool selectBit;
98
99        void
100        select(bool selSlave)
101        {
102            selectBit = selSlave;
103            selected = selectBit ? slave : master;
104        }
105
106        void accessCommand(Addr offset, int size, uint8_t *data, bool read);
107        void accessControl(Addr offset, int size, uint8_t *data, bool read);
108        void accessBMI(Addr offset, int size, uint8_t *data, bool read);
109
110        Channel(std::string newName, Addr _cmdSize, Addr _ctrlSize);
111        ~Channel();
112
113        void serialize(const std::string &base, std::ostream &os) const;
114        void unserialize(const std::string &base, CheckpointIn &cp);
115    };
116
117    Channel primary;
118    Channel secondary;
119
120    /** Bus master interface (BMI) registers */
121    Addr bmiAddr, bmiSize;
122
123    /** Registers used in device specific PCI configuration */
124    uint16_t primaryTiming, secondaryTiming;
125    uint8_t deviceTiming;
126    uint8_t udmaControl;
127    uint16_t udmaTiming;
128    uint16_t ideConfig;
129
130    // Internal management variables
131    bool ioEnabled;
132    bool bmEnabled;
133
134    uint32_t ioShift, ctrlOffset;
135
136    void dispatchAccess(PacketPtr pkt, bool read);
137
138  public:
139    typedef IdeControllerParams Params;
140    const Params *params() const { return (const Params *)_params; }
141    IdeController(Params *p);
142
143    /** See if a disk is selected based on its pointer */
144    bool isDiskSelected(IdeDisk *diskPtr);
145
146    void intrPost();
147
148    Tick writeConfig(PacketPtr pkt) override;
149    Tick readConfig(PacketPtr pkt) override;
150
151    void setDmaComplete(IdeDisk *disk);
152
153    Tick read(PacketPtr pkt) override;
154    Tick write(PacketPtr pkt) override;
155
156    void serialize(CheckpointOut &cp) const override;
157    void unserialize(CheckpointIn &cp) override;
158};
159#endif // __DEV_STORAGE_IDE_CTRL_HH_
160