ide_ctrl.hh revision 929 
1/*
2 * Copyright (c) 2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Simple PCI IDE controller with bus mastering capability and UDMA
31 * modeled after controller in the Intel PIIX4 chip
32 */
33
34#ifndef __IDE_CTRL_HH__
35#define __IDE_CTRL_HH__
36
37#include "dev/pcidev.hh"
38#include "dev/pcireg.h"
39#include "dev/io_device.hh"
40
41#define BMIC0    0x0  // Bus master IDE command register
42#define BMIS0    0x2  // Bus master IDE status register
43#define BMIDTP0  0x4  // Bus master IDE descriptor table pointer register
44#define BMIC1    0x8  // Bus master IDE command register
45#define BMIS1    0xa  // Bus master IDE status register
46#define BMIDTP1  0xc  // Bus master IDE descriptor table pointer register
47
48// Bus master IDE command register bit fields
49#define RWCON 0x08 // Bus master read/write control
50#define SSBM  0x01 // Start/stop bus master
51
52// Bus master IDE status register bit fields
53#define DMA1CAP 0x40 // Drive 1 DMA capable
54#define DMA0CAP 0x20 // Drive 0 DMA capable
55#define IDEINTS 0x04 // IDE Interrupt Status
56#define IDEDMAE 0x02 // IDE DMA error
57#define BMIDEA  0x01 // Bus master IDE active
58
59// IDE Command byte fields
60#define IDE_SELECT_OFFSET       (6)
61#define IDE_SELECT_DEV_BIT      0x10
62
63#define IDE_FEATURE_OFFSET      IDE_ERROR_OFFSET
64#define IDE_COMMAND_OFFSET      IDE_STATUS_OFFSET
65
66// PCI device specific register byte offsets
67#define PCI_IDE_TIMING    0x40
68#define PCI_SLAVE_TIMING  0x44
69#define PCI_UDMA33_CTRL   0x48
70#define PCI_UDMA33_TIMING 0x4a
71
72#define IDETIM  (0)
73#define SIDETIM (4)
74#define UDMACTL (5)
75#define UDMATIM (6)
76
77typedef enum RegType {
78    COMMAND_BLOCK = 0,
79    CONTROL_BLOCK,
80    BMI_BLOCK
81} RegType_t;
82
83class IdeDisk;
84class IntrControl;
85class PciConfigAll;
86class Tsunami;
87class PhysicalMemory;
88class BaseInterface;
89class HierParams;
90class Bus;
91
92/**
93 * Device model for an Intel PIIX4 IDE controller
94 */
95
96class IdeController : public PciDev
97{
98  private:
99    /** Primary command block registers */
100    Addr pri_cmd_addr;
101    Addr pri_cmd_size;
102    /** Primary control block registers */
103    Addr pri_ctrl_addr;
104    Addr pri_ctrl_size;
105    /** Secondary command block registers */
106    Addr sec_cmd_addr;
107    Addr sec_cmd_size;
108    /** Secondary control block registers */
109    Addr sec_ctrl_addr;
110    Addr sec_ctrl_size;
111    /** Bus master interface (BMI) registers */
112    Addr bmi_addr;
113    Addr bmi_size;
114
115  private:
116    /** Registers used for bus master interface */
117    uint8_t bmi_regs[16];
118    /** Shadows of the device select bit */
119    uint8_t dev[2];
120    /** Registers used in PCI configuration */
121    uint8_t pci_regs[8];
122
123    // Internal management variables
124    bool io_enabled;
125    bool bm_enabled;
126    bool cmd_in_progress[4];
127
128  public:
129    /** Pointer to the chipset */
130    Tsunami *tsunami;
131
132  private:
133    /** IDE disks connected to controller */
134    IdeDisk *disks[4];
135
136  private:
137    /** Parse the access address to pass on to device */
138    void parseAddr(const Addr &addr, Addr &offset, bool &primary,
139                   RegType_t &type);
140
141    /** Select the disk based on the channel and device bit */
142    int getDisk(bool primary);
143
144    /** Select the disk based on a pointer */
145    int getDisk(IdeDisk *diskPtr);
146
147  public:
148    /** See if a disk is selected based on its pointer */
149    bool isDiskSelected(IdeDisk *diskPtr);
150
151  public:
152    /**
153     * Constructs and initializes this controller.
154     * @param name The name of this controller.
155     * @param ic The interrupt controller.
156     * @param mmu The memory controller
157     * @param cf PCI config space
158     * @param cd PCI config data
159     * @param bus_num The PCI bus number
160     * @param dev_num The PCI device number
161     * @param func_num The PCI function number
162     * @param host_bus The host bus to connect to
163     * @param hier The hierarchy parameters
164     */
165    IdeController(const std::string &name, IntrControl *ic,
166                  const std::vector<IdeDisk *> &new_disks,
167                  MemoryController *mmu, PciConfigAll *cf,
168                  PciConfigData *cd, Tsunami *t,
169                  uint32_t bus_num, uint32_t dev_num, uint32_t func_num,
170                  Bus *host_bus, HierParams *hier);
171
172    /**
173     * Deletes the connected devices.
174     */
175    ~IdeController();
176
177    virtual void WriteConfig(int offset, int size, uint32_t data);
178    virtual void ReadConfig(int offset, int size, uint8_t *data);
179
180    void intrPost();
181    void intrClear();
182
183    void setDmaComplete(IdeDisk *disk);
184
185    /**
186     * Read a done field for a given target.
187     * @param req Contains the address of the field to read.
188     * @param data Return the field read.
189     * @return The fault condition of the access.
190     */
191    virtual Fault read(MemReqPtr &req, uint8_t *data);
192
193    /**
194     * Write to the mmapped I/O control registers.
195     * @param req Contains the address to write to.
196     * @param data The data to write.
197     * @return The fault condition of the access.
198     */
199    virtual Fault write(MemReqPtr &req, const uint8_t *data);
200
201    /**
202     * Serialize this object to the given output stream.
203     * @param os The stream to serialize to.
204     */
205    virtual void serialize(std::ostream &os);
206
207    /**
208     * Reconstruct the state of this object from a checkpoint.
209     * @param cp The checkpoint use.
210     * @param section The section name of this object
211     */
212    virtual void unserialize(Checkpoint *cp, const std::string &section);
213
214    /**
215     * Return how long this access will take.
216     * @param req the memory request to calcuate
217     * @return Tick when the request is done
218     */
219    Tick cacheAccess(MemReqPtr &req);
220};
221#endif // __IDE_CTRL_HH_
222