ide_ctrl.hh revision 848 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Simple PCI IDE controller with bus mastering capability
31 */
32
33#ifndef __IDE_CTRL_HH__
34#define __IDE_CTRL_HH__
35
36#include "dev/pcidev.hh"
37#include "dev/pcireg.h"
38#include "dev/io_device.hh"
39
40#define CMD0  0x00 // Channel 0 command block offset
41#define CTRL0 0x08 // Channel 0 control block offset
42#define CMD1  0x0c // Channel 1 command block offset
43#define CTRL1 0x14 // Channel 1 control block offset
44#define BMI   0x18 // Bus master IDE offset
45
46#define BMIC0    0x0  // Bus master IDE command register
47#define BMIS0    0x2  // Bus master IDE status register
48#define BMIDTP0  0x4  // Bus master IDE descriptor table pointer register
49#define BMIC1    0x8  // Bus master IDE command register
50#define BMIS1    0xa  // Bus master IDE status register
51#define BMIDTP1  0xc  // Bus master IDE descriptor table pointer register
52
53// Bus master IDE command register bit fields
54#define RWCON 0x08 // Bus master read/write control
55#define SSBM  0x01 // Start/stop bus master
56
57// Bus master IDE status register bit fields
58#define DMA1CAP 0x40 // Drive 1 DMA capable
59#define DMA0CAP 0x20 // Drive 0 DMA capable
60#define IDEINTS 0x04 // IDE Interrupt Status
61#define IDEDMAE 0x02 // IDE DMA error
62#define BMIDEA  0x01 // Bus master IDE active
63
64// IDE Command byte fields
65// Taken from include/linux/ide.h
66#define IDE_DATA_OFFSET         (0)
67#define IDE_ERROR_OFFSET        (1)
68#define IDE_NSECTOR_OFFSET      (2)
69#define IDE_SECTOR_OFFSET       (3)
70#define IDE_LCYL_OFFSET         (4)
71#define IDE_HCYL_OFFSET         (5)
72#define IDE_SELECT_OFFSET       (6)
73#define IDE_STATUS_OFFSET       (7)
74#define IDE_CONTROL_OFFSET      (8)
75#define IDE_IRQ_OFFSET          (9)
76
77#define IDE_FEATURE_OFFSET      IDE_ERROR_OFFSET
78#define IDE_COMMAND_OFFSET      IDE_STATUS_OFFSET
79
80// PCI device specific register byte offsets
81#define PCI_IDE_TIMING    0x40
82#define PCI_SLAVE_TIMING  0x44
83#define PCI_UDMA33_CTRL   0x48
84#define PCI_UDMA33_TIMING 0x4a
85
86#define IDETIM  (0)
87#define SIDETIM (4)
88#define UDMACTL (5)
89#define UDMATIM (6)
90
91// PCI Command bit fields
92#define BME     0x04 // Bus master function enable
93#define IOSE    0x01 // I/O space enable
94
95class IntrControl;
96class IdeDisk;
97class PciConfigAll;
98class Tsunami;
99class PhysicalMemory;
100class BaseInterface;
101class HierParams;
102class Bus;
103
104/**
105 * Device model for an Intel PIIX4 IDE controller
106 */
107
108class IdeController : public PciDev
109{
110  private:
111    /** Primary command block registers */
112    Addr pri_cmd_addr;
113    Addr pri_cmd_size;
114    /** Primary control block registers */
115    Addr pri_ctrl_addr;
116    Addr pri_ctrl_size;
117    /** Secondary command block registers */
118    Addr sec_cmd_addr;
119    Addr sec_cmd_size;
120    /** Secondary control block registers */
121    Addr sec_ctrl_addr;
122    Addr sec_ctrl_size;
123    /** Bus master interface (BMI) registers */
124    Addr bmi_addr;
125    Addr bmi_size;
126
127  private:
128    /** Registers used for programmed I/O and bus master interface */
129    uint8_t regs[40];
130    /** Registers used in PCI configuration */
131    uint8_t pci_regs[8];
132
133    // Internal management variables
134    bool io_enabled;
135    bool bm_enabled;
136    bool cmd_in_progress[4];
137
138  private:
139    /** Pointer to the chipset */
140    Tsunami *tsunami;
141    /** IDE disks connected to controller */
142    IdeDisk *disks[4];
143
144  private:
145    /** Get offset into register file from access address */
146    Addr getOffset(const Addr &addr) {
147        Addr offset = addr;
148
149        if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
150            offset -= pri_cmd_addr;
151            offset += CMD0;
152        } else if (addr >= pri_ctrl_addr &&
153                   addr < (pri_ctrl_addr + pri_ctrl_size)) {
154            offset -= pri_ctrl_addr;
155            offset += CTRL0;
156        } else if (addr >= sec_cmd_addr &&
157                   addr < (sec_cmd_addr + sec_cmd_size)) {
158            offset -= sec_cmd_addr;
159            offset += CMD1;
160        } else if (addr >= sec_ctrl_addr &&
161                   addr < (sec_ctrl_addr + sec_ctrl_size)) {
162            offset -= sec_ctrl_addr;
163            offset += CTRL1;
164        } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
165            offset -= bmi_addr;
166            offset += BMI;
167        } else {
168            panic("IDE controller access to invalid address: %#x\n", addr);
169        }
170
171        return offset;
172    };
173    /** Select the disk based on the register offset */
174    int getDisk(const Addr &offset) {
175        int disk = 0;
176
177        // If the offset is in the channel 1 range, disks are 2 or 3
178        if (offset >= CMD1 && offset < BMI && offset >= (BMI + BMIC1))
179            disk += 2;
180
181        if (disk < 2) {
182            if (regs[CMD0 + IDE_STATUS_OFFSET] & 0x10)
183                disk += 1;
184        } else {
185            if (regs[CMD1 + IDE_STATUS_OFFSET] & 0x10)
186                disk += 1;
187        }
188
189        return disk;
190    };
191
192  public:
193    /**
194     * Constructs and initializes this controller.
195     * @param name The name of this controller.
196     * @param ic The interrupt controller.
197     * @param mmu The memory controller
198     * @param cf PCI config space
199     * @param cd PCI config data
200     * @param bus_num The PCI bus number
201     * @param dev_num The PCI device number
202     * @param func_num The PCI function number
203     * @param host_bus The host bus to connect to
204     * @param hier The hierarchy parameters
205     */
206    IdeController(const std::string &name, IntrControl *ic,
207                  const vector<IdeDisk *> &new_disks,
208                  MemoryController *mmu, PciConfigAll *cf,
209                  PciConfigData *cd, Tsunami *t,
210                  uint32_t bus_num, uint32_t dev_num, uint32_t func_num,
211                  Bus *host_bus, HierParams *hier);
212
213    /**
214     * Deletes the connected devices.
215     */
216    ~IdeController();
217
218    virtual void WriteConfig(int offset, int size, uint32_t data);
219    virtual void ReadConfig(int offset, int size, uint8_t *data);
220
221    /**
222     * Read a done field for a given target.
223     * @param req Contains the address of the field to read.
224     * @param data Return the field read.
225     * @return The fault condition of the access.
226     */
227    virtual Fault read(MemReqPtr &req, uint8_t *data);
228
229    /**
230     * Write to the mmapped I/O control registers.
231     * @param req Contains the address to write to.
232     * @param data The data to write.
233     * @return The fault condition of the access.
234     */
235    virtual Fault write(MemReqPtr &req, const uint8_t *data);
236
237    /**
238     * Cache access timing specific to device
239     * @param req Memory request
240     */
241    Tick cacheAccess(MemReqPtr &req);
242
243    /**
244     * Serialize this object to the given output stream.
245     * @param os The stream to serialize to.
246     */
247    virtual void serialize(std::ostream &os);
248
249    /**
250     * Reconstruct the state of this object from a checkpoint.
251     * @param cp The checkpoint use.
252     * @param section The section name of this object
253     */
254    virtual void unserialize(Checkpoint *cp, const std::string &section);
255
256};
257#endif // __IDE_CTRL_HH_
258