ide_ctrl.hh revision 2665 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Andrew Schultz
29 *          Miguel Serrano
30 */
31
32/** @file
33 * Simple PCI IDE controller with bus mastering capability and UDMA
34 * modeled after controller in the Intel PIIX4 chip
35 */
36
37#ifndef __IDE_CTRL_HH__
38#define __IDE_CTRL_HH__
39
40#include "dev/pcidev.hh"
41#include "dev/pcireg.h"
42#include "dev/io_device.hh"
43
44#define BMIC0    0x0  // Bus master IDE command register
45#define BMIS0    0x2  // Bus master IDE status register
46#define BMIDTP0  0x4  // Bus master IDE descriptor table pointer register
47#define BMIC1    0x8  // Bus master IDE command register
48#define BMIS1    0xa  // Bus master IDE status register
49#define BMIDTP1  0xc  // Bus master IDE descriptor table pointer register
50
51// Bus master IDE command register bit fields
52#define RWCON 0x08 // Bus master read/write control
53#define SSBM  0x01 // Start/stop bus master
54
55// Bus master IDE status register bit fields
56#define DMA1CAP 0x40 // Drive 1 DMA capable
57#define DMA0CAP 0x20 // Drive 0 DMA capable
58#define IDEINTS 0x04 // IDE Interrupt Status
59#define IDEDMAE 0x02 // IDE DMA error
60#define BMIDEA  0x01 // Bus master IDE active
61
62// IDE Command byte fields
63#define IDE_SELECT_OFFSET       (6)
64#define IDE_SELECT_DEV_BIT      0x10
65
66#define IDE_FEATURE_OFFSET      IDE_ERROR_OFFSET
67#define IDE_COMMAND_OFFSET      IDE_STATUS_OFFSET
68
69// IDE Timing Register bit fields
70#define IDETIM_DECODE_EN 0x8000
71
72// PCI device specific register byte offsets
73#define IDE_CTRL_CONF_START 0x40
74#define IDE_CTRL_CONF_END ((IDE_CTRL_CONF_START) + sizeof(config_regs))
75
76#define IDE_CTRL_CONF_PRIM_TIMING   0x40
77#define IDE_CTRL_CONF_SEC_TIMING    0x42
78#define IDE_CTRL_CONF_DEV_TIMING    0x44
79#define IDE_CTRL_CONF_UDMA_CNTRL    0x48
80#define IDE_CTRL_CONF_UDMA_TIMING   0x4A
81#define IDE_CTRL_CONF_IDE_CONFIG    0x54
82
83
84enum IdeRegType {
85    COMMAND_BLOCK,
86    CONTROL_BLOCK,
87    BMI_BLOCK
88};
89
90class IdeDisk;
91class IntrControl;
92class PciConfigAll;
93class Platform;
94
95/**
96 * Device model for an Intel PIIX4 IDE controller
97 */
98
99class IdeController : public PciDev
100{
101    friend class IdeDisk;
102
103    enum IdeChannel {
104        PRIMARY = 0,
105        SECONDARY = 1
106    };
107
108  private:
109    /** Primary command block registers */
110    Addr pri_cmd_addr;
111    Addr pri_cmd_size;
112    /** Primary control block registers */
113    Addr pri_ctrl_addr;
114    Addr pri_ctrl_size;
115    /** Secondary command block registers */
116    Addr sec_cmd_addr;
117    Addr sec_cmd_size;
118    /** Secondary control block registers */
119    Addr sec_ctrl_addr;
120    Addr sec_ctrl_size;
121    /** Bus master interface (BMI) registers */
122    Addr bmi_addr;
123    Addr bmi_size;
124
125  private:
126    /** Registers used for bus master interface */
127    union {
128        uint8_t data[16];
129
130        struct {
131            uint8_t bmic0;
132            uint8_t reserved_0;
133            uint8_t bmis0;
134            uint8_t reserved_1;
135            uint32_t bmidtp0;
136            uint8_t bmic1;
137            uint8_t reserved_2;
138            uint8_t bmis1;
139            uint8_t reserved_3;
140            uint32_t bmidtp1;
141        };
142
143        struct {
144            uint8_t bmic;
145            uint8_t reserved_4;
146            uint8_t bmis;
147            uint8_t reserved_5;
148            uint32_t bmidtp;
149        } chan[2];
150
151    } bmi_regs;
152    /** Shadows of the device select bit */
153    uint8_t dev[2];
154    /** Registers used in device specific PCI configuration */
155    union {
156        uint8_t data[22];
157
158        struct {
159            uint16_t idetim0;
160            uint16_t idetim1;
161            uint8_t sidetim;
162            uint8_t reserved_0[3];
163            uint8_t udmactl;
164            uint8_t reserved_1;
165            uint16_t udmatim;
166            uint8_t reserved_2[8];
167            uint16_t ideconfig;
168        };
169    } config_regs;
170
171    // Internal management variables
172    bool io_enabled;
173    bool bm_enabled;
174    bool cmd_in_progress[4];
175
176  private:
177    /** IDE disks connected to controller */
178    IdeDisk *disks[4];
179
180  private:
181    /** Parse the access address to pass on to device */
182    void parseAddr(const Addr &addr, Addr &offset, IdeChannel &channel,
183                   IdeRegType &reg_type);
184
185    /** Select the disk based on the channel and device bit */
186    int getDisk(IdeChannel channel);
187
188    /** Select the disk based on a pointer */
189    int getDisk(IdeDisk *diskPtr);
190
191  public:
192    /** See if a disk is selected based on its pointer */
193    bool isDiskSelected(IdeDisk *diskPtr);
194
195  public:
196    struct Params : public PciDev::Params
197    {
198        /** Array of disk objects */
199        std::vector<IdeDisk *> disks;
200    };
201    const Params *params() const { return (const Params *)_params; }
202
203  public:
204    IdeController(Params *p);
205    ~IdeController();
206
207    virtual void writeConfig(int offset, const uint8_t data);
208    virtual void writeConfig(int offset, const uint16_t data);
209    virtual void writeConfig(int offset, const uint32_t data);
210    virtual void readConfig(int offset, uint8_t *data);
211    virtual void readConfig(int offset, uint16_t *data);
212    virtual void readConfig(int offset, uint32_t *data);
213
214    void setDmaComplete(IdeDisk *disk);
215
216    /**
217     * Read a done field for a given target.
218     * @param pkt Packet describing what is to be read
219     * @return The amount of time to complete this request
220     */
221    virtual Tick read(Packet *pkt);
222
223    /**
224     * Write a done field for a given target.
225     * @param pkt Packet describing what is to be written
226     * @return The amount of time to complete this request
227     */
228    virtual Tick write(Packet *pkt);
229
230    /**
231     * Serialize this object to the given output stream.
232     * @param os The stream to serialize to.
233     */
234    virtual void serialize(std::ostream &os);
235
236    /**
237     * Reconstruct the state of this object from a checkpoint.
238     * @param cp The checkpoint use.
239     * @param section The section name of this object
240     */
241    virtual void unserialize(Checkpoint *cp, const std::string &section);
242
243};
244#endif // __IDE_CTRL_HH_
245