ide_ctrl.hh revision 1149 
1/*
2 * Copyright (c) 2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Simple PCI IDE controller with bus mastering capability and UDMA
31 * modeled after controller in the Intel PIIX4 chip
32 */
33
34#ifndef __IDE_CTRL_HH__
35#define __IDE_CTRL_HH__
36
37#include "dev/pcidev.hh"
38#include "dev/pcireg.h"
39#include "dev/io_device.hh"
40
41#define BMIC0    0x0  // Bus master IDE command register
42#define BMIS0    0x2  // Bus master IDE status register
43#define BMIDTP0  0x4  // Bus master IDE descriptor table pointer register
44#define BMIC1    0x8  // Bus master IDE command register
45#define BMIS1    0xa  // Bus master IDE status register
46#define BMIDTP1  0xc  // Bus master IDE descriptor table pointer register
47
48// Bus master IDE command register bit fields
49#define RWCON 0x08 // Bus master read/write control
50#define SSBM  0x01 // Start/stop bus master
51
52// Bus master IDE status register bit fields
53#define DMA1CAP 0x40 // Drive 1 DMA capable
54#define DMA0CAP 0x20 // Drive 0 DMA capable
55#define IDEINTS 0x04 // IDE Interrupt Status
56#define IDEDMAE 0x02 // IDE DMA error
57#define BMIDEA  0x01 // Bus master IDE active
58
59// IDE Command byte fields
60#define IDE_SELECT_OFFSET       (6)
61#define IDE_SELECT_DEV_BIT      0x10
62
63#define IDE_FEATURE_OFFSET      IDE_ERROR_OFFSET
64#define IDE_COMMAND_OFFSET      IDE_STATUS_OFFSET
65
66// PCI device specific register byte offsets
67#define PCI_IDE_TIMING    0x40
68#define PCI_SLAVE_TIMING  0x44
69#define PCI_UDMA33_CTRL   0x48
70#define PCI_UDMA33_TIMING 0x4a
71
72#define IDETIM  (0)
73#define SIDETIM (4)
74#define UDMACTL (5)
75#define UDMATIM (6)
76
77typedef enum RegType {
78    COMMAND_BLOCK = 0,
79    CONTROL_BLOCK,
80    BMI_BLOCK
81} RegType_t;
82
83class BaseInterface;
84class Bus;
85class HierParams;
86class IdeDisk;
87class IntrControl;
88class PciConfigAll;
89class PhysicalMemory;
90class Platform;
91
92/**
93 * Device model for an Intel PIIX4 IDE controller
94 */
95
96class IdeController : public PciDev
97{
98    friend class IdeDisk;
99
100  private:
101    /** Primary command block registers */
102    Addr pri_cmd_addr;
103    Addr pri_cmd_size;
104    /** Primary control block registers */
105    Addr pri_ctrl_addr;
106    Addr pri_ctrl_size;
107    /** Secondary command block registers */
108    Addr sec_cmd_addr;
109    Addr sec_cmd_size;
110    /** Secondary control block registers */
111    Addr sec_ctrl_addr;
112    Addr sec_ctrl_size;
113    /** Bus master interface (BMI) registers */
114    Addr bmi_addr;
115    Addr bmi_size;
116
117  private:
118    /** Registers used for bus master interface */
119    uint8_t bmi_regs[16];
120    /** Shadows of the device select bit */
121    uint8_t dev[2];
122    /** Registers used in PCI configuration */
123    uint8_t pci_regs[8];
124
125    // Internal management variables
126    bool io_enabled;
127    bool bm_enabled;
128    bool cmd_in_progress[4];
129
130  private:
131    /** IDE disks connected to controller */
132    IdeDisk *disks[4];
133
134  private:
135    /** Parse the access address to pass on to device */
136    void parseAddr(const Addr &addr, Addr &offset, bool &primary,
137                   RegType_t &type);
138
139    /** Select the disk based on the channel and device bit */
140    int getDisk(bool primary);
141
142    /** Select the disk based on a pointer */
143    int getDisk(IdeDisk *diskPtr);
144
145  public:
146    /** See if a disk is selected based on its pointer */
147    bool isDiskSelected(IdeDisk *diskPtr);
148
149  public:
150    struct Params : public PciDev::Params
151    {
152        /** Array of disk objects */
153        std::vector<IdeDisk *> disks;
154        Bus *host_bus;
155        Tick pio_latency;
156        HierParams *hier;
157    };
158    const Params *params() const { return (const Params *)_params; }
159
160  public:
161    IdeController(Params *p);
162    ~IdeController();
163
164    virtual void WriteConfig(int offset, int size, uint32_t data);
165    virtual void ReadConfig(int offset, int size, uint8_t *data);
166
167    void intrPost();
168    void intrClear();
169
170    void setDmaComplete(IdeDisk *disk);
171
172    /**
173     * Read a done field for a given target.
174     * @param req Contains the address of the field to read.
175     * @param data Return the field read.
176     * @return The fault condition of the access.
177     */
178    virtual Fault read(MemReqPtr &req, uint8_t *data);
179
180    /**
181     * Write to the mmapped I/O control registers.
182     * @param req Contains the address to write to.
183     * @param data The data to write.
184     * @return The fault condition of the access.
185     */
186    virtual Fault write(MemReqPtr &req, const uint8_t *data);
187
188    /**
189     * Serialize this object to the given output stream.
190     * @param os The stream to serialize to.
191     */
192    virtual void serialize(std::ostream &os);
193
194    /**
195     * Reconstruct the state of this object from a checkpoint.
196     * @param cp The checkpoint use.
197     * @param section The section name of this object
198     */
199    virtual void unserialize(Checkpoint *cp, const std::string &section);
200
201    /**
202     * Return how long this access will take.
203     * @param req the memory request to calcuate
204     * @return Tick when the request is done
205     */
206    Tick cacheAccess(MemReqPtr &req);
207};
208#endif // __IDE_CTRL_HH_
209