ide_ctrl.cc revision 897
11142Shsul@eecs.umich.edu/* 21142Shsul@eecs.umich.edu * Copyright (c) 2003 The Regents of The University of Michigan 31142Shsul@eecs.umich.edu * All rights reserved. 41142Shsul@eecs.umich.edu * 51142Shsul@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 61142Shsul@eecs.umich.edu * modification, are permitted provided that the following conditions are 71142Shsul@eecs.umich.edu * met: redistributions of source code must retain the above copyright 81142Shsul@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 91142Shsul@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 101142Shsul@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 111142Shsul@eecs.umich.edu * documentation and/or other materials provided with the distribution; 121142Shsul@eecs.umich.edu * neither the name of the copyright holders nor the names of its 131142Shsul@eecs.umich.edu * contributors may be used to endorse or promote products derived from 141142Shsul@eecs.umich.edu * this software without specific prior written permission. 151142Shsul@eecs.umich.edu * 161142Shsul@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171142Shsul@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181142Shsul@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191142Shsul@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201142Shsul@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211175Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221142Shsul@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231142Shsul@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241142Shsul@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251142Shsul@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261175Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271142Shsul@eecs.umich.edu */ 281142Shsul@eecs.umich.edu 291142Shsul@eecs.umich.edu#include <cstddef> 301142Shsul@eecs.umich.edu#include <cstdlib> 311175Sbinkertn@umich.edu#include <string> 321142Shsul@eecs.umich.edu#include <vector> 331142Shsul@eecs.umich.edu 341142Shsul@eecs.umich.edu#include "base/trace.hh" 351142Shsul@eecs.umich.edu#include "cpu/intr_control.hh" 361142Shsul@eecs.umich.edu#include "dev/dma.hh" 371142Shsul@eecs.umich.edu#include "dev/pcireg.h" 381142Shsul@eecs.umich.edu#include "dev/pciconfigall.hh" 391142Shsul@eecs.umich.edu#include "dev/ide_disk.hh" 401177Sbinkertn@umich.edu#include "dev/ide_ctrl.hh" 411142Shsul@eecs.umich.edu#include "dev/tsunami_cchip.hh" 421142Shsul@eecs.umich.edu#include "mem/bus/bus.hh" 431142Shsul@eecs.umich.edu#include "mem/bus/pio_interface.hh" 441142Shsul@eecs.umich.edu#include "mem/bus/pio_interface_impl.hh" 451142Shsul@eecs.umich.edu#include "mem/bus/dma_interface.hh" 461142Shsul@eecs.umich.edu#include "dev/tsunami.hh" 471142Shsul@eecs.umich.edu#include "mem/functional_mem/memory_control.hh" 48#include "mem/functional_mem/physical_memory.hh" 49#include "sim/builder.hh" 50#include "sim/sim_object.hh" 51 52using namespace std; 53 54//// 55// Initialization and destruction 56//// 57 58IdeController::IdeController(const string &name, IntrControl *ic, 59 const vector<IdeDisk *> &new_disks, 60 MemoryController *mmu, PciConfigAll *cf, 61 PciConfigData *cd, Tsunami *t, uint32_t bus_num, 62 uint32_t dev_num, uint32_t func_num, 63 Bus *host_bus, HierParams *hier) 64 : PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t) 65{ 66 // put back pointer into Tsunami 67 tsunami->disk_controller = this; 68 69 // initialize the PIO interface addresses 70 pri_cmd_addr = 0; 71 pri_cmd_size = BARSize[0]; 72 73 pri_ctrl_addr = 0; 74 pri_ctrl_size = BARSize[1]; 75 76 sec_cmd_addr = 0; 77 sec_cmd_size = BARSize[2]; 78 79 sec_ctrl_addr = 0; 80 sec_ctrl_size = BARSize[3]; 81 82 // initialize the bus master interface (BMI) address to be configured 83 // via PCI 84 bmi_addr = 0; 85 bmi_size = BARSize[4]; 86 87 // zero out all of the registers 88 memset(bmi_regs, 0, sizeof(bmi_regs)); 89 memset(pci_regs, 0, sizeof(pci_regs)); 90 91 // setup initial values 92 *(uint32_t *)&pci_regs[IDETIM] = 0x80008000; // enable both channels 93 *(uint8_t *)&bmi_regs[BMIS0] = 0x60; 94 *(uint8_t *)&bmi_regs[BMIS1] = 0x60; 95 96 // reset all internal variables 97 io_enabled = false; 98 bm_enabled = false; 99 memset(cmd_in_progress, 0, sizeof(cmd_in_progress)); 100 101 // create the PIO and DMA interfaces 102 if (host_bus) { 103 pioInterface = newPioInterface(name, hier, host_bus, this, 104 &IdeController::cacheAccess); 105 106 dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus, 107 host_bus, 1); 108 } 109 110 // setup the disks attached to controller 111 memset(disks, 0, sizeof(IdeDisk *) * 4); 112 113 if (new_disks.size() > 3) 114 panic("IDE controllers support a maximum of 4 devices attached!\n"); 115 116 for (int i = 0; i < new_disks.size(); i++) { 117 disks[i] = new_disks[i]; 118 disks[i]->setController(this, dmaInterface); 119 } 120} 121 122IdeController::~IdeController() 123{ 124 for (int i = 0; i < 4; i++) 125 if (disks[i]) 126 delete disks[i]; 127} 128 129//// 130// Utility functions 131/// 132 133void 134IdeController::parseAddr(const Addr &addr, Addr &offset, bool &primary, 135 RegType_t &type) 136{ 137 offset = addr; 138 139 if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) { 140 offset -= pri_cmd_addr; 141 type = COMMAND_BLOCK; 142 primary = true; 143 } else if (addr >= pri_ctrl_addr && 144 addr < (pri_ctrl_addr + pri_ctrl_size)) { 145 offset -= pri_ctrl_addr; 146 type = CONTROL_BLOCK; 147 primary = true; 148 } else if (addr >= sec_cmd_addr && 149 addr < (sec_cmd_addr + sec_cmd_size)) { 150 offset -= sec_cmd_addr; 151 type = COMMAND_BLOCK; 152 primary = false; 153 } else if (addr >= sec_ctrl_addr && 154 addr < (sec_ctrl_addr + sec_ctrl_size)) { 155 offset -= sec_ctrl_addr; 156 type = CONTROL_BLOCK; 157 primary = false; 158 } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) { 159 offset -= bmi_addr; 160 type = BMI_BLOCK; 161 primary = (offset < BMIC1) ? true : false; 162 } else { 163 panic("IDE controller access to invalid address: %#x\n", addr); 164 } 165} 166 167int 168IdeController::getDisk(bool primary) 169{ 170 int disk = 0; 171 uint8_t *devBit = &dev[0]; 172 173 if (!primary) { 174 disk += 2; 175 devBit = &dev[1]; 176 } 177 178 disk += *devBit; 179 180 assert(*devBit == 0 || *devBit == 1); 181 182 return disk; 183} 184 185int 186IdeController::getDisk(IdeDisk *diskPtr) 187{ 188 for (int i = 0; i < 4; i++) { 189 if ((long)diskPtr == (long)disks[i]) 190 return i; 191 } 192 return -1; 193} 194 195//// 196// Command completion 197//// 198 199void 200IdeController::setDmaComplete(IdeDisk *disk) 201{ 202 int diskNum = getDisk(disk); 203 204 if (diskNum < 0) 205 panic("Unable to find disk based on pointer %#x\n", disk); 206 207 if (diskNum < 2) { 208 // clear the start/stop bit in the command register 209 bmi_regs[BMIC0] &= ~SSBM; 210 // clear the bus master active bit in the status register 211 bmi_regs[BMIS0] &= ~BMIDEA; 212 // set the interrupt bit 213 bmi_regs[BMIS0] |= IDEINTS; 214 } else { 215 // clear the start/stop bit in the command register 216 bmi_regs[BMIC1] &= ~SSBM; 217 // clear the bus master active bit in the status register 218 bmi_regs[BMIS1] &= ~BMIDEA; 219 // set the interrupt bit 220 bmi_regs[BMIS1] |= IDEINTS; 221 } 222} 223 224//// 225// Interrupt handling 226//// 227 228void 229IdeController::intrPost() 230{ 231 tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine); 232} 233 234void 235IdeController::intrClear() 236{ 237 tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine); 238} 239 240//// 241// Bus timing and bus access functions 242//// 243 244Tick 245IdeController::cacheAccess(MemReqPtr &req) 246{ 247 // @todo Add more accurate timing to cache access 248 return curTick + 1000; 249} 250 251//// 252// Read and write handling 253//// 254 255void 256IdeController::ReadConfig(int offset, int size, uint8_t *data) 257{ 258 Addr origOffset = offset; 259 260 if (offset < PCI_DEVICE_SPECIFIC) { 261 PciDev::ReadConfig(offset, size, data); 262 } else { 263 if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) { 264 offset -= PCI_IDE_TIMING; 265 offset += IDETIM; 266 267 if ((offset + size) > (IDETIM + 4)) 268 panic("PCI read of IDETIM with invalid size\n"); 269 } else if (offset == PCI_SLAVE_TIMING) { 270 offset -= PCI_SLAVE_TIMING; 271 offset += SIDETIM; 272 273 if ((offset + size) > (SIDETIM + 1)) 274 panic("PCI read of SIDETIM with invalid size\n"); 275 } else if (offset == PCI_UDMA33_CTRL) { 276 offset -= PCI_UDMA33_CTRL; 277 offset += UDMACTL; 278 279 if ((offset + size) > (UDMACTL + 1)) 280 panic("PCI read of UDMACTL with invalid size\n"); 281 } else if (offset >= PCI_UDMA33_TIMING && 282 offset < (PCI_UDMA33_TIMING + 2)) { 283 offset -= PCI_UDMA33_TIMING; 284 offset += UDMATIM; 285 286 if ((offset + size) > (UDMATIM + 2)) 287 panic("PCI read of UDMATIM with invalid size\n"); 288 } else { 289 panic("PCI read of unimplemented register: %x\n", offset); 290 } 291 292 memcpy((void *)data, (void *)&pci_regs[offset], size); 293 } 294 295 DPRINTF(IdeCtrl, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n", 296 origOffset, offset, size, *(uint32_t *)data); 297} 298 299void 300IdeController::WriteConfig(int offset, int size, uint32_t data) 301{ 302 DPRINTF(IdeCtrl, "IDE PCI write offset: %#x size: %#x data: %#x\n", 303 offset, size, data); 304 305 // do standard write stuff if in standard PCI space 306 if (offset < PCI_DEVICE_SPECIFIC) { 307 PciDev::WriteConfig(offset, size, data); 308 } else { 309 if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) { 310 offset -= PCI_IDE_TIMING; 311 offset += IDETIM; 312 313 if ((offset + size) > (IDETIM + 4)) 314 panic("PCI write to IDETIM with invalid size\n"); 315 } else if (offset == PCI_SLAVE_TIMING) { 316 offset -= PCI_SLAVE_TIMING; 317 offset += SIDETIM; 318 319 if ((offset + size) > (SIDETIM + 1)) 320 panic("PCI write to SIDETIM with invalid size\n"); 321 } else if (offset == PCI_UDMA33_CTRL) { 322 offset -= PCI_UDMA33_CTRL; 323 offset += UDMACTL; 324 325 if ((offset + size) > (UDMACTL + 1)) 326 panic("PCI write to UDMACTL with invalid size\n"); 327 } else if (offset >= PCI_UDMA33_TIMING && 328 offset < (PCI_UDMA33_TIMING + 2)) { 329 offset -= PCI_UDMA33_TIMING; 330 offset += UDMATIM; 331 332 if ((offset + size) > (UDMATIM + 2)) 333 panic("PCI write to UDMATIM with invalid size\n"); 334 } else { 335 panic("PCI write to unimplemented register: %x\n", offset); 336 } 337 338 memcpy((void *)&pci_regs[offset], (void *)&data, size); 339 } 340 341 // Catch the writes to specific PCI registers that have side affects 342 // (like updating the PIO ranges) 343 switch (offset) { 344 case PCI_COMMAND: 345 if (config.data[offset] & IOSE) 346 io_enabled = true; 347 else 348 io_enabled = false; 349 350 if (config.data[offset] & BME) 351 bm_enabled = true; 352 else 353 bm_enabled = false; 354 break; 355 356 case PCI0_BASE_ADDR0: 357 if (BARAddrs[0] != 0) { 358 pri_cmd_addr = BARAddrs[0]; 359 if (pioInterface) 360 pioInterface->addAddrRange(pri_cmd_addr, 361 pri_cmd_addr + pri_cmd_size - 1); 362 363 pri_cmd_addr &= PA_UNCACHED_MASK; 364 } 365 break; 366 367 case PCI0_BASE_ADDR1: 368 if (BARAddrs[1] != 0) { 369 pri_ctrl_addr = BARAddrs[1]; 370 if (pioInterface) 371 pioInterface->addAddrRange(pri_ctrl_addr, 372 pri_ctrl_addr + pri_ctrl_size - 1); 373 374 pri_ctrl_addr &= PA_UNCACHED_MASK; 375 } 376 break; 377 378 case PCI0_BASE_ADDR2: 379 if (BARAddrs[2] != 0) { 380 sec_cmd_addr = BARAddrs[2]; 381 if (pioInterface) 382 pioInterface->addAddrRange(sec_cmd_addr, 383 sec_cmd_addr + sec_cmd_size - 1); 384 385 sec_cmd_addr &= PA_UNCACHED_MASK; 386 } 387 break; 388 389 case PCI0_BASE_ADDR3: 390 if (BARAddrs[3] != 0) { 391 sec_ctrl_addr = BARAddrs[3]; 392 if (pioInterface) 393 pioInterface->addAddrRange(sec_ctrl_addr, 394 sec_ctrl_addr + sec_ctrl_size - 1); 395 396 sec_ctrl_addr &= PA_UNCACHED_MASK; 397 } 398 break; 399 400 case PCI0_BASE_ADDR4: 401 if (BARAddrs[4] != 0) { 402 bmi_addr = BARAddrs[4]; 403 if (pioInterface) 404 pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1); 405 406 bmi_addr &= PA_UNCACHED_MASK; 407 } 408 break; 409 } 410} 411 412Fault 413IdeController::read(MemReqPtr &req, uint8_t *data) 414{ 415 Addr offset; 416 bool primary; 417 bool byte; 418 bool cmdBlk; 419 RegType_t type; 420 int disk; 421 422 parseAddr(req->paddr, offset, primary, type); 423 byte = (req->size == sizeof(uint8_t)) ? true : false; 424 cmdBlk = (type == COMMAND_BLOCK) ? true : false; 425 426 if (!io_enabled) 427 return No_Fault; 428 429 // sanity check the size (allows byte, word, or dword access) 430 if (req->size != sizeof(uint8_t) && req->size != sizeof(uint16_t) && 431 req->size != sizeof(uint32_t)) 432 panic("IDE controller read of invalid size: %#x\n", req->size); 433 434 if (type != BMI_BLOCK) { 435 assert(req->size != sizeof(uint32_t)); 436 437 disk = getDisk(primary); 438 if (disks[disk]) 439 disks[disk]->read(offset, byte, cmdBlk, data); 440 } else { 441 memcpy((void *)data, &bmi_regs[offset], req->size); 442 } 443 444 DPRINTF(IdeCtrl, "IDE read from offset: %#x size: %#x data: %#x\n", 445 offset, req->size, *(uint32_t *)data); 446 447 return No_Fault; 448} 449 450Fault 451IdeController::write(MemReqPtr &req, const uint8_t *data) 452{ 453 Addr offset; 454 bool primary; 455 bool byte; 456 bool cmdBlk; 457 RegType_t type; 458 int disk; 459 460 parseAddr(req->paddr, offset, primary, type); 461 byte = (req->size == sizeof(uint8_t)) ? true : false; 462 cmdBlk = (type == COMMAND_BLOCK) ? true : false; 463 464 DPRINTF(IdeCtrl, "IDE write from offset: %#x size: %#x data: %#x\n", 465 offset, req->size, *(uint32_t *)data); 466 467 uint8_t oldVal, newVal; 468 469 if (!io_enabled) 470 return No_Fault; 471 472 if (type == BMI_BLOCK && !bm_enabled) 473 return No_Fault; 474 475 if (type != BMI_BLOCK) { 476 // shadow the dev bit 477 if (type == COMMAND_BLOCK && offset == IDE_SELECT_OFFSET) { 478 uint8_t *devBit = (primary ? &dev[0] : &dev[1]); 479 *devBit = ((*data & IDE_SELECT_DEV_BIT) ? 1 : 0); 480 } 481 482 assert(req->size != sizeof(uint32_t)); 483 484 disk = getDisk(primary); 485 if (disks[disk]) 486 disks[disk]->write(offset, byte, cmdBlk, data); 487 } else { 488 switch (offset) { 489 // Bus master IDE command register 490 case BMIC1: 491 case BMIC0: 492 if (req->size != sizeof(uint8_t)) 493 panic("Invalid BMIC write size: %x\n", req->size); 494 495 // select the current disk based on DEV bit 496 disk = getDisk(primary); 497 498 oldVal = bmi_regs[offset]; 499 newVal = *data; 500 501 // if a DMA transfer is in progress, R/W control cannot change 502 if (oldVal & SSBM) { 503 if ((oldVal & RWCON) ^ (newVal & RWCON)) { 504 (oldVal & RWCON) ? newVal |= RWCON : newVal &= ~RWCON; 505 } 506 } 507 508 // see if the start/stop bit is being changed 509 if ((oldVal & SSBM) ^ (newVal & SSBM)) { 510 if (oldVal & SSBM) { 511 // stopping DMA transfer 512 DPRINTF(IdeCtrl, "Stopping DMA transfer\n"); 513 514 // clear the BMIDEA bit 515 bmi_regs[offset + 0x2] &= ~BMIDEA; 516 517 if (disks[disk] == NULL) 518 panic("DMA stop for disk %d which does not exist\n", 519 disk); 520 521 // inform the disk of the DMA transfer abort 522 disks[disk]->abortDma(); 523 } else { 524 // starting DMA transfer 525 DPRINTF(IdeCtrl, "Starting DMA transfer\n"); 526 527 // set the BMIDEA bit 528 bmi_regs[offset + 0x2] |= BMIDEA; 529 530 if (disks[disk] == NULL) 531 panic("DMA start for disk %d which does not exist\n", 532 disk); 533 534 // inform the disk of the DMA transfer start 535 if (primary) 536 disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP0]); 537 else 538 disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP1]); 539 } 540 } 541 542 // update the register value 543 bmi_regs[offset] = newVal; 544 break; 545 546 // Bus master IDE status register 547 case BMIS0: 548 case BMIS1: 549 if (req->size != sizeof(uint8_t)) 550 panic("Invalid BMIS write size: %x\n", req->size); 551 552 oldVal = bmi_regs[offset]; 553 newVal = *data; 554 555 // the BMIDEA bit is RO 556 newVal |= (oldVal & BMIDEA); 557 558 // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each 559 if ((oldVal & IDEINTS) && (newVal & IDEINTS)) 560 newVal &= ~IDEINTS; // clear the interrupt? 561 else 562 (oldVal & IDEINTS) ? newVal |= IDEINTS : newVal &= ~IDEINTS; 563 564 if ((oldVal & IDEDMAE) && (newVal & IDEDMAE)) 565 newVal &= ~IDEDMAE; 566 else 567 (oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE; 568 569 bmi_regs[offset] = newVal; 570 break; 571 572 // Bus master IDE descriptor table pointer register 573 case BMIDTP0: 574 case BMIDTP1: 575 if (req->size != sizeof(uint32_t)) 576 panic("Invalid BMIDTP write size: %x\n", req->size); 577 578 *(uint32_t *)&bmi_regs[offset] = *(uint32_t *)data & ~0x3; 579 break; 580 581 default: 582 if (req->size != sizeof(uint8_t) && 583 req->size != sizeof(uint16_t) && 584 req->size != sizeof(uint32_t)) 585 panic("IDE controller write of invalid write size: %x\n", 586 req->size); 587 588 // do a default copy of data into the registers 589 memcpy((void *)&bmi_regs[offset], data, req->size); 590 } 591 } 592 593 return No_Fault; 594} 595 596//// 597// Serialization 598//// 599 600void 601IdeController::serialize(std::ostream &os) 602{ 603 // Serialize the PciDev base class 604 PciDev::serialize(os); 605 606 // Serialize register addresses and sizes 607 SERIALIZE_SCALAR(pri_cmd_addr); 608 SERIALIZE_SCALAR(pri_cmd_size); 609 SERIALIZE_SCALAR(pri_ctrl_addr); 610 SERIALIZE_SCALAR(pri_ctrl_size); 611 SERIALIZE_SCALAR(sec_cmd_addr); 612 SERIALIZE_SCALAR(sec_cmd_size); 613 SERIALIZE_SCALAR(sec_ctrl_addr); 614 SERIALIZE_SCALAR(sec_ctrl_size); 615 SERIALIZE_SCALAR(bmi_addr); 616 SERIALIZE_SCALAR(bmi_size); 617 618 // Serialize registers 619 SERIALIZE_ARRAY(bmi_regs, 16); 620 SERIALIZE_ARRAY(dev, 2); 621 SERIALIZE_ARRAY(pci_regs, 8); 622 623 // Serialize internal state 624 SERIALIZE_SCALAR(io_enabled); 625 SERIALIZE_SCALAR(bm_enabled); 626 SERIALIZE_ARRAY(cmd_in_progress, 4); 627} 628 629void 630IdeController::unserialize(Checkpoint *cp, const std::string §ion) 631{ 632 // Unserialize the PciDev base class 633 PciDev::unserialize(cp, section); 634 635 // Unserialize register addresses and sizes 636 UNSERIALIZE_SCALAR(pri_cmd_addr); 637 UNSERIALIZE_SCALAR(pri_cmd_size); 638 UNSERIALIZE_SCALAR(pri_ctrl_addr); 639 UNSERIALIZE_SCALAR(pri_ctrl_size); 640 UNSERIALIZE_SCALAR(sec_cmd_addr); 641 UNSERIALIZE_SCALAR(sec_cmd_size); 642 UNSERIALIZE_SCALAR(sec_ctrl_addr); 643 UNSERIALIZE_SCALAR(sec_ctrl_size); 644 UNSERIALIZE_SCALAR(bmi_addr); 645 UNSERIALIZE_SCALAR(bmi_size); 646 647 // Unserialize registers 648 UNSERIALIZE_ARRAY(bmi_regs, 16); 649 UNSERIALIZE_ARRAY(dev, 2); 650 UNSERIALIZE_ARRAY(pci_regs, 8); 651 652 // Unserialize internal state 653 UNSERIALIZE_SCALAR(io_enabled); 654 UNSERIALIZE_SCALAR(bm_enabled); 655 UNSERIALIZE_ARRAY(cmd_in_progress, 4); 656} 657 658#ifndef DOXYGEN_SHOULD_SKIP_THIS 659 660BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController) 661 662 SimObjectParam<IntrControl *> intr_ctrl; 663 SimObjectVectorParam<IdeDisk *> disks; 664 SimObjectParam<MemoryController *> mmu; 665 SimObjectParam<PciConfigAll *> configspace; 666 SimObjectParam<PciConfigData *> configdata; 667 SimObjectParam<Tsunami *> tsunami; 668 Param<uint32_t> pci_bus; 669 Param<uint32_t> pci_dev; 670 Param<uint32_t> pci_func; 671 SimObjectParam<Bus *> host_bus; 672 SimObjectParam<HierParams *> hier; 673 674END_DECLARE_SIM_OBJECT_PARAMS(IdeController) 675 676BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController) 677 678 INIT_PARAM(intr_ctrl, "Interrupt Controller"), 679 INIT_PARAM(disks, "IDE disks attached to this controller"), 680 INIT_PARAM(mmu, "Memory controller"), 681 INIT_PARAM(configspace, "PCI Configspace"), 682 INIT_PARAM(configdata, "PCI Config data"), 683 INIT_PARAM(tsunami, "Tsunami chipset pointer"), 684 INIT_PARAM(pci_bus, "PCI bus ID"), 685 INIT_PARAM(pci_dev, "PCI device number"), 686 INIT_PARAM(pci_func, "PCI function code"), 687 INIT_PARAM_DFLT(host_bus, "Host bus to attach to", NULL), 688 INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) 689 690END_INIT_SIM_OBJECT_PARAMS(IdeController) 691 692CREATE_SIM_OBJECT(IdeController) 693{ 694 return new IdeController(getInstanceName(), intr_ctrl, disks, mmu, 695 configspace, configdata, tsunami, pci_bus, 696 pci_dev, pci_func, host_bus, hier); 697} 698 699REGISTER_SIM_OBJECT("IdeController", IdeController) 700 701#endif //DOXYGEN_SHOULD_SKIP_THIS 702