ide_ctrl.cc revision 1149
14776Sgblack@eecs.umich.edu/* 26365Sgblack@eecs.umich.edu * Copyright (c) 2004 The Regents of The University of Michigan 34776Sgblack@eecs.umich.edu * All rights reserved. 44776Sgblack@eecs.umich.edu * 54776Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64776Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 74776Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84776Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94776Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104776Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114776Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124776Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134776Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144776Sgblack@eecs.umich.edu * this software without specific prior written permission. 154776Sgblack@eecs.umich.edu * 164776Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174776Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184776Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194776Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204776Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214776Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224776Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234776Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244776Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254776Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264776Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274776Sgblack@eecs.umich.edu */ 286365Sgblack@eecs.umich.edu 294776Sgblack@eecs.umich.edu#include <cstddef> 304776Sgblack@eecs.umich.edu#include <cstdlib> 314776Sgblack@eecs.umich.edu#include <string> 324776Sgblack@eecs.umich.edu#include <vector> 334776Sgblack@eecs.umich.edu 344776Sgblack@eecs.umich.edu#include "base/trace.hh" 354776Sgblack@eecs.umich.edu#include "cpu/intr_control.hh" 364776Sgblack@eecs.umich.edu#include "dev/dma.hh" 374776Sgblack@eecs.umich.edu#include "dev/ide_ctrl.hh" 384776Sgblack@eecs.umich.edu#include "dev/ide_disk.hh" 394776Sgblack@eecs.umich.edu#include "dev/pciconfigall.hh" 405523Snate@binkert.org#include "dev/pcireg.h" 416409Sgblack@eecs.umich.edu#include "dev/platform.hh" 424776Sgblack@eecs.umich.edu#include "mem/bus/bus.hh" 435523Snate@binkert.org#include "mem/bus/dma_interface.hh" 445523Snate@binkert.org#include "mem/bus/pio_interface.hh" 455523Snate@binkert.org#include "mem/bus/pio_interface_impl.hh" 464776Sgblack@eecs.umich.edu#include "mem/functional_mem/memory_control.hh" 474776Sgblack@eecs.umich.edu#include "mem/functional_mem/physical_memory.hh" 484776Sgblack@eecs.umich.edu#include "sim/builder.hh" 494776Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 504776Sgblack@eecs.umich.edu 514776Sgblack@eecs.umich.eduusing namespace std; 524776Sgblack@eecs.umich.edu 534776Sgblack@eecs.umich.edu//// 545049Sgblack@eecs.umich.edu// Initialization and destruction 555049Sgblack@eecs.umich.edu//// 564776Sgblack@eecs.umich.edu 574776Sgblack@eecs.umich.eduIdeController::IdeController(Params *p) 584776Sgblack@eecs.umich.edu : PciDev(p) 594776Sgblack@eecs.umich.edu{ 604776Sgblack@eecs.umich.edu // initialize the PIO interface addresses 616365Sgblack@eecs.umich.edu pri_cmd_addr = 0; 626365Sgblack@eecs.umich.edu pri_cmd_size = BARSize[0]; 634830Sgblack@eecs.umich.edu 644830Sgblack@eecs.umich.edu pri_ctrl_addr = 0; 656365Sgblack@eecs.umich.edu pri_ctrl_size = BARSize[1]; 66 67 sec_cmd_addr = 0; 68 sec_cmd_size = BARSize[2]; 69 70 sec_ctrl_addr = 0; 71 sec_ctrl_size = BARSize[3]; 72 73 // initialize the bus master interface (BMI) address to be configured 74 // via PCI 75 bmi_addr = 0; 76 bmi_size = BARSize[4]; 77 78 // zero out all of the registers 79 memset(bmi_regs, 0, sizeof(bmi_regs)); 80 memset(pci_regs, 0, sizeof(pci_regs)); 81 82 // setup initial values 83 *(uint32_t *)&pci_regs[IDETIM] = 0x80008000; // enable both channels 84 *(uint8_t *)&bmi_regs[BMIS0] = 0x60; 85 *(uint8_t *)&bmi_regs[BMIS1] = 0x60; 86 87 // reset all internal variables 88 io_enabled = false; 89 bm_enabled = false; 90 memset(cmd_in_progress, 0, sizeof(cmd_in_progress)); 91 92 // create the PIO and DMA interfaces 93 if (params()->host_bus) { 94 pioInterface = newPioInterface(name(), params()->hier, 95 params()->host_bus, this, 96 &IdeController::cacheAccess); 97 98 dmaInterface = new DMAInterface<Bus>(name() + ".dma", 99 params()->host_bus, 100 params()->host_bus, 1); 101 pioLatency = params()->pio_latency * params()->host_bus->clockRatio; 102 } 103 104 // setup the disks attached to controller 105 memset(disks, 0, sizeof(IdeDisk *) * 4); 106 107 if (params()->disks.size() > 3) 108 panic("IDE controllers support a maximum of 4 devices attached!\n"); 109 110 for (int i = 0; i < params()->disks.size(); i++) { 111 disks[i] = params()->disks[i]; 112 disks[i]->setController(this, dmaInterface); 113 } 114} 115 116IdeController::~IdeController() 117{ 118 for (int i = 0; i < 4; i++) 119 if (disks[i]) 120 delete disks[i]; 121} 122 123//// 124// Utility functions 125/// 126 127void 128IdeController::parseAddr(const Addr &addr, Addr &offset, bool &primary, 129 RegType_t &type) 130{ 131 offset = addr; 132 133 if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) { 134 offset -= pri_cmd_addr; 135 type = COMMAND_BLOCK; 136 primary = true; 137 } else if (addr >= pri_ctrl_addr && 138 addr < (pri_ctrl_addr + pri_ctrl_size)) { 139 offset -= pri_ctrl_addr; 140 type = CONTROL_BLOCK; 141 primary = true; 142 } else if (addr >= sec_cmd_addr && 143 addr < (sec_cmd_addr + sec_cmd_size)) { 144 offset -= sec_cmd_addr; 145 type = COMMAND_BLOCK; 146 primary = false; 147 } else if (addr >= sec_ctrl_addr && 148 addr < (sec_ctrl_addr + sec_ctrl_size)) { 149 offset -= sec_ctrl_addr; 150 type = CONTROL_BLOCK; 151 primary = false; 152 } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) { 153 offset -= bmi_addr; 154 type = BMI_BLOCK; 155 primary = (offset < BMIC1) ? true : false; 156 } else { 157 panic("IDE controller access to invalid address: %#x\n", addr); 158 } 159} 160 161int 162IdeController::getDisk(bool primary) 163{ 164 int disk = 0; 165 uint8_t *devBit = &dev[0]; 166 167 if (!primary) { 168 disk += 2; 169 devBit = &dev[1]; 170 } 171 172 disk += *devBit; 173 174 assert(*devBit == 0 || *devBit == 1); 175 176 return disk; 177} 178 179int 180IdeController::getDisk(IdeDisk *diskPtr) 181{ 182 for (int i = 0; i < 4; i++) { 183 if ((long)diskPtr == (long)disks[i]) 184 return i; 185 } 186 return -1; 187} 188 189bool 190IdeController::isDiskSelected(IdeDisk *diskPtr) 191{ 192 for (int i = 0; i < 4; i++) { 193 if ((long)diskPtr == (long)disks[i]) { 194 // is disk is on primary or secondary channel 195 int channel = i/2; 196 // is disk the master or slave 197 int devID = i%2; 198 199 return (dev[channel] == devID); 200 } 201 } 202 panic("Unable to find disk by pointer!!\n"); 203} 204 205//// 206// Command completion 207//// 208 209void 210IdeController::setDmaComplete(IdeDisk *disk) 211{ 212 int diskNum = getDisk(disk); 213 214 if (diskNum < 0) 215 panic("Unable to find disk based on pointer %#x\n", disk); 216 217 if (diskNum < 2) { 218 // clear the start/stop bit in the command register 219 bmi_regs[BMIC0] &= ~SSBM; 220 // clear the bus master active bit in the status register 221 bmi_regs[BMIS0] &= ~BMIDEA; 222 // set the interrupt bit 223 bmi_regs[BMIS0] |= IDEINTS; 224 } else { 225 // clear the start/stop bit in the command register 226 bmi_regs[BMIC1] &= ~SSBM; 227 // clear the bus master active bit in the status register 228 bmi_regs[BMIS1] &= ~BMIDEA; 229 // set the interrupt bit 230 bmi_regs[BMIS1] |= IDEINTS; 231 } 232} 233 234//// 235// Bus timing and bus access functions 236//// 237 238Tick 239IdeController::cacheAccess(MemReqPtr &req) 240{ 241 // @todo Add more accurate timing to cache access 242 return curTick + pioLatency; 243} 244 245//// 246// Read and write handling 247//// 248 249void 250IdeController::ReadConfig(int offset, int size, uint8_t *data) 251{ 252 253#if TRACING_ON 254 Addr origOffset = offset; 255#endif 256 257 if (offset < PCI_DEVICE_SPECIFIC) { 258 PciDev::ReadConfig(offset, size, data); 259 } else { 260 if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) { 261 offset -= PCI_IDE_TIMING; 262 offset += IDETIM; 263 264 if ((offset + size) > (IDETIM + 4)) 265 panic("PCI read of IDETIM with invalid size\n"); 266 } else if (offset == PCI_SLAVE_TIMING) { 267 offset -= PCI_SLAVE_TIMING; 268 offset += SIDETIM; 269 270 if ((offset + size) > (SIDETIM + 1)) 271 panic("PCI read of SIDETIM with invalid size\n"); 272 } else if (offset == PCI_UDMA33_CTRL) { 273 offset -= PCI_UDMA33_CTRL; 274 offset += UDMACTL; 275 276 if ((offset + size) > (UDMACTL + 1)) 277 panic("PCI read of UDMACTL with invalid size\n"); 278 } else if (offset >= PCI_UDMA33_TIMING && 279 offset < (PCI_UDMA33_TIMING + 2)) { 280 offset -= PCI_UDMA33_TIMING; 281 offset += UDMATIM; 282 283 if ((offset + size) > (UDMATIM + 2)) 284 panic("PCI read of UDMATIM with invalid size\n"); 285 } else { 286 panic("PCI read of unimplemented register: %x\n", offset); 287 } 288 289 memcpy((void *)data, (void *)&pci_regs[offset], size); 290 } 291 292 DPRINTF(IdeCtrl, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n", 293 origOffset, offset, size, *(uint32_t *)data); 294} 295 296void 297IdeController::WriteConfig(int offset, int size, uint32_t data) 298{ 299 DPRINTF(IdeCtrl, "IDE PCI write offset: %#x size: %#x data: %#x\n", 300 offset, size, data); 301 302 // do standard write stuff if in standard PCI space 303 if (offset < PCI_DEVICE_SPECIFIC) { 304 PciDev::WriteConfig(offset, size, data); 305 } else { 306 if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) { 307 offset -= PCI_IDE_TIMING; 308 offset += IDETIM; 309 310 if ((offset + size) > (IDETIM + 4)) 311 panic("PCI write to IDETIM with invalid size\n"); 312 } else if (offset == PCI_SLAVE_TIMING) { 313 offset -= PCI_SLAVE_TIMING; 314 offset += SIDETIM; 315 316 if ((offset + size) > (SIDETIM + 1)) 317 panic("PCI write to SIDETIM with invalid size\n"); 318 } else if (offset == PCI_UDMA33_CTRL) { 319 offset -= PCI_UDMA33_CTRL; 320 offset += UDMACTL; 321 322 if ((offset + size) > (UDMACTL + 1)) 323 panic("PCI write to UDMACTL with invalid size\n"); 324 } else if (offset >= PCI_UDMA33_TIMING && 325 offset < (PCI_UDMA33_TIMING + 2)) { 326 offset -= PCI_UDMA33_TIMING; 327 offset += UDMATIM; 328 329 if ((offset + size) > (UDMATIM + 2)) 330 panic("PCI write to UDMATIM with invalid size\n"); 331 } else { 332 panic("PCI write to unimplemented register: %x\n", offset); 333 } 334 335 memcpy((void *)&pci_regs[offset], (void *)&data, size); 336 } 337 338 // Catch the writes to specific PCI registers that have side affects 339 // (like updating the PIO ranges) 340 switch (offset) { 341 case PCI_COMMAND: 342 if (config.data[offset] & PCI_CMD_IOSE) 343 io_enabled = true; 344 else 345 io_enabled = false; 346 347 if (config.data[offset] & PCI_CMD_BME) 348 bm_enabled = true; 349 else 350 bm_enabled = false; 351 break; 352 353 case PCI0_BASE_ADDR0: 354 if (BARAddrs[0] != 0) { 355 pri_cmd_addr = BARAddrs[0]; 356 if (pioInterface) 357 pioInterface->addAddrRange(RangeSize(pri_cmd_addr, 358 pri_cmd_size)); 359 360 pri_cmd_addr &= EV5::PAddrUncachedMask; 361 } 362 break; 363 364 case PCI0_BASE_ADDR1: 365 if (BARAddrs[1] != 0) { 366 pri_ctrl_addr = BARAddrs[1]; 367 if (pioInterface) 368 pioInterface->addAddrRange(RangeSize(pri_ctrl_addr, 369 pri_ctrl_size)); 370 371 pri_ctrl_addr &= EV5::PAddrUncachedMask; 372 } 373 break; 374 375 case PCI0_BASE_ADDR2: 376 if (BARAddrs[2] != 0) { 377 sec_cmd_addr = BARAddrs[2]; 378 if (pioInterface) 379 pioInterface->addAddrRange(RangeSize(sec_cmd_addr, 380 sec_cmd_size)); 381 382 sec_cmd_addr &= EV5::PAddrUncachedMask; 383 } 384 break; 385 386 case PCI0_BASE_ADDR3: 387 if (BARAddrs[3] != 0) { 388 sec_ctrl_addr = BARAddrs[3]; 389 if (pioInterface) 390 pioInterface->addAddrRange(RangeSize(sec_ctrl_addr, 391 sec_ctrl_size)); 392 393 sec_ctrl_addr &= EV5::PAddrUncachedMask; 394 } 395 break; 396 397 case PCI0_BASE_ADDR4: 398 if (BARAddrs[4] != 0) { 399 bmi_addr = BARAddrs[4]; 400 if (pioInterface) 401 pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size)); 402 403 bmi_addr &= EV5::PAddrUncachedMask; 404 } 405 break; 406 } 407} 408 409Fault 410IdeController::read(MemReqPtr &req, uint8_t *data) 411{ 412 Addr offset; 413 bool primary; 414 bool byte; 415 bool cmdBlk; 416 RegType_t type; 417 int disk; 418 419 parseAddr(req->paddr, offset, primary, type); 420 byte = (req->size == sizeof(uint8_t)) ? true : false; 421 cmdBlk = (type == COMMAND_BLOCK) ? true : false; 422 423 if (!io_enabled) 424 return No_Fault; 425 426 // sanity check the size (allows byte, word, or dword access) 427 if (req->size != sizeof(uint8_t) && req->size != sizeof(uint16_t) && 428 req->size != sizeof(uint32_t)) 429 panic("IDE controller read of invalid size: %#x\n", req->size); 430 431 if (type != BMI_BLOCK) { 432 assert(req->size != sizeof(uint32_t)); 433 434 disk = getDisk(primary); 435 if (disks[disk]) 436 disks[disk]->read(offset, byte, cmdBlk, data); 437 } else { 438 memcpy((void *)data, &bmi_regs[offset], req->size); 439 } 440 441 DPRINTF(IdeCtrl, "IDE read from offset: %#x size: %#x data: %#x\n", 442 offset, req->size, *(uint32_t *)data); 443 444 return No_Fault; 445} 446 447Fault 448IdeController::write(MemReqPtr &req, const uint8_t *data) 449{ 450 Addr offset; 451 bool primary; 452 bool byte; 453 bool cmdBlk; 454 RegType_t type; 455 int disk; 456 457 parseAddr(req->paddr, offset, primary, type); 458 byte = (req->size == sizeof(uint8_t)) ? true : false; 459 cmdBlk = (type == COMMAND_BLOCK) ? true : false; 460 461 DPRINTF(IdeCtrl, "IDE write from offset: %#x size: %#x data: %#x\n", 462 offset, req->size, *(uint32_t *)data); 463 464 uint8_t oldVal, newVal; 465 466 if (!io_enabled) 467 return No_Fault; 468 469 if (type == BMI_BLOCK && !bm_enabled) 470 return No_Fault; 471 472 if (type != BMI_BLOCK) { 473 // shadow the dev bit 474 if (type == COMMAND_BLOCK && offset == IDE_SELECT_OFFSET) { 475 uint8_t *devBit = (primary ? &dev[0] : &dev[1]); 476 *devBit = ((*data & IDE_SELECT_DEV_BIT) ? 1 : 0); 477 } 478 479 assert(req->size != sizeof(uint32_t)); 480 481 disk = getDisk(primary); 482 if (disks[disk]) 483 disks[disk]->write(offset, byte, cmdBlk, data); 484 } else { 485 switch (offset) { 486 // Bus master IDE command register 487 case BMIC1: 488 case BMIC0: 489 if (req->size != sizeof(uint8_t)) 490 panic("Invalid BMIC write size: %x\n", req->size); 491 492 // select the current disk based on DEV bit 493 disk = getDisk(primary); 494 495 oldVal = bmi_regs[offset]; 496 newVal = *data; 497 498 // if a DMA transfer is in progress, R/W control cannot change 499 if (oldVal & SSBM) { 500 if ((oldVal & RWCON) ^ (newVal & RWCON)) { 501 (oldVal & RWCON) ? newVal |= RWCON : newVal &= ~RWCON; 502 } 503 } 504 505 // see if the start/stop bit is being changed 506 if ((oldVal & SSBM) ^ (newVal & SSBM)) { 507 if (oldVal & SSBM) { 508 // stopping DMA transfer 509 DPRINTF(IdeCtrl, "Stopping DMA transfer\n"); 510 511 // clear the BMIDEA bit 512 bmi_regs[offset + 0x2] &= ~BMIDEA; 513 514 if (disks[disk] == NULL) 515 panic("DMA stop for disk %d which does not exist\n", 516 disk); 517 518 // inform the disk of the DMA transfer abort 519 disks[disk]->abortDma(); 520 } else { 521 // starting DMA transfer 522 DPRINTF(IdeCtrl, "Starting DMA transfer\n"); 523 524 // set the BMIDEA bit 525 bmi_regs[offset + 0x2] |= BMIDEA; 526 527 if (disks[disk] == NULL) 528 panic("DMA start for disk %d which does not exist\n", 529 disk); 530 531 // inform the disk of the DMA transfer start 532 if (primary) 533 disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP0]); 534 else 535 disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP1]); 536 } 537 } 538 539 // update the register value 540 bmi_regs[offset] = newVal; 541 break; 542 543 // Bus master IDE status register 544 case BMIS0: 545 case BMIS1: 546 if (req->size != sizeof(uint8_t)) 547 panic("Invalid BMIS write size: %x\n", req->size); 548 549 oldVal = bmi_regs[offset]; 550 newVal = *data; 551 552 // the BMIDEA bit is RO 553 newVal |= (oldVal & BMIDEA); 554 555 // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each 556 if ((oldVal & IDEINTS) && (newVal & IDEINTS)) 557 newVal &= ~IDEINTS; // clear the interrupt? 558 else 559 (oldVal & IDEINTS) ? newVal |= IDEINTS : newVal &= ~IDEINTS; 560 561 if ((oldVal & IDEDMAE) && (newVal & IDEDMAE)) 562 newVal &= ~IDEDMAE; 563 else 564 (oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE; 565 566 bmi_regs[offset] = newVal; 567 break; 568 569 // Bus master IDE descriptor table pointer register 570 case BMIDTP0: 571 case BMIDTP1: 572 if (req->size != sizeof(uint32_t)) 573 panic("Invalid BMIDTP write size: %x\n", req->size); 574 575 *(uint32_t *)&bmi_regs[offset] = *(uint32_t *)data & ~0x3; 576 break; 577 578 default: 579 if (req->size != sizeof(uint8_t) && 580 req->size != sizeof(uint16_t) && 581 req->size != sizeof(uint32_t)) 582 panic("IDE controller write of invalid write size: %x\n", 583 req->size); 584 585 // do a default copy of data into the registers 586 memcpy((void *)&bmi_regs[offset], data, req->size); 587 } 588 } 589 590 return No_Fault; 591} 592 593//// 594// Serialization 595//// 596 597void 598IdeController::serialize(std::ostream &os) 599{ 600 // Serialize the PciDev base class 601 PciDev::serialize(os); 602 603 // Serialize register addresses and sizes 604 SERIALIZE_SCALAR(pri_cmd_addr); 605 SERIALIZE_SCALAR(pri_cmd_size); 606 SERIALIZE_SCALAR(pri_ctrl_addr); 607 SERIALIZE_SCALAR(pri_ctrl_size); 608 SERIALIZE_SCALAR(sec_cmd_addr); 609 SERIALIZE_SCALAR(sec_cmd_size); 610 SERIALIZE_SCALAR(sec_ctrl_addr); 611 SERIALIZE_SCALAR(sec_ctrl_size); 612 SERIALIZE_SCALAR(bmi_addr); 613 SERIALIZE_SCALAR(bmi_size); 614 615 // Serialize registers 616 SERIALIZE_ARRAY(bmi_regs, 16); 617 SERIALIZE_ARRAY(dev, 2); 618 SERIALIZE_ARRAY(pci_regs, 8); 619 620 // Serialize internal state 621 SERIALIZE_SCALAR(io_enabled); 622 SERIALIZE_SCALAR(bm_enabled); 623 SERIALIZE_ARRAY(cmd_in_progress, 4); 624} 625 626void 627IdeController::unserialize(Checkpoint *cp, const std::string §ion) 628{ 629 // Unserialize the PciDev base class 630 PciDev::unserialize(cp, section); 631 632 // Unserialize register addresses and sizes 633 UNSERIALIZE_SCALAR(pri_cmd_addr); 634 UNSERIALIZE_SCALAR(pri_cmd_size); 635 UNSERIALIZE_SCALAR(pri_ctrl_addr); 636 UNSERIALIZE_SCALAR(pri_ctrl_size); 637 UNSERIALIZE_SCALAR(sec_cmd_addr); 638 UNSERIALIZE_SCALAR(sec_cmd_size); 639 UNSERIALIZE_SCALAR(sec_ctrl_addr); 640 UNSERIALIZE_SCALAR(sec_ctrl_size); 641 UNSERIALIZE_SCALAR(bmi_addr); 642 UNSERIALIZE_SCALAR(bmi_size); 643 644 // Unserialize registers 645 UNSERIALIZE_ARRAY(bmi_regs, 16); 646 UNSERIALIZE_ARRAY(dev, 2); 647 UNSERIALIZE_ARRAY(pci_regs, 8); 648 649 // Unserialize internal state 650 UNSERIALIZE_SCALAR(io_enabled); 651 UNSERIALIZE_SCALAR(bm_enabled); 652 UNSERIALIZE_ARRAY(cmd_in_progress, 4); 653 654 if (pioInterface) { 655 pioInterface->addAddrRange(RangeSize(pri_cmd_addr, pri_cmd_size)); 656 pioInterface->addAddrRange(RangeSize(pri_ctrl_addr, pri_ctrl_size)); 657 pioInterface->addAddrRange(RangeSize(sec_cmd_addr, sec_cmd_size)); 658 pioInterface->addAddrRange(RangeSize(sec_ctrl_addr, sec_ctrl_size)); 659 pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size)); 660 } 661} 662 663#ifndef DOXYGEN_SHOULD_SKIP_THIS 664 665BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController) 666 667 SimObjectVectorParam<IdeDisk *> disks; 668 SimObjectParam<MemoryController *> mmu; 669 SimObjectParam<PciConfigAll *> configspace; 670 SimObjectParam<PciConfigData *> configdata; 671 SimObjectParam<Platform *> platform; 672 Param<uint32_t> pci_bus; 673 Param<uint32_t> pci_dev; 674 Param<uint32_t> pci_func; 675 SimObjectParam<Bus *> io_bus; 676 Param<Tick> pio_latency; 677 SimObjectParam<HierParams *> hier; 678 679END_DECLARE_SIM_OBJECT_PARAMS(IdeController) 680 681BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController) 682 683 INIT_PARAM(disks, "IDE disks attached to this controller"), 684 INIT_PARAM(mmu, "Memory controller"), 685 INIT_PARAM(configspace, "PCI Configspace"), 686 INIT_PARAM(configdata, "PCI Config data"), 687 INIT_PARAM(platform, "Platform pointer"), 688 INIT_PARAM(pci_bus, "PCI bus ID"), 689 INIT_PARAM(pci_dev, "PCI device number"), 690 INIT_PARAM(pci_func, "PCI function code"), 691 INIT_PARAM_DFLT(io_bus, "Host bus to attach to", NULL), 692 INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), 693 INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) 694 695END_INIT_SIM_OBJECT_PARAMS(IdeController) 696 697CREATE_SIM_OBJECT(IdeController) 698{ 699 IdeController::Params *params = new IdeController::Params; 700 params->name = getInstanceName(); 701 params->mmu = mmu; 702 params->configSpace = configspace; 703 params->configData = configdata; 704 params->plat = platform; 705 params->busNum = pci_bus; 706 params->deviceNum = pci_dev; 707 params->functionNum = pci_func; 708 709 params->disks = disks; 710 params->host_bus = io_bus; 711 params->pio_latency = pio_latency; 712 params->hier = hier; 713 return new IdeController(params); 714} 715 716REGISTER_SIM_OBJECT("IdeController", IdeController) 717 718#endif //DOXYGEN_SHOULD_SKIP_THIS 719