ide_ctrl.cc revision 864
1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <cstddef> 30#include <cstdlib> 31#include <string> 32#include <vector> 33 34#include "base/trace.hh" 35#include "cpu/intr_control.hh" 36#include "dev/dma.hh" 37#include "dev/pcireg.h" 38#include "dev/pciconfigall.hh" 39#include "dev/ide_disk.hh" 40#include "dev/ide_ctrl.hh" 41#include "dev/tsunami_cchip.hh" 42#include "mem/bus/bus.hh" 43#include "mem/bus/pio_interface.hh" 44#include "mem/bus/pio_interface_impl.hh" 45#include "mem/bus/dma_interface.hh" 46#include "dev/tsunami.hh" 47#include "mem/functional_mem/memory_control.hh" 48#include "mem/functional_mem/physical_memory.hh" 49#include "sim/builder.hh" 50#include "sim/sim_object.hh" 51 52using namespace std; 53 54//// 55// Initialization and destruction 56//// 57 58IdeController::IdeController(const string &name, IntrControl *ic, 59 const vector<IdeDisk *> &new_disks, 60 MemoryController *mmu, PciConfigAll *cf, 61 PciConfigData *cd, Tsunami *t, uint32_t bus_num, 62 uint32_t dev_num, uint32_t func_num, 63 Bus *host_bus, HierParams *hier) 64 : PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t) 65{ 66 // put back pointer into Tsunami 67 tsunami->disk_controller = this; 68 69 // initialize the PIO interface addresses 70 pri_cmd_addr = 0; 71 pri_cmd_size = BARSize[0]; 72 73 pri_ctrl_addr = 0; 74 pri_ctrl_size = BARSize[1]; 75 76 sec_cmd_addr = 0; 77 sec_cmd_size = BARSize[2]; 78 79 sec_ctrl_addr = 0; 80 sec_ctrl_size = BARSize[3]; 81 82 // initialize the bus master interface (BMI) address to be configured 83 // via PCI 84 bmi_addr = 0; 85 bmi_size = BARSize[4]; 86 87 // zero out all of the registers 88 memset(bmi_regs, 0, sizeof(bmi_regs)); 89 memset(pci_regs, 0, sizeof(pci_regs)); 90 91 // setup initial values 92 *(uint32_t *)&pci_regs[IDETIM] = 0x80008000; // enable both channels 93 *(uint8_t *)&bmi_regs[BMIS0] = 0x60; 94 *(uint8_t *)&bmi_regs[BMIS1] = 0x60; 95 96 // reset all internal variables 97 io_enabled = false; 98 bm_enabled = false; 99 memset(cmd_in_progress, 0, sizeof(cmd_in_progress)); 100 101 // create the PIO and DMA interfaces 102 if (host_bus) { 103 pioInterface = newPioInterface(name, hier, host_bus, this, 104 &IdeController::cacheAccess); 105 106 dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus, 107 host_bus, 1); 108 } 109 110 // setup the disks attached to controller 111 memset(disks, 0, sizeof(IdeDisk *) * 4); 112 113 if (new_disks.size() > 3) 114 panic("IDE controllers support a maximum of 4 devices attached!\n"); 115 116 for (int i = 0; i < new_disks.size(); i++) { 117 disks[i] = new_disks[i]; 118 disks[i]->setController(this, dmaInterface); 119 } 120} 121 122IdeController::~IdeController() 123{ 124 for (int i = 0; i < 4; i++) 125 if (disks[i]) 126 delete disks[i]; 127} 128 129//// 130// Utility functions 131/// 132 133void 134IdeController::parseAddr(const Addr &addr, Addr &offset, bool &primary, 135 RegType_t &type) 136{ 137 offset = addr; 138 139 if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) { 140 offset -= pri_cmd_addr; 141 type = COMMAND_BLOCK; 142 primary = true; 143 } else if (addr >= pri_ctrl_addr && 144 addr < (pri_ctrl_addr + pri_ctrl_size)) { 145 offset -= pri_ctrl_addr; 146 type = CONTROL_BLOCK; 147 primary = true; 148 } else if (addr >= sec_cmd_addr && 149 addr < (sec_cmd_addr + sec_cmd_size)) { 150 offset -= sec_cmd_addr; 151 type = COMMAND_BLOCK; 152 primary = false; 153 } else if (addr >= sec_ctrl_addr && 154 addr < (sec_ctrl_addr + sec_ctrl_size)) { 155 offset -= sec_ctrl_addr; 156 type = CONTROL_BLOCK; 157 primary = false; 158 } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) { 159 offset -= bmi_addr; 160 type = BMI_BLOCK; 161 primary = (offset < BMIC1) ? true : false; 162 } else { 163 panic("IDE controller access to invalid address: %#x\n", addr); 164 } 165} 166 167int 168IdeController::getDisk(bool primary) 169{ 170 int disk = 0; 171 uint8_t *devBit = &dev[0]; 172 173 if (!primary) { 174 disk += 2; 175 devBit = &dev[1]; 176 } 177 178 disk += *devBit; 179 180 assert(*devBit == 0 || *devBit == 1); 181 182 return disk; 183} 184 185int 186IdeController::getDisk(IdeDisk *diskPtr) 187{ 188 for (int i = 0; i < 4; i++) { 189 if ((long)diskPtr == (long)disks[i]) 190 return i; 191 } 192 return -1; 193} 194 195//// 196// Command completion 197//// 198 199void 200IdeController::setDmaComplete(IdeDisk *disk) 201{ 202 int diskNum = getDisk(disk); 203 204 if (diskNum < 0) 205 panic("Unable to find disk based on pointer %#x\n", disk); 206 207 if (diskNum < 2) { 208 // clear the start/stop bit in the command register 209 bmi_regs[BMIC0] &= ~SSBM; 210 // clear the bus master active bit in the status register 211 bmi_regs[BMIS0] &= ~BMIDEA; 212 // set the interrupt bit 213 bmi_regs[BMIS0] |= IDEINTS; 214 } else { 215 // clear the start/stop bit in the command register 216 bmi_regs[BMIC1] &= ~SSBM; 217 // clear the bus master active bit in the status register 218 bmi_regs[BMIS1] &= ~BMIDEA; 219 // set the interrupt bit 220 bmi_regs[BMIS1] |= IDEINTS; 221 } 222} 223 224//// 225// Interrupt handling 226//// 227 228void 229IdeController::intrPost() 230{ 231 tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine); 232} 233 234void 235IdeController::intrClear() 236{ 237 tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine); 238} 239 240//// 241// Bus timing and bus access functions 242//// 243 244Tick 245IdeController::cacheAccess(MemReqPtr &req) 246{ 247 // @todo Add more accurate timing to cache access 248 return curTick + 1000; 249} 250 251//// 252// Read and write handling 253//// 254 255void 256IdeController::ReadConfig(int offset, int size, uint8_t *data) 257{ 258 Addr origOffset = offset; 259 260 if (offset < PCI_DEVICE_SPECIFIC) { 261 PciDev::ReadConfig(offset, size, data); 262 } else { 263 if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) { 264 offset -= PCI_IDE_TIMING; 265 offset += IDETIM; 266 267 if ((offset + size) > (IDETIM + 4)) 268 panic("PCI read of IDETIM with invalid size\n"); 269 } else if (offset == PCI_SLAVE_TIMING) { 270 offset -= PCI_SLAVE_TIMING; 271 offset += SIDETIM; 272 273 if ((offset + size) > (SIDETIM + 1)) 274 panic("PCI read of SIDETIM with invalid size\n"); 275 } else if (offset == PCI_UDMA33_CTRL) { 276 offset -= PCI_UDMA33_CTRL; 277 offset += UDMACTL; 278 279 if ((offset + size) > (UDMACTL + 1)) 280 panic("PCI read of UDMACTL with invalid size\n"); 281 } else if (offset >= PCI_UDMA33_TIMING && 282 offset < (PCI_UDMA33_TIMING + 2)) { 283 offset -= PCI_UDMA33_TIMING; 284 offset += UDMATIM; 285 286 if ((offset + size) > (UDMATIM + 2)) 287 panic("PCI read of UDMATIM with invalid size\n"); 288 } else { 289 panic("PCI read of unimplemented register: %x\n", offset); 290 } 291 292 memcpy((void *)data, (void *)&pci_regs[offset], size); 293 } 294 295 DPRINTF(IdeCtrl, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n", 296 origOffset, offset, size, *(uint32_t *)data); 297} 298 299void 300IdeController::WriteConfig(int offset, int size, uint32_t data) 301{ 302 DPRINTF(IdeCtrl, "IDE PCI write offset: %#x size: %#x data: %#x\n", 303 offset, size, data); 304 305 // do standard write stuff if in standard PCI space 306 if (offset < PCI_DEVICE_SPECIFIC) { 307 PciDev::WriteConfig(offset, size, data); 308 } else { 309 if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) { 310 offset -= PCI_IDE_TIMING; 311 offset += IDETIM; 312 313 if ((offset + size) > (IDETIM + 4)) 314 panic("PCI write to IDETIM with invalid size\n"); 315 } else if (offset == PCI_SLAVE_TIMING) { 316 offset -= PCI_SLAVE_TIMING; 317 offset += SIDETIM; 318 319 if ((offset + size) > (SIDETIM + 1)) 320 panic("PCI write to SIDETIM with invalid size\n"); 321 } else if (offset == PCI_UDMA33_CTRL) { 322 offset -= PCI_UDMA33_CTRL; 323 offset += UDMACTL; 324 325 if ((offset + size) > (UDMACTL + 1)) 326 panic("PCI write to UDMACTL with invalid size\n"); 327 } else if (offset >= PCI_UDMA33_TIMING && 328 offset < (PCI_UDMA33_TIMING + 2)) { 329 offset -= PCI_UDMA33_TIMING; 330 offset += UDMATIM; 331 332 if ((offset + size) > (UDMATIM + 2)) 333 panic("PCI write to UDMATIM with invalid size\n"); 334 } else { 335 panic("PCI write to unimplemented register: %x\n", offset); 336 } 337 338 memcpy((void *)&pci_regs[offset], (void *)&data, size); 339 } 340 341 if (offset == PCI_COMMAND) { 342 if (config.data[offset] & IOSE) 343 io_enabled = true; 344 else 345 io_enabled = false; 346 347 if (config.data[offset] & BME) 348 bm_enabled = true; 349 else 350 bm_enabled = false; 351 352 } else if (data != 0xffffffff) { 353 switch (offset) { 354 case PCI0_BASE_ADDR0: 355 pri_cmd_addr = BARAddrs[0]; 356 if (pioInterface) 357 pioInterface->addAddrRange(pri_cmd_addr, 358 pri_cmd_addr + pri_cmd_size - 1); 359 360 pri_cmd_addr = ((pri_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK); 361 break; 362 363 case PCI0_BASE_ADDR1: 364 pri_ctrl_addr = BARAddrs[1]; 365 if (pioInterface) 366 pioInterface->addAddrRange(pri_ctrl_addr, 367 pri_ctrl_addr + pri_ctrl_size - 1); 368 369 pri_ctrl_addr = ((pri_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK); 370 break; 371 372 case PCI0_BASE_ADDR2: 373 sec_cmd_addr = BARAddrs[2]; 374 if (pioInterface) 375 pioInterface->addAddrRange(sec_cmd_addr, 376 sec_cmd_addr + sec_cmd_size - 1); 377 378 sec_cmd_addr = ((sec_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK); 379 break; 380 381 case PCI0_BASE_ADDR3: 382 sec_ctrl_addr = BARAddrs[3]; 383 if (pioInterface) 384 pioInterface->addAddrRange(sec_ctrl_addr, 385 sec_ctrl_addr + sec_ctrl_size - 1); 386 387 sec_ctrl_addr = ((sec_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK); 388 break; 389 390 case PCI0_BASE_ADDR4: 391 bmi_addr = BARAddrs[4]; 392 if (pioInterface) 393 pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1); 394 395 bmi_addr = ((bmi_addr | 0xf0000000000ULL) & PA_IMPL_MASK); 396 break; 397 } 398 } 399} 400 401Fault 402IdeController::read(MemReqPtr &req, uint8_t *data) 403{ 404 Addr offset; 405 bool primary; 406 bool byte; 407 bool cmdBlk; 408 RegType_t type; 409 int disk; 410 411 parseAddr(req->paddr, offset, primary, type); 412 byte = (req->size == sizeof(uint8_t)) ? true : false; 413 cmdBlk = (type == COMMAND_BLOCK) ? true : false; 414 415 if (!io_enabled) 416 return No_Fault; 417 418 // sanity check the size (allows byte, word, or dword access) 419 if (req->size != sizeof(uint8_t) && req->size != sizeof(uint16_t) && 420 req->size != sizeof(uint32_t)) 421 panic("IDE controller read of invalid size: %#x\n", req->size); 422 423 if (type != BMI_BLOCK) { 424 assert(req->size != sizeof(uint32_t)); 425 426 disk = getDisk(primary); 427 if (disks[disk]) 428 disks[disk]->read(offset, byte, cmdBlk, data); 429 } else { 430 memcpy((void *)data, &bmi_regs[offset], req->size); 431 } 432 433 DPRINTF(IdeCtrl, "IDE read from offset: %#x size: %#x data: %#x\n", 434 offset, req->size, *(uint32_t *)data); 435 436 return No_Fault; 437} 438 439Fault 440IdeController::write(MemReqPtr &req, const uint8_t *data) 441{ 442 Addr offset; 443 bool primary; 444 bool byte; 445 bool cmdBlk; 446 RegType_t type; 447 int disk; 448 449 parseAddr(req->paddr, offset, primary, type); 450 byte = (req->size == sizeof(uint8_t)) ? true : false; 451 cmdBlk = (type == COMMAND_BLOCK) ? true : false; 452 453 DPRINTF(IdeCtrl, "IDE write from offset: %#x size: %#x data: %#x\n", 454 offset, req->size, *(uint32_t *)data); 455 456 uint8_t oldVal, newVal; 457 458 if (!io_enabled) 459 return No_Fault; 460 461 if (type == BMI_BLOCK && !bm_enabled) 462 return No_Fault; 463 464 if (type != BMI_BLOCK) { 465 // shadow the dev bit 466 if (type == COMMAND_BLOCK && offset == IDE_SELECT_OFFSET) { 467 uint8_t *devBit = (primary ? &dev[0] : &dev[1]); 468 *devBit = ((*data & IDE_SELECT_DEV_BIT) ? 1 : 0); 469 } 470 471 assert(req->size != sizeof(uint32_t)); 472 473 disk = getDisk(primary); 474 if (disks[disk]) 475 disks[disk]->write(offset, byte, cmdBlk, data); 476 } else { 477 switch (offset) { 478 // Bus master IDE command register 479 case BMIC1: 480 case BMIC0: 481 if (req->size != sizeof(uint8_t)) 482 panic("Invalid BMIC write size: %x\n", req->size); 483 484 // select the current disk based on DEV bit 485 disk = getDisk(primary); 486 487 oldVal = bmi_regs[offset]; 488 newVal = *data; 489 490 // if a DMA transfer is in progress, R/W control cannot change 491 if (oldVal & SSBM) { 492 if ((oldVal & RWCON) ^ (newVal & RWCON)) { 493 (oldVal & RWCON) ? newVal |= RWCON : newVal &= ~RWCON; 494 } 495 } 496 497 // see if the start/stop bit is being changed 498 if ((oldVal & SSBM) ^ (newVal & SSBM)) { 499 if (oldVal & SSBM) { 500 // stopping DMA transfer 501 DPRINTF(IdeCtrl, "Stopping DMA transfer\n"); 502 503 // clear the BMIDEA bit 504 bmi_regs[offset + 0x2] &= ~BMIDEA; 505 506 if (disks[disk] == NULL) 507 panic("DMA stop for disk %d which does not exist\n", 508 disk); 509 510 // inform the disk of the DMA transfer abort 511 disks[disk]->abortDma(); 512 } else { 513 // starting DMA transfer 514 DPRINTF(IdeCtrl, "Starting DMA transfer\n"); 515 516 // set the BMIDEA bit 517 bmi_regs[offset + 0x2] |= BMIDEA; 518 519 if (disks[disk] == NULL) 520 panic("DMA start for disk %d which does not exist\n", 521 disk); 522 523 // inform the disk of the DMA transfer start 524 if (primary) 525 disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP0]); 526 else 527 disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP1]); 528 } 529 } 530 531 // update the register value 532 bmi_regs[offset] = newVal; 533 break; 534 535 // Bus master IDE status register 536 case BMIS0: 537 case BMIS1: 538 if (req->size != sizeof(uint8_t)) 539 panic("Invalid BMIS write size: %x\n", req->size); 540 541 oldVal = bmi_regs[offset]; 542 newVal = *data; 543 544 // the BMIDEA bit is RO 545 newVal |= (oldVal & BMIDEA); 546 547 // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each 548 if ((oldVal & IDEINTS) && (newVal & IDEINTS)) 549 newVal &= ~IDEINTS; // clear the interrupt? 550 else 551 (oldVal & IDEINTS) ? newVal |= IDEINTS : newVal &= ~IDEINTS; 552 553 if ((oldVal & IDEDMAE) && (newVal & IDEDMAE)) 554 newVal &= ~IDEDMAE; 555 else 556 (oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE; 557 558 bmi_regs[offset] = newVal; 559 break; 560 561 // Bus master IDE descriptor table pointer register 562 case BMIDTP0: 563 case BMIDTP1: 564 if (req->size != sizeof(uint32_t)) 565 panic("Invalid BMIDTP write size: %x\n", req->size); 566 567 *(uint32_t *)&bmi_regs[offset] = *(uint32_t *)data & ~0x3; 568 break; 569 570 default: 571 if (req->size != sizeof(uint8_t) && 572 req->size != sizeof(uint16_t) && 573 req->size != sizeof(uint32_t)) 574 panic("IDE controller write of invalid write size: %x\n", 575 req->size); 576 577 // do a default copy of data into the registers 578 memcpy((void *)&bmi_regs[offset], data, req->size); 579 } 580 } 581 582 return No_Fault; 583} 584 585//// 586// Serialization 587//// 588 589void 590IdeController::serialize(std::ostream &os) 591{ 592 // Serialize register addresses and sizes 593 SERIALIZE_SCALAR(pri_cmd_addr); 594 SERIALIZE_SCALAR(pri_cmd_size); 595 SERIALIZE_SCALAR(pri_ctrl_addr); 596 SERIALIZE_SCALAR(pri_ctrl_size); 597 SERIALIZE_SCALAR(sec_cmd_addr); 598 SERIALIZE_SCALAR(sec_cmd_size); 599 SERIALIZE_SCALAR(sec_ctrl_addr); 600 SERIALIZE_SCALAR(sec_ctrl_size); 601 SERIALIZE_SCALAR(bmi_addr); 602 SERIALIZE_SCALAR(bmi_size); 603 604 // Serialize registers 605 SERIALIZE_ARRAY(bmi_regs, 16); 606 SERIALIZE_ARRAY(dev, 2); 607 SERIALIZE_ARRAY(pci_regs, 8); 608 609 // Serialize internal state 610 SERIALIZE_SCALAR(io_enabled); 611 SERIALIZE_SCALAR(bm_enabled); 612 SERIALIZE_ARRAY(cmd_in_progress, 4); 613} 614 615void 616IdeController::unserialize(Checkpoint *cp, const std::string §ion) 617{ 618 // Unserialize register addresses and sizes 619 UNSERIALIZE_SCALAR(pri_cmd_addr); 620 UNSERIALIZE_SCALAR(pri_cmd_size); 621 UNSERIALIZE_SCALAR(pri_ctrl_addr); 622 UNSERIALIZE_SCALAR(pri_ctrl_size); 623 UNSERIALIZE_SCALAR(sec_cmd_addr); 624 UNSERIALIZE_SCALAR(sec_cmd_size); 625 UNSERIALIZE_SCALAR(sec_ctrl_addr); 626 UNSERIALIZE_SCALAR(sec_ctrl_size); 627 UNSERIALIZE_SCALAR(bmi_addr); 628 UNSERIALIZE_SCALAR(bmi_size); 629 630 // Unserialize registers 631 UNSERIALIZE_ARRAY(bmi_regs, 16); 632 UNSERIALIZE_ARRAY(dev, 2); 633 UNSERIALIZE_ARRAY(pci_regs, 8); 634 635 // Unserialize internal state 636 UNSERIALIZE_SCALAR(io_enabled); 637 UNSERIALIZE_SCALAR(bm_enabled); 638 UNSERIALIZE_ARRAY(cmd_in_progress, 4); 639} 640 641#ifndef DOXYGEN_SHOULD_SKIP_THIS 642 643BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController) 644 645 SimObjectParam<IntrControl *> intr_ctrl; 646 SimObjectVectorParam<IdeDisk *> disks; 647 SimObjectParam<MemoryController *> mmu; 648 SimObjectParam<PciConfigAll *> configspace; 649 SimObjectParam<PciConfigData *> configdata; 650 SimObjectParam<Tsunami *> tsunami; 651 Param<uint32_t> pci_bus; 652 Param<uint32_t> pci_dev; 653 Param<uint32_t> pci_func; 654 SimObjectParam<Bus *> host_bus; 655 SimObjectParam<HierParams *> hier; 656 657END_DECLARE_SIM_OBJECT_PARAMS(IdeController) 658 659BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController) 660 661 INIT_PARAM(intr_ctrl, "Interrupt Controller"), 662 INIT_PARAM(disks, "IDE disks attached to this controller"), 663 INIT_PARAM(mmu, "Memory controller"), 664 INIT_PARAM(configspace, "PCI Configspace"), 665 INIT_PARAM(configdata, "PCI Config data"), 666 INIT_PARAM(tsunami, "Tsunami chipset pointer"), 667 INIT_PARAM(pci_bus, "PCI bus ID"), 668 INIT_PARAM(pci_dev, "PCI device number"), 669 INIT_PARAM(pci_func, "PCI function code"), 670 INIT_PARAM_DFLT(host_bus, "Host bus to attach to", NULL), 671 INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) 672 673END_INIT_SIM_OBJECT_PARAMS(IdeController) 674 675CREATE_SIM_OBJECT(IdeController) 676{ 677 return new IdeController(getInstanceName(), intr_ctrl, disks, mmu, 678 configspace, configdata, tsunami, pci_bus, 679 pci_dev, pci_func, host_bus, hier); 680} 681 682REGISTER_SIM_OBJECT("IdeController", IdeController) 683 684#endif //DOXYGEN_SHOULD_SKIP_THIS 685