t1000.hh revision 5034:6186ef720dd4
12391SN/A/*
28931Sandreas.hansson@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan
38931Sandreas.hansson@arm.com * All rights reserved.
48931Sandreas.hansson@arm.com *
58931Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without
68931Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are
78931Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright
88931Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer;
98931Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright
108931Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the
118931Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution;
128931Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its
138931Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from
142391SN/A * this software without specific prior written permission.
152391SN/A *
162391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272391SN/A *
282391SN/A * Authors: Ali Saidi
292391SN/A */
302391SN/A
312391SN/A/**
322391SN/A * @file
332391SN/A * Declaration of top level class for the T1000 platform chips. This class just
342391SN/A * retains pointers to all its children so the children can communicate.
352391SN/A */
362391SN/A
372391SN/A#ifndef __DEV_T1000_HH__
382391SN/A#define __DEV_T1000_HH__
392665SN/A
402665SN/A#include "dev/platform.hh"
418931Sandreas.hansson@arm.com#include "params/T1000.hh"
422391SN/A
432391SN/Aclass IdeController;
448931Sandreas.hansson@arm.comclass System;
458931Sandreas.hansson@arm.com
468931Sandreas.hansson@arm.comclass T1000 : public Platform
472391SN/A{
482391SN/A  public:
498931Sandreas.hansson@arm.com    /** Pointer to the system */
508931Sandreas.hansson@arm.com    System *system;
512391SN/A
522462SN/A  public:
538931Sandreas.hansson@arm.com    typedef T1000Params Params;
548719SN/A    /**
552462SN/A     * Constructor for the Tsunami Class.
568931Sandreas.hansson@arm.com     * @param name name of the object
578931Sandreas.hansson@arm.com     * @param s system the object belongs to
588931Sandreas.hansson@arm.com     * @param intctrl pointer to the interrupt controller
598931Sandreas.hansson@arm.com     */
608931Sandreas.hansson@arm.com    T1000(const Params *p);
618931Sandreas.hansson@arm.com
628931Sandreas.hansson@arm.com    /**
638931Sandreas.hansson@arm.com     * Return the interrupting frequency to AlphaAccess
642391SN/A     * @return frequency of RTC interrupts
656107SN/A     */
666107SN/A    virtual Tick intrFrequency();
678931Sandreas.hansson@arm.com
688931Sandreas.hansson@arm.com    /**
692413SN/A     * Cause the cpu to post a serial interrupt to the CPU.
708931Sandreas.hansson@arm.com     */
718931Sandreas.hansson@arm.com    virtual void postConsoleInt();
722413SN/A
738931Sandreas.hansson@arm.com    /**
748931Sandreas.hansson@arm.com     * Clear a posted CPU interrupt
752413SN/A     */
768931Sandreas.hansson@arm.com    virtual void clearConsoleInt();
778931Sandreas.hansson@arm.com
783170SN/A    /**
793170SN/A     * Cause the chipset to post a cpi interrupt to the CPU.
808931Sandreas.hansson@arm.com     */
813170SN/A    virtual void postPciInt(int line);
823170SN/A
833170SN/A    /**
843170SN/A     * Clear a posted PCI->CPU interrupt
853170SN/A     */
863170SN/A    virtual void clearPciInt(int line);
873170SN/A
885543SN/A
895714SN/A    virtual Addr pciToDma(Addr pciAddr) const;
903170SN/A
913170SN/A    /**
923170SN/A     * Calculate the configuration address given a bus/dev/func.
933170SN/A     */
945714SN/A    virtual Addr calcConfigAddr(int bus, int dev, int func);
953170SN/A};
963170SN/A
978931Sandreas.hansson@arm.com#endif // __DEV_T1000_HH__
988931Sandreas.hansson@arm.com