t1000.hh revision 3812:eaa215123a26
1955SN/A/* 2955SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 311408Sandreas.sandberg@arm.com * All rights reserved. 49812Sandreas.hansson@arm.com * 59812Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 69812Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 79812Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 89812Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 99812Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 109812Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 119812Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 129812Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 139812Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 149812Sandreas.hansson@arm.com * this software without specific prior written permission. 157816Ssteve.reinhardt@amd.com * 165871Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171762SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18955SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19955SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20955SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21955SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22955SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23955SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24955SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25955SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26955SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27955SN/A * 28955SN/A * Authors: Ali Saidi 29955SN/A */ 30955SN/A 31955SN/A/** 32955SN/A * @file 33955SN/A * Declaration of top level class for the T1000 platform chips. This class just 34955SN/A * retains pointers to all its children so the children can communicate. 35955SN/A */ 36955SN/A 37955SN/A#ifndef __DEV_T1000_HH__ 38955SN/A#define __DEV_T1000_HH__ 39955SN/A 40955SN/A#include "dev/platform.hh" 41955SN/A 422665Ssaidi@eecs.umich.educlass IdeController; 432665Ssaidi@eecs.umich.educlass System; 445863Snate@binkert.org 45955SN/Aclass T1000 : public Platform 46955SN/A{ 47955SN/A public: 48955SN/A /** Pointer to the system */ 49955SN/A System *system; 508878Ssteve.reinhardt@amd.com 512632Sstever@eecs.umich.edu public: 528878Ssteve.reinhardt@amd.com /** 532632Sstever@eecs.umich.edu * Constructor for the Tsunami Class. 54955SN/A * @param name name of the object 558878Ssteve.reinhardt@amd.com * @param s system the object belongs to 562632Sstever@eecs.umich.edu * @param intctrl pointer to the interrupt controller 572761Sstever@eecs.umich.edu */ 582632Sstever@eecs.umich.edu T1000(const std::string &name, System *s, IntrControl *intctrl); 592632Sstever@eecs.umich.edu 602632Sstever@eecs.umich.edu /** 612761Sstever@eecs.umich.edu * Return the interrupting frequency to AlphaAccess 622761Sstever@eecs.umich.edu * @return frequency of RTC interrupts 632761Sstever@eecs.umich.edu */ 648878Ssteve.reinhardt@amd.com virtual Tick intrFrequency(); 658878Ssteve.reinhardt@amd.com 662761Sstever@eecs.umich.edu /** 672761Sstever@eecs.umich.edu * Cause the cpu to post a serial interrupt to the CPU. 682761Sstever@eecs.umich.edu */ 692761Sstever@eecs.umich.edu virtual void postConsoleInt(); 702761Sstever@eecs.umich.edu 718878Ssteve.reinhardt@amd.com /** 728878Ssteve.reinhardt@amd.com * Clear a posted CPU interrupt 732632Sstever@eecs.umich.edu */ 742632Sstever@eecs.umich.edu virtual void clearConsoleInt(); 758878Ssteve.reinhardt@amd.com 768878Ssteve.reinhardt@amd.com /** 772632Sstever@eecs.umich.edu * Cause the chipset to post a cpi interrupt to the CPU. 78955SN/A */ 79955SN/A virtual void postPciInt(int line); 80955SN/A 815863Snate@binkert.org /** 825863Snate@binkert.org * Clear a posted PCI->CPU interrupt 835863Snate@binkert.org */ 845863Snate@binkert.org virtual void clearPciInt(int line); 855863Snate@binkert.org 865863Snate@binkert.org 875863Snate@binkert.org virtual Addr pciToDma(Addr pciAddr) const; 885863Snate@binkert.org 895863Snate@binkert.org /** 905863Snate@binkert.org * Calculate the configuration address given a bus/dev/func. 915863Snate@binkert.org */ 928878Ssteve.reinhardt@amd.com virtual Addr calcConfigAddr(int bus, int dev, int func); 935863Snate@binkert.org 945863Snate@binkert.org /** 955863Snate@binkert.org * Serialize this object to the given output stream. 969812Sandreas.hansson@arm.com * @param os The stream to serialize to. 979812Sandreas.hansson@arm.com */ 985863Snate@binkert.org virtual void serialize(std::ostream &os); 999812Sandreas.hansson@arm.com 1005863Snate@binkert.org /** 1015863Snate@binkert.org * Reconstruct the state of this object from a checkpoint. 1025863Snate@binkert.org * @param cp The checkpoint use. 1039812Sandreas.hansson@arm.com * @param section The section name of this object 1049812Sandreas.hansson@arm.com */ 1055863Snate@binkert.org virtual void unserialize(Checkpoint *cp, const std::string §ion); 1065863Snate@binkert.org}; 1078878Ssteve.reinhardt@amd.com 1085863Snate@binkert.org#endif // __DEV_T1000_HH__ 1095863Snate@binkert.org