t1000.cc revision 3918:1f9a98d198e8
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31/** @file 32 * Implementation of T1000 platform. 33 */ 34 35#include <deque> 36#include <string> 37#include <vector> 38 39#include "cpu/intr_control.hh" 40#include "dev/simconsole.hh" 41#include "dev/sparc/t1000.hh" 42#include "sim/builder.hh" 43#include "sim/system.hh" 44 45using namespace std; 46//Should this be AlphaISA? 47using namespace TheISA; 48 49T1000::T1000(const string &name, System *s, IntrControl *ic) 50 : Platform(name, ic), system(s) 51{ 52 // set the back pointer from the system to myself 53 system->platform = this; 54} 55 56Tick 57T1000::intrFrequency() 58{ 59 panic("Need implementation\n"); 60 M5_DUMMY_RETURN 61} 62 63void 64T1000::postConsoleInt() 65{ 66 warn_once("Don't know what interrupt to post for console.\n"); 67 //panic("Need implementation\n"); 68} 69 70void 71T1000::clearConsoleInt() 72{ 73 warn_once("Don't know what interrupt to clear for console.\n"); 74 //panic("Need implementation\n"); 75} 76 77void 78T1000::postPciInt(int line) 79{ 80 panic("Need implementation\n"); 81} 82 83void 84T1000::clearPciInt(int line) 85{ 86 panic("Need implementation\n"); 87} 88 89Addr 90T1000::pciToDma(Addr pciAddr) const 91{ 92 panic("Need implementation\n"); 93 M5_DUMMY_RETURN 94} 95 96 97Addr 98T1000::calcConfigAddr(int bus, int dev, int func) 99{ 100 panic("Need implementation\n"); 101 M5_DUMMY_RETURN 102} 103 104void 105T1000::serialize(std::ostream &os) 106{ 107 panic("Need implementation\n"); 108} 109 110void 111T1000::unserialize(Checkpoint *cp, const std::string §ion) 112{ 113 panic("Need implementation\n"); 114} 115 116BEGIN_DECLARE_SIM_OBJECT_PARAMS(T1000) 117 118 SimObjectParam<System *> system; 119 SimObjectParam<IntrControl *> intrctrl; 120 121END_DECLARE_SIM_OBJECT_PARAMS(T1000) 122 123BEGIN_INIT_SIM_OBJECT_PARAMS(T1000) 124 125 INIT_PARAM(system, "system"), 126 INIT_PARAM(intrctrl, "interrupt controller") 127 128END_INIT_SIM_OBJECT_PARAMS(T1000) 129 130CREATE_SIM_OBJECT(T1000) 131{ 132 return new T1000(getInstanceName(), system, intrctrl); 133} 134 135REGISTER_SIM_OBJECT("T1000", T1000) 136