iob.cc revision 4104
14104Ssaidi@eecs.umich.edu/* 24104Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 34104Ssaidi@eecs.umich.edu * All rights reserved. 44104Ssaidi@eecs.umich.edu * 54104Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64104Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 74104Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84104Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94104Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104104Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114104Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124104Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134104Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144104Ssaidi@eecs.umich.edu * this software without specific prior written permission. 154104Ssaidi@eecs.umich.edu * 164104Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174104Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184104Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194104Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204104Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214104Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224104Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234104Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244104Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254104Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264104Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274104Ssaidi@eecs.umich.edu * 284104Ssaidi@eecs.umich.edu * Authors: Ali Saidi 294104Ssaidi@eecs.umich.edu */ 304104Ssaidi@eecs.umich.edu 314104Ssaidi@eecs.umich.edu/** @file 324104Ssaidi@eecs.umich.edu * This device implemetns the niagara I/O bridge chip. It manages incomming 334104Ssaidi@eecs.umich.edu * interrupts and posts them to the CPU when needed. It holds mask registers and 344104Ssaidi@eecs.umich.edu * various status registers for CPUs to check what interrupts are pending as 354104Ssaidi@eecs.umich.edu * well as facilities to send IPIs to other cpus. 364104Ssaidi@eecs.umich.edu */ 374104Ssaidi@eecs.umich.edu 384104Ssaidi@eecs.umich.edu#include <cstring> 394104Ssaidi@eecs.umich.edu 404104Ssaidi@eecs.umich.edu#include "arch/sparc/isa_traits.hh" 414104Ssaidi@eecs.umich.edu#include "base/trace.hh" 424104Ssaidi@eecs.umich.edu#include "cpu/intr_control.hh" 434104Ssaidi@eecs.umich.edu#include "dev/sparc/iob.hh" 444104Ssaidi@eecs.umich.edu#include "dev/platform.hh" 454104Ssaidi@eecs.umich.edu#include "mem/port.hh" 464104Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 474104Ssaidi@eecs.umich.edu#include "sim/builder.hh" 484104Ssaidi@eecs.umich.edu#include "sim/system.hh" 494104Ssaidi@eecs.umich.edu 504104Ssaidi@eecs.umich.eduIob::Iob(Params *p) 514104Ssaidi@eecs.umich.edu : PioDevice(p), ic(p->platform->intrctrl) 524104Ssaidi@eecs.umich.edu{ 534104Ssaidi@eecs.umich.edu iobManAddr = ULL(0x9800000000); 544104Ssaidi@eecs.umich.edu iobManSize = ULL(0x0100000000); 554104Ssaidi@eecs.umich.edu iobJBusAddr = ULL(0x9F00000000); 564104Ssaidi@eecs.umich.edu iobJBusSize = ULL(0x0100000000); 574104Ssaidi@eecs.umich.edu assert (params()->system->threadContexts.size() <= MaxNiagaraProcs); 584104Ssaidi@eecs.umich.edu // Get the interrupt controller from the platform 594104Ssaidi@eecs.umich.edu ic = platform->intrctrl; 604104Ssaidi@eecs.umich.edu 614104Ssaidi@eecs.umich.edu for (int x = 0; x < NumDeviceIds; ++x) { 624104Ssaidi@eecs.umich.edu intMan[x].cpu = 0; 634104Ssaidi@eecs.umich.edu intMan[x].vector = 0; 644104Ssaidi@eecs.umich.edu intCtl[x].mask = true; 654104Ssaidi@eecs.umich.edu intCtl[x].pend = false; 664104Ssaidi@eecs.umich.edu } 674104Ssaidi@eecs.umich.edu 684104Ssaidi@eecs.umich.edu} 694104Ssaidi@eecs.umich.edu 704104Ssaidi@eecs.umich.eduTick 714104Ssaidi@eecs.umich.eduIob::read(PacketPtr pkt) 724104Ssaidi@eecs.umich.edu{ 734104Ssaidi@eecs.umich.edu assert(pkt->result == Packet::Unknown); 744104Ssaidi@eecs.umich.edu 754104Ssaidi@eecs.umich.edu if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize) 764104Ssaidi@eecs.umich.edu readIob(pkt); 774104Ssaidi@eecs.umich.edu else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize) 784104Ssaidi@eecs.umich.edu readJBus(pkt); 794104Ssaidi@eecs.umich.edu else 804104Ssaidi@eecs.umich.edu panic("Invalid address reached Iob\n"); 814104Ssaidi@eecs.umich.edu 824104Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 834104Ssaidi@eecs.umich.edu return pioDelay; 844104Ssaidi@eecs.umich.edu} 854104Ssaidi@eecs.umich.edu 864104Ssaidi@eecs.umich.eduvoid 874104Ssaidi@eecs.umich.eduIob::readIob(PacketPtr pkt) 884104Ssaidi@eecs.umich.edu{ 894104Ssaidi@eecs.umich.edu Addr accessAddr = pkt->getAddr() - iobManAddr; 904104Ssaidi@eecs.umich.edu int index; 914104Ssaidi@eecs.umich.edu uint64_t data; 924104Ssaidi@eecs.umich.edu 934104Ssaidi@eecs.umich.edu if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) { 944104Ssaidi@eecs.umich.edu index = (accessAddr - IntManAddr) >> 3; 954104Ssaidi@eecs.umich.edu data = intMan[index].cpu << 8 | intMan[index].vector << 0; 964104Ssaidi@eecs.umich.edu pkt->set(data); 974104Ssaidi@eecs.umich.edu return; 984104Ssaidi@eecs.umich.edu } 994104Ssaidi@eecs.umich.edu 1004104Ssaidi@eecs.umich.edu if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) { 1014104Ssaidi@eecs.umich.edu index = (accessAddr - IntManAddr) >> 3; 1024104Ssaidi@eecs.umich.edu data = intCtl[index].mask ? 1 << 2 : 0 | 1034104Ssaidi@eecs.umich.edu intCtl[index].pend ? 1 << 0 : 0; 1044104Ssaidi@eecs.umich.edu pkt->set(data); 1054104Ssaidi@eecs.umich.edu return; 1064104Ssaidi@eecs.umich.edu } 1074104Ssaidi@eecs.umich.edu 1084104Ssaidi@eecs.umich.edu if (accessAddr == JIntVecAddr) { 1094104Ssaidi@eecs.umich.edu pkt->set(jIntVec); 1104104Ssaidi@eecs.umich.edu return; 1114104Ssaidi@eecs.umich.edu } 1124104Ssaidi@eecs.umich.edu 1134104Ssaidi@eecs.umich.edu panic("Read to unknown IOB offset 0x%x\n", accessAddr); 1144104Ssaidi@eecs.umich.edu} 1154104Ssaidi@eecs.umich.edu 1164104Ssaidi@eecs.umich.eduvoid 1174104Ssaidi@eecs.umich.eduIob::readJBus(PacketPtr pkt) 1184104Ssaidi@eecs.umich.edu{ 1194104Ssaidi@eecs.umich.edu Addr accessAddr = pkt->getAddr() - iobJBusAddr; 1204104Ssaidi@eecs.umich.edu int cpuid = pkt->req->getCpuNum(); 1214104Ssaidi@eecs.umich.edu int index; 1224104Ssaidi@eecs.umich.edu uint64_t data; 1234104Ssaidi@eecs.umich.edu 1244104Ssaidi@eecs.umich.edu 1254104Ssaidi@eecs.umich.edu 1264104Ssaidi@eecs.umich.edu 1274104Ssaidi@eecs.umich.edu if (accessAddr >= JIntData0Addr && accessAddr < JIntData1Addr) { 1284104Ssaidi@eecs.umich.edu index = (accessAddr - JIntData0Addr) >> 3; 1294104Ssaidi@eecs.umich.edu pkt->set(jBusData0[index]); 1304104Ssaidi@eecs.umich.edu return; 1314104Ssaidi@eecs.umich.edu } 1324104Ssaidi@eecs.umich.edu 1334104Ssaidi@eecs.umich.edu if (accessAddr >= JIntData1Addr && accessAddr < JIntDataA0Addr) { 1344104Ssaidi@eecs.umich.edu index = (accessAddr - JIntData1Addr) >> 3; 1354104Ssaidi@eecs.umich.edu pkt->set(jBusData1[index]); 1364104Ssaidi@eecs.umich.edu return; 1374104Ssaidi@eecs.umich.edu } 1384104Ssaidi@eecs.umich.edu 1394104Ssaidi@eecs.umich.edu if (accessAddr == JIntDataA0Addr) { 1404104Ssaidi@eecs.umich.edu pkt->set(jBusData0[cpuid]); 1414104Ssaidi@eecs.umich.edu return; 1424104Ssaidi@eecs.umich.edu } 1434104Ssaidi@eecs.umich.edu 1444104Ssaidi@eecs.umich.edu if (accessAddr == JIntDataA1Addr) { 1454104Ssaidi@eecs.umich.edu pkt->set(jBusData1[cpuid]); 1464104Ssaidi@eecs.umich.edu return; 1474104Ssaidi@eecs.umich.edu } 1484104Ssaidi@eecs.umich.edu 1494104Ssaidi@eecs.umich.edu if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) { 1504104Ssaidi@eecs.umich.edu index = (accessAddr - JIntBusyAddr) >> 3; 1514104Ssaidi@eecs.umich.edu data = jIntBusy[index].busy ? 1 << 5 : 0 | 1524104Ssaidi@eecs.umich.edu jIntBusy[index].source; 1534104Ssaidi@eecs.umich.edu pkt->set(data); 1544104Ssaidi@eecs.umich.edu return; 1554104Ssaidi@eecs.umich.edu } 1564104Ssaidi@eecs.umich.edu if (accessAddr == JIntABusyAddr) { 1574104Ssaidi@eecs.umich.edu data = jIntBusy[cpuid].busy ? 1 << 5 : 0 | 1584104Ssaidi@eecs.umich.edu jIntBusy[cpuid].source; 1594104Ssaidi@eecs.umich.edu pkt->set(data); 1604104Ssaidi@eecs.umich.edu return; 1614104Ssaidi@eecs.umich.edu }; 1624104Ssaidi@eecs.umich.edu 1634104Ssaidi@eecs.umich.edu panic("Read to unknown JBus offset 0x%x\n", accessAddr); 1644104Ssaidi@eecs.umich.edu} 1654104Ssaidi@eecs.umich.edu 1664104Ssaidi@eecs.umich.eduTick 1674104Ssaidi@eecs.umich.eduIob::write(PacketPtr pkt) 1684104Ssaidi@eecs.umich.edu{ 1694104Ssaidi@eecs.umich.edu if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize) 1704104Ssaidi@eecs.umich.edu writeIob(pkt); 1714104Ssaidi@eecs.umich.edu else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize) 1724104Ssaidi@eecs.umich.edu writeJBus(pkt); 1734104Ssaidi@eecs.umich.edu else 1744104Ssaidi@eecs.umich.edu panic("Invalid address reached Iob\n"); 1754104Ssaidi@eecs.umich.edu 1764104Ssaidi@eecs.umich.edu 1774104Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 1784104Ssaidi@eecs.umich.edu return pioDelay; 1794104Ssaidi@eecs.umich.edu} 1804104Ssaidi@eecs.umich.edu 1814104Ssaidi@eecs.umich.eduvoid 1824104Ssaidi@eecs.umich.eduIob::writeIob(PacketPtr pkt) 1834104Ssaidi@eecs.umich.edu{ 1844104Ssaidi@eecs.umich.edu Addr accessAddr = pkt->getAddr() - iobManAddr; 1854104Ssaidi@eecs.umich.edu int index; 1864104Ssaidi@eecs.umich.edu uint64_t data; 1874104Ssaidi@eecs.umich.edu 1884104Ssaidi@eecs.umich.edu if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) { 1894104Ssaidi@eecs.umich.edu index = (accessAddr - IntManAddr) >> 3; 1904104Ssaidi@eecs.umich.edu data = pkt->get<uint64_t>(); 1914104Ssaidi@eecs.umich.edu intMan[index].cpu = bits(data,12,8); 1924104Ssaidi@eecs.umich.edu intMan[index].vector = bits(data,5,0); 1934104Ssaidi@eecs.umich.edu return; 1944104Ssaidi@eecs.umich.edu } 1954104Ssaidi@eecs.umich.edu 1964104Ssaidi@eecs.umich.edu if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) { 1974104Ssaidi@eecs.umich.edu index = (accessAddr - IntManAddr) >> 3; 1984104Ssaidi@eecs.umich.edu data = pkt->get<uint64_t>(); 1994104Ssaidi@eecs.umich.edu intCtl[index].mask = bits(data,2,2); 2004104Ssaidi@eecs.umich.edu if (bits(data,1,1)) 2014104Ssaidi@eecs.umich.edu intCtl[index].pend = false; 2024104Ssaidi@eecs.umich.edu return; 2034104Ssaidi@eecs.umich.edu } 2044104Ssaidi@eecs.umich.edu 2054104Ssaidi@eecs.umich.edu if (accessAddr == JIntVecAddr) { 2064104Ssaidi@eecs.umich.edu jIntVec = bits(pkt->get<uint64_t>(), 5,0); 2074104Ssaidi@eecs.umich.edu return; 2084104Ssaidi@eecs.umich.edu } 2094104Ssaidi@eecs.umich.edu 2104104Ssaidi@eecs.umich.edu if (accessAddr >= IntVecDisAddr && accessAddr < IntVecDisAddr + IntVecDisSize) { 2114104Ssaidi@eecs.umich.edu Type type; 2124104Ssaidi@eecs.umich.edu int cpu_id; 2134104Ssaidi@eecs.umich.edu int vector; 2144104Ssaidi@eecs.umich.edu index = (accessAddr - IntManAddr) >> 3; 2154104Ssaidi@eecs.umich.edu data = pkt->get<uint64_t>(); 2164104Ssaidi@eecs.umich.edu type = (Type)bits(data,17,16); 2174104Ssaidi@eecs.umich.edu cpu_id = bits(data, 12,8); 2184104Ssaidi@eecs.umich.edu vector = bits(data,5,0); 2194104Ssaidi@eecs.umich.edu generateIpi(type,cpu_id, vector); 2204104Ssaidi@eecs.umich.edu return; 2214104Ssaidi@eecs.umich.edu } 2224104Ssaidi@eecs.umich.edu 2234104Ssaidi@eecs.umich.edu panic("Write to unknown IOB offset 0x%x\n", accessAddr); 2244104Ssaidi@eecs.umich.edu} 2254104Ssaidi@eecs.umich.edu 2264104Ssaidi@eecs.umich.eduvoid 2274104Ssaidi@eecs.umich.eduIob::writeJBus(PacketPtr pkt) 2284104Ssaidi@eecs.umich.edu{ 2294104Ssaidi@eecs.umich.edu Addr accessAddr = pkt->getAddr() - iobJBusAddr; 2304104Ssaidi@eecs.umich.edu int cpuid = pkt->req->getCpuNum(); 2314104Ssaidi@eecs.umich.edu int index; 2324104Ssaidi@eecs.umich.edu uint64_t data; 2334104Ssaidi@eecs.umich.edu 2344104Ssaidi@eecs.umich.edu if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) { 2354104Ssaidi@eecs.umich.edu index = (accessAddr - JIntBusyAddr) >> 3; 2364104Ssaidi@eecs.umich.edu data = pkt->get<uint64_t>(); 2374104Ssaidi@eecs.umich.edu jIntBusy[index].busy = bits(data,5,5); 2384104Ssaidi@eecs.umich.edu return; 2394104Ssaidi@eecs.umich.edu } 2404104Ssaidi@eecs.umich.edu if (accessAddr == JIntABusyAddr) { 2414104Ssaidi@eecs.umich.edu data = pkt->get<uint64_t>(); 2424104Ssaidi@eecs.umich.edu jIntBusy[cpuid].busy = bits(data,5,5); 2434104Ssaidi@eecs.umich.edu return; 2444104Ssaidi@eecs.umich.edu }; 2454104Ssaidi@eecs.umich.edu 2464104Ssaidi@eecs.umich.edu panic("Write to unknown JBus offset 0x%x\n", accessAddr); 2474104Ssaidi@eecs.umich.edu} 2484104Ssaidi@eecs.umich.edu 2494104Ssaidi@eecs.umich.eduvoid 2504104Ssaidi@eecs.umich.eduIob::receiveDeviceInterrupt(DeviceId devid) 2514104Ssaidi@eecs.umich.edu{ 2524104Ssaidi@eecs.umich.edu assert(devid < NumDeviceIds); 2534104Ssaidi@eecs.umich.edu if (intCtl[devid].mask) 2544104Ssaidi@eecs.umich.edu return; 2554104Ssaidi@eecs.umich.edu intCtl[devid].mask = true; 2564104Ssaidi@eecs.umich.edu intCtl[devid].pend = true; 2574104Ssaidi@eecs.umich.edu ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector); 2584104Ssaidi@eecs.umich.edu} 2594104Ssaidi@eecs.umich.edu 2604104Ssaidi@eecs.umich.edu 2614104Ssaidi@eecs.umich.eduvoid 2624104Ssaidi@eecs.umich.eduIob::generateIpi(Type type, int cpu_id, int vector) 2634104Ssaidi@eecs.umich.edu{ 2644104Ssaidi@eecs.umich.edu // Only handle interrupts for the moment... Cpu Idle/reset/resume will be 2654104Ssaidi@eecs.umich.edu // later 2664104Ssaidi@eecs.umich.edu if (type != 0) { 2674104Ssaidi@eecs.umich.edu warn("Ignoring IntVecDis write\n"); 2684104Ssaidi@eecs.umich.edu return; 2694104Ssaidi@eecs.umich.edu } 2704104Ssaidi@eecs.umich.edu assert(type == 0); 2714104Ssaidi@eecs.umich.edu ic->post(cpu_id, SparcISA::IT_INT_VEC, vector); 2724104Ssaidi@eecs.umich.edu} 2734104Ssaidi@eecs.umich.edu 2744104Ssaidi@eecs.umich.edubool 2754104Ssaidi@eecs.umich.eduIob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1) 2764104Ssaidi@eecs.umich.edu{ 2774104Ssaidi@eecs.umich.edu // If we are already dealing with an interrupt for that cpu we can't deal 2784104Ssaidi@eecs.umich.edu // with another one right now... come back later 2794104Ssaidi@eecs.umich.edu if (jIntBusy[cpu_id].busy) 2804104Ssaidi@eecs.umich.edu return false; 2814104Ssaidi@eecs.umich.edu 2824104Ssaidi@eecs.umich.edu jIntBusy[cpu_id].busy = true; 2834104Ssaidi@eecs.umich.edu jIntBusy[cpu_id].source = source; 2844104Ssaidi@eecs.umich.edu jBusData0[cpu_id] = d0; 2854104Ssaidi@eecs.umich.edu jBusData1[cpu_id] = d1; 2864104Ssaidi@eecs.umich.edu 2874104Ssaidi@eecs.umich.edu ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec); 2884104Ssaidi@eecs.umich.edu return true; 2894104Ssaidi@eecs.umich.edu} 2904104Ssaidi@eecs.umich.edu 2914104Ssaidi@eecs.umich.eduvoid 2924104Ssaidi@eecs.umich.eduIob::addressRanges(AddrRangeList &range_list) 2934104Ssaidi@eecs.umich.edu{ 2944104Ssaidi@eecs.umich.edu range_list.clear(); 2954104Ssaidi@eecs.umich.edu range_list.push_back(RangeSize(iobManAddr, iobManSize)); 2964104Ssaidi@eecs.umich.edu range_list.push_back(RangeSize(iobJBusAddr, iobJBusSize)); 2974104Ssaidi@eecs.umich.edu} 2984104Ssaidi@eecs.umich.edu 2994104Ssaidi@eecs.umich.edu 3004104Ssaidi@eecs.umich.eduvoid 3014104Ssaidi@eecs.umich.eduIob::serialize(std::ostream &os) 3024104Ssaidi@eecs.umich.edu{ 3034104Ssaidi@eecs.umich.edu 3044104Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(jIntVec); 3054104Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs); 3064104Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs); 3074104Ssaidi@eecs.umich.edu for (int x = 0; x < NumDeviceIds; x++) { 3084104Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.Int%d", name(), x)); 3094104Ssaidi@eecs.umich.edu paramOut(os, "cpu", intMan[x].cpu); 3104104Ssaidi@eecs.umich.edu paramOut(os, "vector", intMan[x].vector); 3114104Ssaidi@eecs.umich.edu paramOut(os, "mask", intCtl[x].mask); 3124104Ssaidi@eecs.umich.edu paramOut(os, "pend", intCtl[x].pend); 3134104Ssaidi@eecs.umich.edu }; 3144104Ssaidi@eecs.umich.edu for (int x = 0; x < MaxNiagaraProcs; x++) { 3154104Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.jIntBusy%d", name(), x)); 3164104Ssaidi@eecs.umich.edu paramOut(os, "busy", jIntBusy[x].busy); 3174104Ssaidi@eecs.umich.edu paramOut(os, "source", jIntBusy[x].source); 3184104Ssaidi@eecs.umich.edu }; 3194104Ssaidi@eecs.umich.edu} 3204104Ssaidi@eecs.umich.edu 3214104Ssaidi@eecs.umich.eduvoid 3224104Ssaidi@eecs.umich.eduIob::unserialize(Checkpoint *cp, const std::string §ion) 3234104Ssaidi@eecs.umich.edu{ 3244104Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(jIntVec); 3254104Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs); 3264104Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs); 3274104Ssaidi@eecs.umich.edu for (int x = 0; x < NumDeviceIds; x++) { 3284104Ssaidi@eecs.umich.edu paramIn(cp, csprintf("%s.Int%d", name(), x), "cpu", intMan[x].cpu); 3294104Ssaidi@eecs.umich.edu paramIn(cp, csprintf("%s.Int%d", name(), x), "vector", intMan[x].vector); 3304104Ssaidi@eecs.umich.edu paramIn(cp, csprintf("%s.Int%d", name(), x), "mask", intCtl[x].mask); 3314104Ssaidi@eecs.umich.edu paramIn(cp, csprintf("%s.Int%d", name(), x), "pend", intCtl[x].pend); 3324104Ssaidi@eecs.umich.edu }; 3334104Ssaidi@eecs.umich.edu for (int x = 0; x < MaxNiagaraProcs; x++) { 3344104Ssaidi@eecs.umich.edu paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "busy", jIntBusy[x].busy); 3354104Ssaidi@eecs.umich.edu paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "source", jIntBusy[x].source); 3364104Ssaidi@eecs.umich.edu }; 3374104Ssaidi@eecs.umich.edu} 3384104Ssaidi@eecs.umich.edu 3394104Ssaidi@eecs.umich.edu 3404104Ssaidi@eecs.umich.edu 3414104Ssaidi@eecs.umich.edu 3424104Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(Iob) 3434104Ssaidi@eecs.umich.edu Param<Tick> pio_latency; 3444104Ssaidi@eecs.umich.edu SimObjectParam<Platform *> platform; 3454104Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 3464104Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(Iob) 3474104Ssaidi@eecs.umich.edu 3484104Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(Iob) 3494104Ssaidi@eecs.umich.edu 3504104Ssaidi@eecs.umich.edu INIT_PARAM(pio_latency, "Programmed IO latency"), 3514104Ssaidi@eecs.umich.edu INIT_PARAM(platform, "platform"), 3524104Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object") 3534104Ssaidi@eecs.umich.edu 3544104Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(Iob) 3554104Ssaidi@eecs.umich.edu 3564104Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(Iob) 3574104Ssaidi@eecs.umich.edu{ 3584104Ssaidi@eecs.umich.edu Iob::Params *p = new Iob::Params; 3594104Ssaidi@eecs.umich.edu p->name = getInstanceName(); 3604104Ssaidi@eecs.umich.edu p->pio_delay = pio_latency; 3614104Ssaidi@eecs.umich.edu p->platform = platform; 3624104Ssaidi@eecs.umich.edu p->system = system; 3634104Ssaidi@eecs.umich.edu return new Iob(p); 3644104Ssaidi@eecs.umich.edu} 3654104Ssaidi@eecs.umich.edu 3664104Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("Iob", Iob) 367