iob.cc revision 11294
14104Ssaidi@eecs.umich.edu/* 24104Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 34104Ssaidi@eecs.umich.edu * All rights reserved. 44104Ssaidi@eecs.umich.edu * 54104Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64104Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 74104Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84104Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94104Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104104Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114104Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124104Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134104Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144104Ssaidi@eecs.umich.edu * this software without specific prior written permission. 154104Ssaidi@eecs.umich.edu * 164104Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174104Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184104Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194104Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204104Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214104Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224104Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234104Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244104Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254104Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264104Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274104Ssaidi@eecs.umich.edu * 284104Ssaidi@eecs.umich.edu * Authors: Ali Saidi 294104Ssaidi@eecs.umich.edu */ 304104Ssaidi@eecs.umich.edu 314104Ssaidi@eecs.umich.edu/** @file 324104Ssaidi@eecs.umich.edu * This device implemetns the niagara I/O bridge chip. It manages incomming 334104Ssaidi@eecs.umich.edu * interrupts and posts them to the CPU when needed. It holds mask registers and 344104Ssaidi@eecs.umich.edu * various status registers for CPUs to check what interrupts are pending as 354104Ssaidi@eecs.umich.edu * well as facilities to send IPIs to other cpus. 364104Ssaidi@eecs.umich.edu */ 374104Ssaidi@eecs.umich.edu 384104Ssaidi@eecs.umich.edu#include <cstring> 394104Ssaidi@eecs.umich.edu 408229Snate@binkert.org#include "arch/sparc/faults.hh" 414104Ssaidi@eecs.umich.edu#include "arch/sparc/isa_traits.hh" 427723SAli.Saidi@ARM.com#include "base/bitfield.hh" 434104Ssaidi@eecs.umich.edu#include "base/trace.hh" 444104Ssaidi@eecs.umich.edu#include "cpu/intr_control.hh" 458739Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 468232Snate@binkert.org#include "debug/Iob.hh" 474104Ssaidi@eecs.umich.edu#include "dev/sparc/iob.hh" 484104Ssaidi@eecs.umich.edu#include "dev/platform.hh" 498229Snate@binkert.org#include "mem/packet_access.hh" 504104Ssaidi@eecs.umich.edu#include "mem/port.hh" 514194Ssaidi@eecs.umich.edu#include "sim/faults.hh" 524104Ssaidi@eecs.umich.edu#include "sim/system.hh" 534104Ssaidi@eecs.umich.edu 544762Snate@binkert.orgIob::Iob(const Params *p) 554104Ssaidi@eecs.umich.edu : PioDevice(p), ic(p->platform->intrctrl) 564104Ssaidi@eecs.umich.edu{ 574104Ssaidi@eecs.umich.edu iobManAddr = ULL(0x9800000000); 584104Ssaidi@eecs.umich.edu iobManSize = ULL(0x0100000000); 594104Ssaidi@eecs.umich.edu iobJBusAddr = ULL(0x9F00000000); 604104Ssaidi@eecs.umich.edu iobJBusSize = ULL(0x0100000000); 614104Ssaidi@eecs.umich.edu assert (params()->system->threadContexts.size() <= MaxNiagaraProcs); 625103Ssaidi@eecs.umich.edu 635103Ssaidi@eecs.umich.edu pioDelay = p->pio_latency; 645103Ssaidi@eecs.umich.edu 654104Ssaidi@eecs.umich.edu for (int x = 0; x < NumDeviceIds; ++x) { 664104Ssaidi@eecs.umich.edu intMan[x].cpu = 0; 674104Ssaidi@eecs.umich.edu intMan[x].vector = 0; 684104Ssaidi@eecs.umich.edu intCtl[x].mask = true; 694104Ssaidi@eecs.umich.edu intCtl[x].pend = false; 704104Ssaidi@eecs.umich.edu } 714104Ssaidi@eecs.umich.edu 724104Ssaidi@eecs.umich.edu} 734104Ssaidi@eecs.umich.edu 744104Ssaidi@eecs.umich.eduTick 754104Ssaidi@eecs.umich.eduIob::read(PacketPtr pkt) 764104Ssaidi@eecs.umich.edu{ 774104Ssaidi@eecs.umich.edu 784104Ssaidi@eecs.umich.edu if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize) 794104Ssaidi@eecs.umich.edu readIob(pkt); 804104Ssaidi@eecs.umich.edu else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize) 814104Ssaidi@eecs.umich.edu readJBus(pkt); 824104Ssaidi@eecs.umich.edu else 834104Ssaidi@eecs.umich.edu panic("Invalid address reached Iob\n"); 844104Ssaidi@eecs.umich.edu 854870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 864104Ssaidi@eecs.umich.edu return pioDelay; 874104Ssaidi@eecs.umich.edu} 884104Ssaidi@eecs.umich.edu 894104Ssaidi@eecs.umich.eduvoid 904104Ssaidi@eecs.umich.eduIob::readIob(PacketPtr pkt) 914104Ssaidi@eecs.umich.edu{ 924104Ssaidi@eecs.umich.edu Addr accessAddr = pkt->getAddr() - iobManAddr; 934104Ssaidi@eecs.umich.edu 9411294Sandreas.hansson@arm.com assert(IntManAddr == 0); 9511294Sandreas.hansson@arm.com if (accessAddr < IntManAddr + IntManSize) { 966712Snate@binkert.org int index = (accessAddr - IntManAddr) >> 3; 976712Snate@binkert.org uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0; 984104Ssaidi@eecs.umich.edu pkt->set(data); 994104Ssaidi@eecs.umich.edu return; 1004104Ssaidi@eecs.umich.edu } 1014104Ssaidi@eecs.umich.edu 1024104Ssaidi@eecs.umich.edu if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) { 1036712Snate@binkert.org int index = (accessAddr - IntCtlAddr) >> 3; 1046712Snate@binkert.org uint64_t data = intCtl[index].mask ? 1 << 2 : 0 | 1056712Snate@binkert.org intCtl[index].pend ? 1 << 0 : 0; 1064104Ssaidi@eecs.umich.edu pkt->set(data); 1074104Ssaidi@eecs.umich.edu return; 1084104Ssaidi@eecs.umich.edu } 1094104Ssaidi@eecs.umich.edu 1104104Ssaidi@eecs.umich.edu if (accessAddr == JIntVecAddr) { 1114104Ssaidi@eecs.umich.edu pkt->set(jIntVec); 1124104Ssaidi@eecs.umich.edu return; 1134104Ssaidi@eecs.umich.edu } 1144104Ssaidi@eecs.umich.edu 1154104Ssaidi@eecs.umich.edu panic("Read to unknown IOB offset 0x%x\n", accessAddr); 1164104Ssaidi@eecs.umich.edu} 1174104Ssaidi@eecs.umich.edu 1184104Ssaidi@eecs.umich.eduvoid 1194104Ssaidi@eecs.umich.eduIob::readJBus(PacketPtr pkt) 1204104Ssaidi@eecs.umich.edu{ 1214104Ssaidi@eecs.umich.edu Addr accessAddr = pkt->getAddr() - iobJBusAddr; 12211005Sandreas.sandberg@arm.com ContextID cpuid = pkt->req->contextId(); 1234104Ssaidi@eecs.umich.edu int index; 1244104Ssaidi@eecs.umich.edu uint64_t data; 1254104Ssaidi@eecs.umich.edu 1264104Ssaidi@eecs.umich.edu 1274104Ssaidi@eecs.umich.edu 1284104Ssaidi@eecs.umich.edu 1294104Ssaidi@eecs.umich.edu if (accessAddr >= JIntData0Addr && accessAddr < JIntData1Addr) { 1304104Ssaidi@eecs.umich.edu index = (accessAddr - JIntData0Addr) >> 3; 1314104Ssaidi@eecs.umich.edu pkt->set(jBusData0[index]); 1324104Ssaidi@eecs.umich.edu return; 1334104Ssaidi@eecs.umich.edu } 1344104Ssaidi@eecs.umich.edu 1354104Ssaidi@eecs.umich.edu if (accessAddr >= JIntData1Addr && accessAddr < JIntDataA0Addr) { 1364104Ssaidi@eecs.umich.edu index = (accessAddr - JIntData1Addr) >> 3; 1374104Ssaidi@eecs.umich.edu pkt->set(jBusData1[index]); 1384104Ssaidi@eecs.umich.edu return; 1394104Ssaidi@eecs.umich.edu } 1404104Ssaidi@eecs.umich.edu 1414104Ssaidi@eecs.umich.edu if (accessAddr == JIntDataA0Addr) { 1424104Ssaidi@eecs.umich.edu pkt->set(jBusData0[cpuid]); 1434104Ssaidi@eecs.umich.edu return; 1444104Ssaidi@eecs.umich.edu } 1454104Ssaidi@eecs.umich.edu 1464104Ssaidi@eecs.umich.edu if (accessAddr == JIntDataA1Addr) { 1474104Ssaidi@eecs.umich.edu pkt->set(jBusData1[cpuid]); 1484104Ssaidi@eecs.umich.edu return; 1494104Ssaidi@eecs.umich.edu } 1504104Ssaidi@eecs.umich.edu 1514104Ssaidi@eecs.umich.edu if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) { 1524104Ssaidi@eecs.umich.edu index = (accessAddr - JIntBusyAddr) >> 3; 1534104Ssaidi@eecs.umich.edu data = jIntBusy[index].busy ? 1 << 5 : 0 | 1544104Ssaidi@eecs.umich.edu jIntBusy[index].source; 1554104Ssaidi@eecs.umich.edu pkt->set(data); 1564104Ssaidi@eecs.umich.edu return; 1574104Ssaidi@eecs.umich.edu } 1584104Ssaidi@eecs.umich.edu if (accessAddr == JIntABusyAddr) { 1594104Ssaidi@eecs.umich.edu data = jIntBusy[cpuid].busy ? 1 << 5 : 0 | 1604104Ssaidi@eecs.umich.edu jIntBusy[cpuid].source; 1614104Ssaidi@eecs.umich.edu pkt->set(data); 1624104Ssaidi@eecs.umich.edu return; 1634104Ssaidi@eecs.umich.edu }; 1644104Ssaidi@eecs.umich.edu 1654104Ssaidi@eecs.umich.edu panic("Read to unknown JBus offset 0x%x\n", accessAddr); 1664104Ssaidi@eecs.umich.edu} 1674104Ssaidi@eecs.umich.edu 1684104Ssaidi@eecs.umich.eduTick 1694104Ssaidi@eecs.umich.eduIob::write(PacketPtr pkt) 1704104Ssaidi@eecs.umich.edu{ 1714104Ssaidi@eecs.umich.edu if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize) 1724104Ssaidi@eecs.umich.edu writeIob(pkt); 1734104Ssaidi@eecs.umich.edu else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize) 1744104Ssaidi@eecs.umich.edu writeJBus(pkt); 1754104Ssaidi@eecs.umich.edu else 1764104Ssaidi@eecs.umich.edu panic("Invalid address reached Iob\n"); 1774104Ssaidi@eecs.umich.edu 1784104Ssaidi@eecs.umich.edu 1794870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 1804104Ssaidi@eecs.umich.edu return pioDelay; 1814104Ssaidi@eecs.umich.edu} 1824104Ssaidi@eecs.umich.edu 1834104Ssaidi@eecs.umich.eduvoid 1844104Ssaidi@eecs.umich.eduIob::writeIob(PacketPtr pkt) 1854104Ssaidi@eecs.umich.edu{ 1864104Ssaidi@eecs.umich.edu Addr accessAddr = pkt->getAddr() - iobManAddr; 1874104Ssaidi@eecs.umich.edu int index; 1884104Ssaidi@eecs.umich.edu uint64_t data; 1894104Ssaidi@eecs.umich.edu 19011294Sandreas.hansson@arm.com assert(IntManAddr == 0); 19111294Sandreas.hansson@arm.com if (accessAddr < IntManAddr + IntManSize) { 1924104Ssaidi@eecs.umich.edu index = (accessAddr - IntManAddr) >> 3; 1934104Ssaidi@eecs.umich.edu data = pkt->get<uint64_t>(); 1944104Ssaidi@eecs.umich.edu intMan[index].cpu = bits(data,12,8); 1954104Ssaidi@eecs.umich.edu intMan[index].vector = bits(data,5,0); 1964216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Wrote IntMan %d cpu %d, vec %d\n", index, 1974216Ssaidi@eecs.umich.edu intMan[index].cpu, intMan[index].vector); 1984104Ssaidi@eecs.umich.edu return; 1994104Ssaidi@eecs.umich.edu } 2004104Ssaidi@eecs.umich.edu 2014104Ssaidi@eecs.umich.edu if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) { 2026712Snate@binkert.org index = (accessAddr - IntCtlAddr) >> 3; 2034104Ssaidi@eecs.umich.edu data = pkt->get<uint64_t>(); 2044104Ssaidi@eecs.umich.edu intCtl[index].mask = bits(data,2,2); 2054104Ssaidi@eecs.umich.edu if (bits(data,1,1)) 2064104Ssaidi@eecs.umich.edu intCtl[index].pend = false; 2074216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Wrote IntCtl %d pend %d cleared %d\n", index, 2084216Ssaidi@eecs.umich.edu intCtl[index].pend, bits(data,2,2)); 2094104Ssaidi@eecs.umich.edu return; 2104104Ssaidi@eecs.umich.edu } 2114104Ssaidi@eecs.umich.edu 2124104Ssaidi@eecs.umich.edu if (accessAddr == JIntVecAddr) { 2134104Ssaidi@eecs.umich.edu jIntVec = bits(pkt->get<uint64_t>(), 5,0); 2144216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Wrote jIntVec %d\n", jIntVec); 2154104Ssaidi@eecs.umich.edu return; 2164104Ssaidi@eecs.umich.edu } 2174104Ssaidi@eecs.umich.edu 2184104Ssaidi@eecs.umich.edu if (accessAddr >= IntVecDisAddr && accessAddr < IntVecDisAddr + IntVecDisSize) { 2194104Ssaidi@eecs.umich.edu Type type; 2204104Ssaidi@eecs.umich.edu int cpu_id; 2214104Ssaidi@eecs.umich.edu int vector; 2224104Ssaidi@eecs.umich.edu index = (accessAddr - IntManAddr) >> 3; 2234104Ssaidi@eecs.umich.edu data = pkt->get<uint64_t>(); 2244104Ssaidi@eecs.umich.edu type = (Type)bits(data,17,16); 2254104Ssaidi@eecs.umich.edu cpu_id = bits(data, 12,8); 2264104Ssaidi@eecs.umich.edu vector = bits(data,5,0); 2274104Ssaidi@eecs.umich.edu generateIpi(type,cpu_id, vector); 2284104Ssaidi@eecs.umich.edu return; 2294104Ssaidi@eecs.umich.edu } 2304104Ssaidi@eecs.umich.edu 2314104Ssaidi@eecs.umich.edu panic("Write to unknown IOB offset 0x%x\n", accessAddr); 2324104Ssaidi@eecs.umich.edu} 2334104Ssaidi@eecs.umich.edu 2344104Ssaidi@eecs.umich.eduvoid 2354104Ssaidi@eecs.umich.eduIob::writeJBus(PacketPtr pkt) 2364104Ssaidi@eecs.umich.edu{ 2374104Ssaidi@eecs.umich.edu Addr accessAddr = pkt->getAddr() - iobJBusAddr; 23811005Sandreas.sandberg@arm.com ContextID cpuid = pkt->req->contextId(); 2394104Ssaidi@eecs.umich.edu int index; 2404104Ssaidi@eecs.umich.edu uint64_t data; 2414104Ssaidi@eecs.umich.edu 2424104Ssaidi@eecs.umich.edu if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) { 2434104Ssaidi@eecs.umich.edu index = (accessAddr - JIntBusyAddr) >> 3; 2444104Ssaidi@eecs.umich.edu data = pkt->get<uint64_t>(); 2454104Ssaidi@eecs.umich.edu jIntBusy[index].busy = bits(data,5,5); 2464216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", index, 2474216Ssaidi@eecs.umich.edu jIntBusy[index].busy); 2484104Ssaidi@eecs.umich.edu return; 2494104Ssaidi@eecs.umich.edu } 2504104Ssaidi@eecs.umich.edu if (accessAddr == JIntABusyAddr) { 2514104Ssaidi@eecs.umich.edu data = pkt->get<uint64_t>(); 2524104Ssaidi@eecs.umich.edu jIntBusy[cpuid].busy = bits(data,5,5); 2534216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", cpuid, 2544216Ssaidi@eecs.umich.edu jIntBusy[cpuid].busy); 2554104Ssaidi@eecs.umich.edu return; 2564104Ssaidi@eecs.umich.edu }; 2574104Ssaidi@eecs.umich.edu 2584104Ssaidi@eecs.umich.edu panic("Write to unknown JBus offset 0x%x\n", accessAddr); 2594104Ssaidi@eecs.umich.edu} 2604104Ssaidi@eecs.umich.edu 2614104Ssaidi@eecs.umich.eduvoid 2624104Ssaidi@eecs.umich.eduIob::receiveDeviceInterrupt(DeviceId devid) 2634104Ssaidi@eecs.umich.edu{ 2644104Ssaidi@eecs.umich.edu assert(devid < NumDeviceIds); 2654104Ssaidi@eecs.umich.edu if (intCtl[devid].mask) 2664104Ssaidi@eecs.umich.edu return; 2674104Ssaidi@eecs.umich.edu intCtl[devid].mask = true; 2684104Ssaidi@eecs.umich.edu intCtl[devid].pend = true; 2694216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Receiving Device interrupt: %d for cpu %d vec %d\n", 2704216Ssaidi@eecs.umich.edu devid, intMan[devid].cpu, intMan[devid].vector); 2714104Ssaidi@eecs.umich.edu ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector); 2724104Ssaidi@eecs.umich.edu} 2734104Ssaidi@eecs.umich.edu 2744104Ssaidi@eecs.umich.edu 2754104Ssaidi@eecs.umich.eduvoid 2764104Ssaidi@eecs.umich.eduIob::generateIpi(Type type, int cpu_id, int vector) 2774104Ssaidi@eecs.umich.edu{ 2784194Ssaidi@eecs.umich.edu SparcISA::SparcFault<SparcISA::PowerOnReset> *por = new SparcISA::PowerOnReset(); 2795719Shsul@eecs.umich.edu if (cpu_id >= sys->numContexts()) 2804104Ssaidi@eecs.umich.edu return; 2814130Ssaidi@eecs.umich.edu 2824194Ssaidi@eecs.umich.edu switch (type) { 2834194Ssaidi@eecs.umich.edu case 0: // interrupt 2844216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Generating interrupt because of I/O write to cpu: %d vec %d\n", 2854216Ssaidi@eecs.umich.edu cpu_id, vector); 2864194Ssaidi@eecs.umich.edu ic->post(cpu_id, SparcISA::IT_INT_VEC, vector); 2874194Ssaidi@eecs.umich.edu break; 2884194Ssaidi@eecs.umich.edu case 1: // reset 2894194Ssaidi@eecs.umich.edu warn("Sending reset to CPU: %d\n", cpu_id); 2904194Ssaidi@eecs.umich.edu if (vector != por->trapType()) 2914194Ssaidi@eecs.umich.edu panic("Don't know how to set non-POR reset to cpu\n"); 2924194Ssaidi@eecs.umich.edu por->invoke(sys->threadContexts[cpu_id]); 2934194Ssaidi@eecs.umich.edu sys->threadContexts[cpu_id]->activate(); 2944194Ssaidi@eecs.umich.edu break; 2954194Ssaidi@eecs.umich.edu case 2: // idle -- this means stop executing and don't wake on interrupts 2964216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Idling CPU because of I/O write cpu: %d\n", cpu_id); 2974194Ssaidi@eecs.umich.edu sys->threadContexts[cpu_id]->halt(); 2984194Ssaidi@eecs.umich.edu break; 2994194Ssaidi@eecs.umich.edu case 3: // resume 3004216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Resuming CPU because of I/O write cpu: %d\n", cpu_id); 3014194Ssaidi@eecs.umich.edu sys->threadContexts[cpu_id]->activate(); 3024194Ssaidi@eecs.umich.edu break; 3034194Ssaidi@eecs.umich.edu default: 3044194Ssaidi@eecs.umich.edu panic("Invalid type to generate ipi\n"); 3054194Ssaidi@eecs.umich.edu } 3064104Ssaidi@eecs.umich.edu} 3074104Ssaidi@eecs.umich.edu 3084104Ssaidi@eecs.umich.edubool 3094104Ssaidi@eecs.umich.eduIob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1) 3104104Ssaidi@eecs.umich.edu{ 3114104Ssaidi@eecs.umich.edu // If we are already dealing with an interrupt for that cpu we can't deal 3124104Ssaidi@eecs.umich.edu // with another one right now... come back later 3134104Ssaidi@eecs.umich.edu if (jIntBusy[cpu_id].busy) 3144104Ssaidi@eecs.umich.edu return false; 3154104Ssaidi@eecs.umich.edu 3164216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Receiving jBus interrupt: %d for cpu %d vec %d\n", 3174216Ssaidi@eecs.umich.edu source, cpu_id, jIntVec); 3184216Ssaidi@eecs.umich.edu 3194104Ssaidi@eecs.umich.edu jIntBusy[cpu_id].busy = true; 3204104Ssaidi@eecs.umich.edu jIntBusy[cpu_id].source = source; 3214104Ssaidi@eecs.umich.edu jBusData0[cpu_id] = d0; 3224104Ssaidi@eecs.umich.edu jBusData1[cpu_id] = d1; 3234104Ssaidi@eecs.umich.edu 3244104Ssaidi@eecs.umich.edu ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec); 3254104Ssaidi@eecs.umich.edu return true; 3264104Ssaidi@eecs.umich.edu} 3274104Ssaidi@eecs.umich.edu 3288711Sandreas.hansson@arm.comAddrRangeList 3299090Sandreas.hansson@arm.comIob::getAddrRanges() const 3304104Ssaidi@eecs.umich.edu{ 3318711Sandreas.hansson@arm.com AddrRangeList ranges; 3328711Sandreas.hansson@arm.com ranges.push_back(RangeSize(iobManAddr, iobManSize)); 3338711Sandreas.hansson@arm.com ranges.push_back(RangeSize(iobJBusAddr, iobJBusSize)); 3348711Sandreas.hansson@arm.com return ranges; 3354104Ssaidi@eecs.umich.edu} 3364104Ssaidi@eecs.umich.edu 3374104Ssaidi@eecs.umich.edu 3384104Ssaidi@eecs.umich.eduvoid 33910905Sandreas.sandberg@arm.comIob::serialize(CheckpointOut &cp) const 3404104Ssaidi@eecs.umich.edu{ 3414104Ssaidi@eecs.umich.edu 3424104Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(jIntVec); 3434104Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs); 3444104Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs); 3454104Ssaidi@eecs.umich.edu for (int x = 0; x < NumDeviceIds; x++) { 34610905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("Int%d", x)); 34710905Sandreas.sandberg@arm.com paramOut(cp, "cpu", intMan[x].cpu); 34810905Sandreas.sandberg@arm.com paramOut(cp, "vector", intMan[x].vector); 34910905Sandreas.sandberg@arm.com paramOut(cp, "mask", intCtl[x].mask); 35010905Sandreas.sandberg@arm.com paramOut(cp, "pend", intCtl[x].pend); 3514104Ssaidi@eecs.umich.edu }; 3524104Ssaidi@eecs.umich.edu for (int x = 0; x < MaxNiagaraProcs; x++) { 35310905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("jIntBusy%d", x)); 35410905Sandreas.sandberg@arm.com paramOut(cp, "busy", jIntBusy[x].busy); 35510905Sandreas.sandberg@arm.com paramOut(cp, "source", jIntBusy[x].source); 3564104Ssaidi@eecs.umich.edu }; 3574104Ssaidi@eecs.umich.edu} 3584104Ssaidi@eecs.umich.edu 3594104Ssaidi@eecs.umich.eduvoid 36010905Sandreas.sandberg@arm.comIob::unserialize(CheckpointIn &cp) 3614104Ssaidi@eecs.umich.edu{ 3624104Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(jIntVec); 3634104Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs); 3644104Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs); 3654104Ssaidi@eecs.umich.edu for (int x = 0; x < NumDeviceIds; x++) { 36610905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("Int%d", x)); 36710905Sandreas.sandberg@arm.com paramIn(cp, "cpu", intMan[x].cpu); 36810905Sandreas.sandberg@arm.com paramIn(cp, "vector", intMan[x].vector); 36910905Sandreas.sandberg@arm.com paramIn(cp, "mask", intCtl[x].mask); 37010905Sandreas.sandberg@arm.com paramIn(cp, "pend", intCtl[x].pend); 3714104Ssaidi@eecs.umich.edu }; 3724104Ssaidi@eecs.umich.edu for (int x = 0; x < MaxNiagaraProcs; x++) { 37310905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("jIntBusy%d", x)); 37410905Sandreas.sandberg@arm.com paramIn(cp, "busy", jIntBusy[x].busy); 37510905Sandreas.sandberg@arm.com paramIn(cp, "source", jIntBusy[x].source); 3764104Ssaidi@eecs.umich.edu }; 3774104Ssaidi@eecs.umich.edu} 3784104Ssaidi@eecs.umich.edu 3794762Snate@binkert.orgIob * 3804762Snate@binkert.orgIobParams::create() 3814104Ssaidi@eecs.umich.edu{ 3824762Snate@binkert.org return new Iob(this); 3834104Ssaidi@eecs.umich.edu} 384