rtcreg.h revision 5391:b2852a9f4196
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2005 The Regents of The University of Michigan 311308Santhony.gutierrez@amd.com * All rights reserved. 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 611308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are 711308Santhony.gutierrez@amd.com * met: redistributions of source code must retain the above copyright 811308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer; 911308Santhony.gutierrez@amd.com * redistributions in binary form must reproduce the above copyright 1011308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer in the 1111308Santhony.gutierrez@amd.com * documentation and/or other materials provided with the distribution; 1211308Santhony.gutierrez@amd.com * neither the name of the copyright holders nor the names of its 1311308Santhony.gutierrez@amd.com * contributors may be used to endorse or promote products derived from 1411308Santhony.gutierrez@amd.com * this software without specific prior written permission. 1511308Santhony.gutierrez@amd.com * 1611308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712697Santhony.gutierrez@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812697Santhony.gutierrez@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912697Santhony.gutierrez@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011308Santhony.gutierrez@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111308Santhony.gutierrez@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211308Santhony.gutierrez@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311308Santhony.gutierrez@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411308Santhony.gutierrez@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511308Santhony.gutierrez@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611308Santhony.gutierrez@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711308Santhony.gutierrez@amd.com * 2811308Santhony.gutierrez@amd.com * Authors: Ali Saidi 2911308Santhony.gutierrez@amd.com * Miguel Serrano 3011308Santhony.gutierrez@amd.com * Nathan Binkert 3111308Santhony.gutierrez@amd.com */ 3211308Santhony.gutierrez@amd.com 3312697Santhony.gutierrez@amd.comstatic const int RTC_SEC = 0x00; 3411308Santhony.gutierrez@amd.comstatic const int RTC_SEC_ALRM = 0x01; 3511308Santhony.gutierrez@amd.comstatic const int RTC_MIN = 0x02; 3611308Santhony.gutierrez@amd.comstatic const int RTC_MIN_ALRM = 0x03; 3711308Santhony.gutierrez@amd.comstatic const int RTC_HR = 0x04; 3811308Santhony.gutierrez@amd.comstatic const int RTC_HR_ALRM = 0x05; 3911308Santhony.gutierrez@amd.comstatic const int RTC_DOW = 0x06; 4011308Santhony.gutierrez@amd.comstatic const int RTC_DOM = 0x07; 4111308Santhony.gutierrez@amd.comstatic const int RTC_MON = 0x08; 4211308Santhony.gutierrez@amd.comstatic const int RTC_YEAR = 0x09; 4311308Santhony.gutierrez@amd.com 4411308Santhony.gutierrez@amd.comstatic const int RTC_STAT_REGA = 0x0A; 4511308Santhony.gutierrez@amd.comstatic const int RTCA_1024HZ = 0x06; /* 1024Hz periodic interrupt frequency */ 4611308Santhony.gutierrez@amd.comstatic const int RTCA_32768HZ = 0x20; /* 22-stage divider, 32.768KHz timebase */ 4711308Santhony.gutierrez@amd.comstatic const int RTCA_UIP = 0x80; /* 1 = date and time update in progress */ 4811308Santhony.gutierrez@amd.com 4911308Santhony.gutierrez@amd.comstatic const int RTC_STAT_REGB = 0x0B; 5012334Sgabeblack@google.comstatic const int RTCB_DST = 0x01; /* USA Daylight Savings Time enable */ 5111308Santhony.gutierrez@amd.comstatic const int RTCB_24HR = 0x02; /* 0 = 12 hours, 1 = 24 hours */ 5211308Santhony.gutierrez@amd.comstatic const int RTCB_BIN = 0x04; /* 0 = BCD, 1 = Binary coded time */ 5311308Santhony.gutierrez@amd.comstatic const int RTCB_SQWE = 0x08; /* 1 = output sqare wave at SQW pin */ 5411308Santhony.gutierrez@amd.comstatic const int RTCB_UPDT_IE = 0x10; /* 1 = enable update-ended interrupt */ 5511308Santhony.gutierrez@amd.comstatic const int RTCB_ALRM_IE = 0x20; /* 1 = enable alarm interrupt */ 5611308Santhony.gutierrez@amd.comstatic const int RTCB_PRDC_IE = 0x40; /* 1 = enable periodic clock interrupt */ 5711308Santhony.gutierrez@amd.comstatic const int RTCB_NO_UPDT = 0x80; /* stop clock updates */ 5811308Santhony.gutierrez@amd.com 5911308Santhony.gutierrez@amd.comstatic const int RTC_STAT_REGC = 0x0C; 6011308Santhony.gutierrez@amd.comstatic const int RTC_STAT_REGD = 0x0D; 6111308Santhony.gutierrez@amd.com 6211308Santhony.gutierrez@amd.com