rtcreg.h revision 2665
11363SN/A/* 21363SN/A * Copyright (c) 2005 The Regents of The University of Michigan 31363SN/A * All rights reserved. 41363SN/A * 51363SN/A * Redistribution and use in source and binary forms, with or without 61363SN/A * modification, are permitted provided that the following conditions are 71363SN/A * met: redistributions of source code must retain the above copyright 81363SN/A * notice, this list of conditions and the following disclaimer; 91363SN/A * redistributions in binary form must reproduce the above copyright 101363SN/A * notice, this list of conditions and the following disclaimer in the 111363SN/A * documentation and/or other materials provided with the distribution; 121363SN/A * neither the name of the copyright holders nor the names of its 131363SN/A * contributors may be used to endorse or promote products derived from 141363SN/A * this software without specific prior written permission. 151363SN/A * 161363SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171363SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181363SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191363SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201363SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211363SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221363SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231363SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241363SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251363SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261363SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292665Ssaidi@eecs.umich.edu * Miguel Serrano 302665Ssaidi@eecs.umich.edu * Nathan Binkert 311363SN/A */ 321363SN/A 331363SN/A#define RTC_SEC 0x00 341363SN/A#define RTC_SEC_ALRM 0x01 351363SN/A#define RTC_MIN 0x02 361363SN/A#define RTC_MIN_ALRM 0x03 371363SN/A#define RTC_HR 0x04 381363SN/A#define RTC_HR_ALRM 0x05 391363SN/A#define RTC_DOW 0x06 401363SN/A#define RTC_DOM 0x07 411363SN/A#define RTC_MON 0x08 421363SN/A#define RTC_YEAR 0x09 431363SN/A 441817SN/A#define RTC_STAT_REGA 0x0A 451817SN/A#define RTCA_1024HZ 0x06 /* 1024Hz periodic interrupt frequency */ 461817SN/A#define RTCA_32768HZ 0x20 /* 22-stage divider, 32.768KHz timebase */ 471817SN/A#define RTCA_UIP 0x80 /* 1 = date and time update in progress */ 481817SN/A 491817SN/A#define RTC_STAT_REGB 0x0B 501817SN/A#define RTCB_DST 0x01 /* USA Daylight Savings Time enable */ 511817SN/A#define RTCB_24HR 0x02 /* 0 = 12 hours, 1 = 24 hours */ 521817SN/A#define RTCB_BIN 0x04 /* 0 = BCD, 1 = Binary coded time */ 531817SN/A#define RTCB_SQWE 0x08 /* 1 = output sqare wave at SQW pin */ 541817SN/A#define RTCB_UPDT_IE 0x10 /* 1 = enable update-ended interrupt */ 551817SN/A#define RTCB_ALRM_IE 0x20 /* 1 = enable alarm interrupt */ 561817SN/A#define RTCB_PRDC_IE 0x40 /* 1 = enable periodic clock interrupt */ 571817SN/A#define RTCB_NO_UPDT 0x80 /* stop clock updates */ 581817SN/A 591817SN/A#define RTC_STAT_REGC 0x0C 601817SN/A#define RTC_STAT_REGD 0x0D 611817SN/A 62