platform.hh revision 5034
1807SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3807SN/A * All rights reserved. 4807SN/A * 5807SN/A * Redistribution and use in source and binary forms, with or without 6807SN/A * modification, are permitted provided that the following conditions are 7807SN/A * met: redistributions of source code must retain the above copyright 8807SN/A * notice, this list of conditions and the following disclaimer; 9807SN/A * redistributions in binary form must reproduce the above copyright 10807SN/A * notice, this list of conditions and the following disclaimer in the 11807SN/A * documentation and/or other materials provided with the distribution; 12807SN/A * neither the name of the copyright holders nor the names of its 13807SN/A * contributors may be used to endorse or promote products derived from 14807SN/A * this software without specific prior written permission. 15807SN/A * 16807SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17807SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18807SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19807SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20807SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21807SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22807SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23807SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24807SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25807SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26807SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Andrew Schultz 292760Sbinkertn@umich.edu * Nathan Binkert 30807SN/A */ 31807SN/A 32807SN/A/** 33807SN/A * @file 34807SN/A * Generic interface for platforms 35807SN/A */ 36807SN/A 371634SN/A#ifndef __DEV_PLATFORM_HH__ 381634SN/A#define __DEV_PLATFORM_HH__ 39807SN/A 402846Ssaidi@eecs.umich.edu#include <bitset> 412846Ssaidi@eecs.umich.edu#include <set> 422846Ssaidi@eecs.umich.edu 43807SN/A#include "sim/sim_object.hh" 442080SN/A#include "arch/isa_traits.hh" 455034Smilesck@eecs.umich.edu#include "params/Platform.hh" 46807SN/A 47849SN/Aclass PciConfigAll; 48807SN/Aclass IntrControl; 49807SN/Aclass SimConsole; 50932SN/Aclass Uart; 512384SN/Aclass System; 52807SN/A 53807SN/Aclass Platform : public SimObject 54807SN/A{ 55807SN/A public: 56807SN/A /** Pointer to the interrupt controller */ 57807SN/A IntrControl *intrctrl; 581634SN/A 592384SN/A /** Pointer to the system for info about the memory system. */ 602384SN/A System *system; 612384SN/A 62807SN/A public: 635034Smilesck@eecs.umich.edu typedef PlatformParams Params; 645034Smilesck@eecs.umich.edu Platform(const Params *p); 651634SN/A virtual ~Platform(); 66865SN/A virtual void postConsoleInt() = 0; 67865SN/A virtual void clearConsoleInt() = 0; 68891SN/A virtual Tick intrFrequency() = 0; 691149SN/A virtual void postPciInt(int line); 701149SN/A virtual void clearPciInt(int line); 711149SN/A virtual Addr pciToDma(Addr pciAddr) const; 722846Ssaidi@eecs.umich.edu virtual Addr calcConfigAddr(int bus, int dev, int func) = 0; 732846Ssaidi@eecs.umich.edu virtual void registerPciDevice(uint8_t bus, uint8_t dev, uint8_t func, 742846Ssaidi@eecs.umich.edu uint8_t intr); 752846Ssaidi@eecs.umich.edu 762846Ssaidi@eecs.umich.edu private: 772846Ssaidi@eecs.umich.edu std::bitset<256> intLines; 782846Ssaidi@eecs.umich.edu std::set<uint32_t> pciDevices; 792846Ssaidi@eecs.umich.edu 80807SN/A}; 81807SN/A 821634SN/A#endif // __DEV_PLATFORM_HH__ 83