pcireg.h revision 3085 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 *          Miguel Serrano
30 */
31
32/* @file
33 * Device register definitions for a device's PCI config space
34 */
35
36#ifndef __PCIREG_H__
37#define __PCIREG_H__
38
39#include <sys/types.h>
40
41union PCIConfig {
42    uint8_t data[64];
43
44    struct {
45        uint16_t vendor;
46        uint16_t device;
47        uint16_t command;
48        uint16_t status;
49        uint8_t revision;
50        uint8_t progIF;
51        uint8_t subClassCode;
52        uint8_t classCode;
53        uint8_t cacheLineSize;
54        uint8_t latencyTimer;
55        uint8_t headerType;
56        uint8_t bist;
57        uint32_t baseAddr[6];
58        uint32_t cardbusCIS;
59        uint16_t subsystemVendorID;
60        uint16_t subsystemID;
61        uint32_t expansionROM;
62        uint32_t reserved0;
63        uint32_t reserved1;
64        uint8_t interruptLine;
65        uint8_t interruptPin;
66        uint8_t minimumGrant;
67        uint8_t maximumLatency;
68    };
69};
70
71// Common PCI offsets
72#define PCI_VENDOR_ID		0x00	// Vendor ID			ro
73#define PCI_DEVICE_ID		0x02	// Device ID			ro
74#define PCI_COMMAND		0x04	// Command			rw
75#define PCI_STATUS		0x06	// Status			rw
76#define PCI_REVISION_ID 	0x08	// Revision ID			ro
77#define PCI_CLASS_CODE		0x09	// Class Code			ro
78#define PCI_SUB_CLASS_CODE	0x0A	// Sub Class Code		ro
79#define PCI_BASE_CLASS_CODE	0x0B	// Base Class Code		ro
80#define PCI_CACHE_LINE_SIZE	0x0C	// Cache Line Size		ro+
81#define PCI_LATENCY_TIMER	0x0D	// Latency Timer		ro+
82#define PCI_HEADER_TYPE		0x0E	// Header Type			ro
83#define PCI_BIST		0x0F	// Built in self test		rw
84
85// some pci command reg bitfields
86#define PCI_CMD_BME     0x04 // Bus master function enable
87#define PCI_CMD_MSE     0x02 // Memory Space Access enable
88#define PCI_CMD_IOSE    0x01 // I/O space enable
89
90// Type 0 PCI offsets
91#define PCI0_BASE_ADDR0		0x10	// Base Address 0		rw
92#define PCI0_BASE_ADDR1		0x14	// Base Address 1		rw
93#define PCI0_BASE_ADDR2		0x18	// Base Address 2		rw
94#define PCI0_BASE_ADDR3		0x1C	// Base Address 3		rw
95#define PCI0_BASE_ADDR4		0x20	// Base Address 4		rw
96#define PCI0_BASE_ADDR5		0x24	// Base Address 5		rw
97#define PCI0_CIS		0x28	// CardBus CIS Pointer		ro
98#define PCI0_SUB_VENDOR_ID	0x2C	// Sub-Vendor ID		ro
99#define PCI0_SUB_SYSTEM_ID	0x2E	// Sub-System ID		ro
100#define PCI0_ROM_BASE_ADDR	0x30	// Expansion ROM Base Address	rw
101#define PCI0_RESERVED0		0x34
102#define PCI0_RESERVED1		0x38
103#define PCI0_INTERRUPT_LINE	0x3C	// Interrupt Line		rw
104#define PCI0_INTERRUPT_PIN	0x3D	// Interrupt Pin		ro
105#define PCI0_MINIMUM_GRANT	0x3E	// Maximum Grant		ro
106#define PCI0_MAXIMUM_LATENCY	0x3F	// Maximum Latency		ro
107
108// Type 1 PCI offsets
109#define PCI1_BASE_ADDR0		0x10	// Base Address 0		rw
110#define PCI1_BASE_ADDR1		0x14	// Base Address 1		rw
111#define PCI1_PRI_BUS_NUM	0x18	// Primary Bus Number		rw
112#define PCI1_SEC_BUS_NUM	0x19	// Secondary Bus Number		rw
113#define PCI1_SUB_BUS_NUM	0x1A	// Subordinate Bus Number	rw
114#define PCI1_SEC_LAT_TIMER	0x1B	// Secondary Latency Timer	ro+
115#define PCI1_IO_BASE		0x1C	// I/O Base			rw
116#define PCI1_IO_LIMIT		0x1D	// I/O Limit			rw
117#define PCI1_SECONDARY_STATUS	0x1E	// Secondary Status		rw
118#define PCI1_MEM_BASE		0x20	// Memory Base			rw
119#define PCI1_MEM_LIMIT		0x22	// Memory Limit			rw
120#define PCI1_PRF_MEM_BASE	0x24	// Prefetchable Memory Base	rw
121#define PCI1_PRF_MEM_LIMIT	0x26	// Prefetchable Memory Limit	rw
122#define PCI1_PRF_BASE_UPPER	0x28	// Prefetchable Base Upper 32	rw
123#define PCI1_PRF_LIMIT_UPPER	0x2C	// Prefetchable Limit Upper 32	rw
124#define PCI1_IO_BASE_UPPER	0x30	// I/O Base Upper 16 bits	rw
125#define PCI1_IO_LIMIT_UPPER	0x32	// I/O Limit Upper 16 bits	rw
126#define PCI1_RESERVED		0x34	// Reserved			ro
127#define PCI1_ROM_BASE_ADDR	0x38	// Expansion ROM Base Address	rw
128#define PCI1_INTR_LINE		0x3C	// Interrupt Line		rw
129#define PCI1_INTR_PIN		0x3D	// Interrupt Pin		ro
130#define PCI1_BRIDGE_CTRL	0x3E	// Bridge Control		rw
131
132// Device specific offsets
133#define PCI_DEVICE_SPECIFIC     	0x40	// 192 bytes
134#define PCI_CONFIG_SIZE         0xFF
135
136// Some Vendor IDs
137#define PCI_VENDOR_DEC			0x1011
138#define PCI_VENDOR_NCR			0x101A
139#define PCI_VENDOR_QLOGIC		0x1077
140#define PCI_VENDOR_SIMOS		0x1291
141
142// Some Product IDs
143#define PCI_PRODUCT_DEC_PZA		0x0008
144#define PCI_PRODUCT_NCR_810		0x0001
145#define PCI_PRODUCT_QLOGIC_ISP1020	0x1020
146#define PCI_PRODUCT_SIMOS_SIMOS		0x1291
147#define PCI_PRODUCT_SIMOS_ETHER		0x1292
148
149#endif // __PCIREG_H__
150