pcireg.h revision 1762
110259SAndrew.Bardsley@arm.com/*
210259SAndrew.Bardsley@arm.com * Copyright (c) 2001-2005 The Regents of The University of Michigan
310259SAndrew.Bardsley@arm.com * All rights reserved.
410259SAndrew.Bardsley@arm.com *
510259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without
610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are
710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright
810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer;
910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright
1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the
1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution;
1210259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its
1310259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from
1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission.
1510259SAndrew.Bardsley@arm.com *
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1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2010259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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2210259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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2510259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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2710259SAndrew.Bardsley@arm.com */
2810259SAndrew.Bardsley@arm.com
2910259SAndrew.Bardsley@arm.com/* @file
3010259SAndrew.Bardsley@arm.com * Device register definitions for a device's PCI config space
3110259SAndrew.Bardsley@arm.com */
3210259SAndrew.Bardsley@arm.com
3310259SAndrew.Bardsley@arm.com#ifndef __PCIREG_H__
3410259SAndrew.Bardsley@arm.com#define __PCIREG_H__
3510259SAndrew.Bardsley@arm.com
3610259SAndrew.Bardsley@arm.com#include <sys/types.h>
3710259SAndrew.Bardsley@arm.com
3810259SAndrew.Bardsley@arm.comunion PCIConfig {
3910259SAndrew.Bardsley@arm.com    uint8_t	data[64];
4010259SAndrew.Bardsley@arm.com
4110259SAndrew.Bardsley@arm.com    struct hdr {
4210259SAndrew.Bardsley@arm.com        uint16_t	vendor;
4310259SAndrew.Bardsley@arm.com        uint16_t	device;
4410259SAndrew.Bardsley@arm.com        uint16_t	command;
4510259SAndrew.Bardsley@arm.com        uint16_t	status;
4610259SAndrew.Bardsley@arm.com        uint8_t		revision;
4710259SAndrew.Bardsley@arm.com        uint8_t		progIF;
4810259SAndrew.Bardsley@arm.com        uint8_t		subClassCode;
4910259SAndrew.Bardsley@arm.com        uint8_t		classCode;
5010259SAndrew.Bardsley@arm.com        uint8_t		cacheLineSize;
5110259SAndrew.Bardsley@arm.com        uint8_t		latencyTimer;
5210259SAndrew.Bardsley@arm.com        uint8_t		headerType;
5310259SAndrew.Bardsley@arm.com        uint8_t		bist;
5410259SAndrew.Bardsley@arm.com
5510259SAndrew.Bardsley@arm.com        union {
5610259SAndrew.Bardsley@arm.com            struct {
5710259SAndrew.Bardsley@arm.com                uint32_t	baseAddr0;
5810259SAndrew.Bardsley@arm.com                uint32_t	baseAddr1;
5910259SAndrew.Bardsley@arm.com                uint32_t	baseAddr2;
6010259SAndrew.Bardsley@arm.com                uint32_t	baseAddr3;
6110259SAndrew.Bardsley@arm.com                uint32_t	baseAddr4;
6210259SAndrew.Bardsley@arm.com                uint32_t	baseAddr5;
6310259SAndrew.Bardsley@arm.com                uint32_t	cardbusCIS;
6410259SAndrew.Bardsley@arm.com                uint16_t	subsystemVendorID;
6510259SAndrew.Bardsley@arm.com                uint16_t	subsystemID;
6610259SAndrew.Bardsley@arm.com                uint32_t	expansionROM;
6710259SAndrew.Bardsley@arm.com                uint32_t	reserved0;
6810259SAndrew.Bardsley@arm.com                uint32_t	reserved1;
6910259SAndrew.Bardsley@arm.com                uint8_t		interruptLine;
7010259SAndrew.Bardsley@arm.com                uint8_t		interruptPin;
7110259SAndrew.Bardsley@arm.com                uint8_t		minimumGrant;
7210259SAndrew.Bardsley@arm.com                uint8_t		maximumLatency;
7310259SAndrew.Bardsley@arm.com            } pci0;
7410259SAndrew.Bardsley@arm.com
7510259SAndrew.Bardsley@arm.com            struct {
7610259SAndrew.Bardsley@arm.com                uint32_t	baseAddr0;
7710259SAndrew.Bardsley@arm.com                uint32_t	baseAddr1;
7810259SAndrew.Bardsley@arm.com                uint8_t		priBusNum;
7910259SAndrew.Bardsley@arm.com                uint8_t		secBusNum;
8010259SAndrew.Bardsley@arm.com                uint8_t		subBusNum;
8110259SAndrew.Bardsley@arm.com                uint8_t		secLatency;
8210259SAndrew.Bardsley@arm.com                uint8_t		ioBase;
8310259SAndrew.Bardsley@arm.com                uint8_t		minimumGrantioLimit;
8410259SAndrew.Bardsley@arm.com                uint16_t	secStatus;
8510259SAndrew.Bardsley@arm.com                uint16_t	memBase;
8610259SAndrew.Bardsley@arm.com                uint16_t	memLimit;
8710259SAndrew.Bardsley@arm.com                uint16_t	prefetchMemBase;
8810259SAndrew.Bardsley@arm.com                uint16_t	prefetchMemLimit;
8910259SAndrew.Bardsley@arm.com                uint32_t	prfBaseUpper32;
9010259SAndrew.Bardsley@arm.com                uint32_t	prfLimitUpper32;
9110259SAndrew.Bardsley@arm.com                uint16_t	ioBaseUpper16;
9210259SAndrew.Bardsley@arm.com                uint16_t	ioLimitUpper16;
9310259SAndrew.Bardsley@arm.com                uint32_t	reserved0;
9410259SAndrew.Bardsley@arm.com                uint32_t	expansionROM;
9510259SAndrew.Bardsley@arm.com                uint8_t		interruptLine;
9610259SAndrew.Bardsley@arm.com                uint8_t		interruptPin;
9710259SAndrew.Bardsley@arm.com                uint16_t	bridgeControl;
9810259SAndrew.Bardsley@arm.com            } pci1;
9910259SAndrew.Bardsley@arm.com        };
10010259SAndrew.Bardsley@arm.com    } hdr;
10110259SAndrew.Bardsley@arm.com};
10210259SAndrew.Bardsley@arm.com
10310259SAndrew.Bardsley@arm.com// Common PCI offsets
10410259SAndrew.Bardsley@arm.com#define PCI_VENDOR_ID		0x00	// Vendor ID			ro
10510259SAndrew.Bardsley@arm.com#define PCI_DEVICE_ID		0x02	// Device ID			ro
10610259SAndrew.Bardsley@arm.com#define PCI_COMMAND		0x04	// Command			rw
10710259SAndrew.Bardsley@arm.com#define PCI_STATUS		0x06	// Status			rw
10810259SAndrew.Bardsley@arm.com#define PCI_REVISION_ID 	0x08	// Revision ID			ro
10910259SAndrew.Bardsley@arm.com#define PCI_CLASS_CODE		0x09	// Class Code			ro
11010259SAndrew.Bardsley@arm.com#define PCI_SUB_CLASS_CODE	0x0A	// Sub Class Code		ro
11110259SAndrew.Bardsley@arm.com#define PCI_BASE_CLASS_CODE	0x0B	// Base Class Code		ro
11210259SAndrew.Bardsley@arm.com#define PCI_CACHE_LINE_SIZE	0x0C	// Cache Line Size		ro+
11310259SAndrew.Bardsley@arm.com#define PCI_LATENCY_TIMER	0x0D	// Latency Timer		ro+
11410259SAndrew.Bardsley@arm.com#define PCI_HEADER_TYPE		0x0E	// Header Type			ro
11510259SAndrew.Bardsley@arm.com#define PCI_BIST		0x0F	// Built in self test		rw
11610259SAndrew.Bardsley@arm.com
11710259SAndrew.Bardsley@arm.com// some pci command reg bitfields
11810259SAndrew.Bardsley@arm.com#define PCI_CMD_BME     0x04 // Bus master function enable
11910259SAndrew.Bardsley@arm.com#define PCI_CMD_MSE     0x02 // Memory Space Access enable
12010259SAndrew.Bardsley@arm.com#define PCI_CMD_IOSE    0x01 // I/O space enable
12110259SAndrew.Bardsley@arm.com
12210259SAndrew.Bardsley@arm.com// Type 0 PCI offsets
12310259SAndrew.Bardsley@arm.com#define PCI0_BASE_ADDR0		0x10	// Base Address 0		rw
12410259SAndrew.Bardsley@arm.com#define PCI0_BASE_ADDR1		0x14	// Base Address 1		rw
12510259SAndrew.Bardsley@arm.com#define PCI0_BASE_ADDR2		0x18	// Base Address 2		rw
12610259SAndrew.Bardsley@arm.com#define PCI0_BASE_ADDR3		0x1C	// Base Address 3		rw
12710259SAndrew.Bardsley@arm.com#define PCI0_BASE_ADDR4		0x20	// Base Address 4		rw
12810259SAndrew.Bardsley@arm.com#define PCI0_BASE_ADDR5		0x24	// Base Address 5		rw
12910259SAndrew.Bardsley@arm.com#define PCI0_CIS		0x28	// CardBus CIS Pointer		ro
13010259SAndrew.Bardsley@arm.com#define PCI0_SUB_VENDOR_ID	0x2C	// Sub-Vendor ID		ro
13110259SAndrew.Bardsley@arm.com#define PCI0_SUB_SYSTEM_ID	0x2E	// Sub-System ID		ro
13210259SAndrew.Bardsley@arm.com#define PCI0_ROM_BASE_ADDR	0x30	// Expansion ROM Base Address	rw
13310259SAndrew.Bardsley@arm.com#define PCI0_RESERVED0		0x34
13410259SAndrew.Bardsley@arm.com#define PCI0_RESERVED1		0x38
13510259SAndrew.Bardsley@arm.com#define PCI0_INTERRUPT_LINE	0x3C	// Interrupt Line		rw
13610259SAndrew.Bardsley@arm.com#define PCI0_INTERRUPT_PIN	0x3D	// Interrupt Pin		ro
13710259SAndrew.Bardsley@arm.com#define PCI0_MINIMUM_GRANT	0x3E	// Maximum Grant		ro
13810259SAndrew.Bardsley@arm.com#define PCI0_MAXIMUM_LATENCY	0x3F	// Maximum Latency		ro
13910259SAndrew.Bardsley@arm.com
14010259SAndrew.Bardsley@arm.com// Type 1 PCI offsets
14110259SAndrew.Bardsley@arm.com#define PCI1_BASE_ADDR0		0x10	// Base Address 0		rw
14210259SAndrew.Bardsley@arm.com#define PCI1_BASE_ADDR1		0x14	// Base Address 1		rw
14310259SAndrew.Bardsley@arm.com#define PCI1_PRI_BUS_NUM	0x18	// Primary Bus Number		rw
14410259SAndrew.Bardsley@arm.com#define PCI1_SEC_BUS_NUM	0x19	// Secondary Bus Number		rw
14510259SAndrew.Bardsley@arm.com#define PCI1_SUB_BUS_NUM	0x1A	// Subordinate Bus Number	rw
14610259SAndrew.Bardsley@arm.com#define PCI1_SEC_LAT_TIMER	0x1B	// Secondary Latency Timer	ro+
14710259SAndrew.Bardsley@arm.com#define PCI1_IO_BASE		0x1C	// I/O Base			rw
14810259SAndrew.Bardsley@arm.com#define PCI1_IO_LIMIT		0x1D	// I/O Limit			rw
14910259SAndrew.Bardsley@arm.com#define PCI1_SECONDARY_STATUS	0x1E	// Secondary Status		rw
15010259SAndrew.Bardsley@arm.com#define PCI1_MEM_BASE		0x20	// Memory Base			rw
15110259SAndrew.Bardsley@arm.com#define PCI1_MEM_LIMIT		0x22	// Memory Limit			rw
15210259SAndrew.Bardsley@arm.com#define PCI1_PRF_MEM_BASE	0x24	// Prefetchable Memory Base	rw
15310259SAndrew.Bardsley@arm.com#define PCI1_PRF_MEM_LIMIT	0x26	// Prefetchable Memory Limit	rw
15410259SAndrew.Bardsley@arm.com#define PCI1_PRF_BASE_UPPER	0x28	// Prefetchable Base Upper 32	rw
15510259SAndrew.Bardsley@arm.com#define PCI1_PRF_LIMIT_UPPER	0x2C	// Prefetchable Limit Upper 32	rw
15610259SAndrew.Bardsley@arm.com#define PCI1_IO_BASE_UPPER	0x30	// I/O Base Upper 16 bits	rw
15710259SAndrew.Bardsley@arm.com#define PCI1_IO_LIMIT_UPPER	0x32	// I/O Limit Upper 16 bits	rw
15810259SAndrew.Bardsley@arm.com#define PCI1_RESERVED		0x34	// Reserved			ro
15910259SAndrew.Bardsley@arm.com#define PCI1_ROM_BASE_ADDR	0x38	// Expansion ROM Base Address	rw
16010259SAndrew.Bardsley@arm.com#define PCI1_INTR_LINE		0x3C	// Interrupt Line		rw
16110259SAndrew.Bardsley@arm.com#define PCI1_INTR_PIN		0x3D	// Interrupt Pin		ro
16210259SAndrew.Bardsley@arm.com#define PCI1_BRIDGE_CTRL	0x3E	// Bridge Control		rw
16310259SAndrew.Bardsley@arm.com
16410259SAndrew.Bardsley@arm.com// Device specific offsets
16510259SAndrew.Bardsley@arm.com#define PCI_DEVICE_SPECIFIC     	0x40	// 192 bytes
16610259SAndrew.Bardsley@arm.com
16710259SAndrew.Bardsley@arm.com// Some Vendor IDs
16810259SAndrew.Bardsley@arm.com#define PCI_VENDOR_DEC			0x1011
16910259SAndrew.Bardsley@arm.com#define PCI_VENDOR_NCR			0x101A
17010259SAndrew.Bardsley@arm.com#define PCI_VENDOR_QLOGIC		0x1077
17110259SAndrew.Bardsley@arm.com#define PCI_VENDOR_SIMOS		0x1291
17210259SAndrew.Bardsley@arm.com
17310259SAndrew.Bardsley@arm.com// Some Product IDs
17410259SAndrew.Bardsley@arm.com#define PCI_PRODUCT_DEC_PZA		0x0008
17510259SAndrew.Bardsley@arm.com#define PCI_PRODUCT_NCR_810		0x0001
17610259SAndrew.Bardsley@arm.com#define PCI_PRODUCT_QLOGIC_ISP1020	0x1020
17710259SAndrew.Bardsley@arm.com#define PCI_PRODUCT_SIMOS_SIMOS		0x1291
17810259SAndrew.Bardsley@arm.com#define PCI_PRODUCT_SIMOS_ETHER		0x1292
17910259SAndrew.Bardsley@arm.com
18010259SAndrew.Bardsley@arm.com#endif // __PCIREG_H__
18110259SAndrew.Bardsley@arm.com