pcireg.h revision 2
110152Satgutier@umich.edu/* 210152Satgutier@umich.edu * Copyright (c) 2003 The Regents of The University of Michigan 310152Satgutier@umich.edu * All rights reserved. 410152Satgutier@umich.edu * 510152Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 610152Satgutier@umich.edu * modification, are permitted provided that the following conditions are 710152Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 810152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 910152Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1010152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 1110152Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 1210152Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 1310152Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 1410152Satgutier@umich.edu * this software without specific prior written permission. 1510152Satgutier@umich.edu * 1610152Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710152Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810152Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910152Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010152Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110152Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210152Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310152Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410152Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510152Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610152Satgutier@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710152Satgutier@umich.edu */ 2810152Satgutier@umich.edu 2910152Satgutier@umich.edu/* @file 3010152Satgutier@umich.edu * Device register definitions for a device's PCI config space 3110152Satgutier@umich.edu */ 3210152Satgutier@umich.edu 3310152Satgutier@umich.edu#ifndef __PCIREG_H__ 3410152Satgutier@umich.edu#define __PCIREG_H__ 3510152Satgutier@umich.edu 3610152Satgutier@umich.edu#include <sys/types.h> 3710152Satgutier@umich.edu 3810152Satgutier@umich.eduunion PCIConfig { 3910152Satgutier@umich.edu uint8_t data[64]; 4010152Satgutier@umich.edu 4110152Satgutier@umich.edu struct hdr { 4210152Satgutier@umich.edu uint16_t vendor; 4310152Satgutier@umich.edu uint16_t device; 4410152Satgutier@umich.edu uint16_t command; 4510152Satgutier@umich.edu uint16_t status; 4610152Satgutier@umich.edu uint8_t revision; 4710152Satgutier@umich.edu uint8_t progIF; 4810152Satgutier@umich.edu uint8_t subClassCode; 4910152Satgutier@umich.edu uint8_t classCode; 5010152Satgutier@umich.edu uint8_t cacheLineSize; 5110152Satgutier@umich.edu uint8_t latencyTimer; 5210152Satgutier@umich.edu uint8_t headerType; 5310152Satgutier@umich.edu uint8_t bist; 5410152Satgutier@umich.edu 5510152Satgutier@umich.edu union { 5610152Satgutier@umich.edu struct { 5710152Satgutier@umich.edu uint32_t baseAddr0; 5810152Satgutier@umich.edu uint32_t baseAddr1; 5910152Satgutier@umich.edu uint32_t baseAddr2; 6010152Satgutier@umich.edu uint32_t baseAddr3; 6110152Satgutier@umich.edu uint32_t baseAddr4; 6210152Satgutier@umich.edu uint32_t baseAddr5; 6310152Satgutier@umich.edu uint32_t cardbusCIS; 6410152Satgutier@umich.edu uint16_t subsystemVendorID; 6510152Satgutier@umich.edu uint16_t subsystemID; 6610152Satgutier@umich.edu uint32_t expansionROM; 6710152Satgutier@umich.edu uint32_t reserved0; 6810152Satgutier@umich.edu uint32_t reserved1; 6910152Satgutier@umich.edu uint8_t interruptLine; 7010152Satgutier@umich.edu uint8_t interruptPin; 7110152Satgutier@umich.edu uint8_t minimumGrant; 7210152Satgutier@umich.edu uint8_t maximumLatency; 7310152Satgutier@umich.edu } pci0; 7410152Satgutier@umich.edu 7510152Satgutier@umich.edu struct { 7610152Satgutier@umich.edu uint32_t baseAddr0; 7710152Satgutier@umich.edu uint32_t baseAddr1; 7810152Satgutier@umich.edu uint8_t priBusNum; 7910152Satgutier@umich.edu uint8_t secBusNum; 8010152Satgutier@umich.edu uint8_t subBusNum; 8110152Satgutier@umich.edu uint8_t secLatency; 8210152Satgutier@umich.edu uint8_t ioBase; 8310152Satgutier@umich.edu uint8_t minimumGrantioLimit; 8410152Satgutier@umich.edu uint16_t secStatus; 8510152Satgutier@umich.edu uint16_t memBase; 8610152Satgutier@umich.edu uint16_t memLimit; 8710152Satgutier@umich.edu uint16_t prefetchMemBase; 8810152Satgutier@umich.edu uint16_t prefetchMemLimit; 8910152Satgutier@umich.edu uint32_t prfBaseUpper32; 9010152Satgutier@umich.edu uint32_t prfLimitUpper32; 9110152Satgutier@umich.edu uint16_t ioBaseUpper16; 9210152Satgutier@umich.edu uint16_t ioLimitUpper16; 9310152Satgutier@umich.edu uint32_t reserved0; 9410152Satgutier@umich.edu uint32_t expansionROM; 9510152Satgutier@umich.edu uint8_t interruptLine; 9610152Satgutier@umich.edu uint8_t interruptPin; 9710152Satgutier@umich.edu uint16_t bridgeControl; 9810152Satgutier@umich.edu } pci1; 9910152Satgutier@umich.edu }; 10010152Satgutier@umich.edu } hdr; 10110152Satgutier@umich.edu}; 10210152Satgutier@umich.edu 10310152Satgutier@umich.edu// Common PCI offsets 10410152Satgutier@umich.edu#define PCI_VENDOR_ID 0x00 // Vendor ID ro 10510152Satgutier@umich.edu#define PCI_DEVICE_ID 0x02 // Device ID ro 10610152Satgutier@umich.edu#define PCI_COMMAND 0x04 // Command rw 10710152Satgutier@umich.edu#define PCI_STATUS 0x06 // Status rw 10810152Satgutier@umich.edu#define PCI_REVISION_ID 0x08 // Revision ID ro 10910152Satgutier@umich.edu#define PCI_CLASS_CODE 0x09 // Class Code ro 11010152Satgutier@umich.edu#define PCI_SUB_CLASS_CODE 0x0A // Sub Class Code ro 11110152Satgutier@umich.edu#define PCI_BASE_CLASS_CODE 0x0B // Base Class Code ro 11210152Satgutier@umich.edu#define PCI_CACHE_LINE_SIZE 0x0C // Cache Line Size ro+ 11310152Satgutier@umich.edu#define PCI_LATENCY_TIMER 0x0D // Latency Timer ro+ 11410152Satgutier@umich.edu#define PCI_HEADER_TYPE 0x0E // Header Type ro 11510152Satgutier@umich.edu#define PCI_BIST 0x0F // Built in self test rw 11610152Satgutier@umich.edu 11710152Satgutier@umich.edu// Type 0 PCI offsets 11810152Satgutier@umich.edu#define PCI0_BASE_ADDR0 0x10 // Base Address 0 rw 11910152Satgutier@umich.edu#define PCI0_BASE_ADDR1 0x14 // Base Address 1 rw 12010152Satgutier@umich.edu#define PCI0_BASE_ADDR2 0x18 // Base Address 2 rw 12110152Satgutier@umich.edu#define PCI0_BASE_ADDR3 0x1C // Base Address 3 rw 12210152Satgutier@umich.edu#define PCI0_BASE_ADDR4 0x20 // Base Address 4 rw 12310152Satgutier@umich.edu#define PCI0_BASE_ADDR5 0x24 // Base Address 5 rw 12410152Satgutier@umich.edu#define PCI0_CIS 0x28 // CardBus CIS Pointer ro 12510152Satgutier@umich.edu#define PCI0_SUB_VENDOR_ID 0x2C // Sub-Vendor ID ro 12610152Satgutier@umich.edu#define PCI0_SUB_SYSTEM_ID 0x2E // Sub-System ID ro 12710152Satgutier@umich.edu#define PCI0_ROM_BASE_ADDR 0x30 // Expansion ROM Base Address rw 12810152Satgutier@umich.edu#define PCI0_RESERVED0 0x34 12910152Satgutier@umich.edu#define PCI0_RESERVED1 0x38 13010152Satgutier@umich.edu#define PCI0_INTERRUPT_LINE 0x3C // Interrupt Line rw 13110152Satgutier@umich.edu#define PCI0_INTERRUPT_PIN 0x3D // Interrupt Pin ro 13210152Satgutier@umich.edu#define PCI0_MINIMUM_GRANT 0x3E // Maximum Grant ro 13310152Satgutier@umich.edu#define PCI0_MAXIMUM_LATENCY 0x3F // Maximum Latency ro 13410152Satgutier@umich.edu 13510152Satgutier@umich.edu// Type 1 PCI offsets 13610152Satgutier@umich.edu#define PCI1_BASE_ADDR0 0x10 // Base Address 0 rw 13710152Satgutier@umich.edu#define PCI1_BASE_ADDR1 0x14 // Base Address 1 rw 13810152Satgutier@umich.edu#define PCI1_PRI_BUS_NUM 0x18 // Primary Bus Number rw 13910152Satgutier@umich.edu#define PCI1_SEC_BUS_NUM 0x19 // Secondary Bus Number rw 14010152Satgutier@umich.edu#define PCI1_SUB_BUS_NUM 0x1A // Subordinate Bus Number rw 14110152Satgutier@umich.edu#define PCI1_SEC_LAT_TIMER 0x1B // Secondary Latency Timer ro+ 14210152Satgutier@umich.edu#define PCI1_IO_BASE 0x1C // I/O Base rw 14310152Satgutier@umich.edu#define PCI1_IO_LIMIT 0x1D // I/O Limit rw 14410152Satgutier@umich.edu#define PCI1_SECONDARY_STATUS 0x1E // Secondary Status rw 14510152Satgutier@umich.edu#define PCI1_MEM_BASE 0x20 // Memory Base rw 14610152Satgutier@umich.edu#define PCI1_MEM_LIMIT 0x22 // Memory Limit rw 14710152Satgutier@umich.edu#define PCI1_PRF_MEM_BASE 0x24 // Prefetchable Memory Base rw 14810152Satgutier@umich.edu#define PCI1_PRF_MEM_LIMIT 0x26 // Prefetchable Memory Limit rw 14910152Satgutier@umich.edu#define PCI1_PRF_BASE_UPPER 0x28 // Prefetchable Base Upper 32 rw 15010152Satgutier@umich.edu#define PCI1_PRF_LIMIT_UPPER 0x2C // Prefetchable Limit Upper 32 rw 15110152Satgutier@umich.edu#define PCI1_IO_BASE_UPPER 0x30 // I/O Base Upper 16 bits rw 15210152Satgutier@umich.edu#define PCI1_IO_LIMIT_UPPER 0x32 // I/O Limit Upper 16 bits rw 15310152Satgutier@umich.edu#define PCI1_RESERVED 0x34 // Reserved ro 15410152Satgutier@umich.edu#define PCI1_ROM_BASE_ADDR 0x38 // Expansion ROM Base Address rw 15510152Satgutier@umich.edu#define PCI1_INTR_LINE 0x3C // Interrupt Line rw 15610152Satgutier@umich.edu#define PCI1_INTR_PIN 0x3D // Interrupt Pin ro 15710152Satgutier@umich.edu#define PCI1_BRIDGE_CTRL 0x3E // Bridge Control rw 15810152Satgutier@umich.edu 15910152Satgutier@umich.edu// Device specific offsets 16010152Satgutier@umich.edu#define PCI_DEVICE_SPECIFIC 0x40 // 192 bytes 16110152Satgutier@umich.edu 16210152Satgutier@umich.edu// Some Vendor IDs 16310152Satgutier@umich.edu#define PCI_VENDOR_DEC 0x1011 16410152Satgutier@umich.edu#define PCI_VENDOR_NCR 0x101A 16510152Satgutier@umich.edu#define PCI_VENDOR_QLOGIC 0x1077 16610152Satgutier@umich.edu#define PCI_VENDOR_SIMOS 0x1291 16710152Satgutier@umich.edu 16810152Satgutier@umich.edu// Some Product IDs 16910152Satgutier@umich.edu#define PCI_PRODUCT_DEC_PZA 0x0008 17010152Satgutier@umich.edu#define PCI_PRODUCT_NCR_810 0x0001 17110152Satgutier@umich.edu#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 17210152Satgutier@umich.edu#define PCI_PRODUCT_SIMOS_SIMOS 0x1291 17310152Satgutier@umich.edu#define PCI_PRODUCT_SIMOS_ETHER 0x1292 17410152Satgutier@umich.edu 17510152Satgutier@umich.edu#endif // __PCIREG_H__ 17610152Satgutier@umich.edu