pcireg.h revision 10479
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Nathan Binkert
41 *          Miguel Serrano
42 */
43
44/* @file
45 * Device register definitions for a device's PCI config space
46 */
47
48#ifndef __PCIREG_H__
49#define __PCIREG_H__
50
51#include <sys/types.h>
52
53#include "base/bitfield.hh"
54#include "base/bitunion.hh"
55
56union PCIConfig {
57    uint8_t data[64];
58
59    struct {
60        uint16_t vendor;
61        uint16_t device;
62        uint16_t command;
63        uint16_t status;
64        uint8_t revision;
65        uint8_t progIF;
66        uint8_t subClassCode;
67        uint8_t classCode;
68        uint8_t cacheLineSize;
69        uint8_t latencyTimer;
70        uint8_t headerType;
71        uint8_t bist;
72        uint32_t baseAddr[6];
73        uint32_t cardbusCIS;
74        uint16_t subsystemVendorID;
75        uint16_t subsystemID;
76        uint32_t expansionROM;
77        uint8_t capabilityPtr;
78        // Was 8 bytes in the legacy PCI spec, but to support PCIe
79        // this field is now 7 bytes with PCIe's addition of the
80        // capability list pointer.
81        uint8_t reserved[7];
82        uint8_t interruptLine;
83        uint8_t interruptPin;
84        uint8_t minimumGrant;
85        uint8_t maximumLatency;
86    };
87};
88
89// Common PCI offsets
90#define PCI_VENDOR_ID           0x00    // Vendor ID                    ro
91#define PCI_DEVICE_ID           0x02    // Device ID                    ro
92#define PCI_COMMAND             0x04    // Command                      rw
93#define PCI_STATUS              0x06    // Status                       rw
94#define PCI_REVISION_ID         0x08    // Revision ID                  ro
95#define PCI_CLASS_CODE          0x09    // Class Code                   ro
96#define PCI_SUB_CLASS_CODE      0x0A    // Sub Class Code               ro
97#define PCI_BASE_CLASS_CODE     0x0B    // Base Class Code              ro
98#define PCI_CACHE_LINE_SIZE     0x0C    // Cache Line Size              ro+
99#define PCI_LATENCY_TIMER       0x0D    // Latency Timer                ro+
100#define PCI_HEADER_TYPE         0x0E    // Header Type                  ro
101#define PCI_BIST                0x0F    // Built in self test           rw
102
103// some pci command reg bitfields
104#define PCI_CMD_BME     0x04 // Bus master function enable
105#define PCI_CMD_MSE     0x02 // Memory Space Access enable
106#define PCI_CMD_IOSE    0x01 // I/O space enable
107
108// Type 0 PCI offsets
109#define PCI0_BASE_ADDR0         0x10    // Base Address 0               rw
110#define PCI0_BASE_ADDR1         0x14    // Base Address 1               rw
111#define PCI0_BASE_ADDR2         0x18    // Base Address 2               rw
112#define PCI0_BASE_ADDR3         0x1C    // Base Address 3               rw
113#define PCI0_BASE_ADDR4         0x20    // Base Address 4               rw
114#define PCI0_BASE_ADDR5         0x24    // Base Address 5               rw
115#define PCI0_CIS                0x28    // CardBus CIS Pointer          ro
116#define PCI0_SUB_VENDOR_ID      0x2C    // Sub-Vendor ID                ro
117#define PCI0_SUB_SYSTEM_ID      0x2E    // Sub-System ID                ro
118#define PCI0_ROM_BASE_ADDR      0x30    // Expansion ROM Base Address   rw
119#define PCI0_CAP_PTR            0x34    // Capability list pointer      ro
120#define PCI0_RESERVED           0x35
121#define PCI0_INTERRUPT_LINE     0x3C    // Interrupt Line               rw
122#define PCI0_INTERRUPT_PIN      0x3D    // Interrupt Pin                ro
123#define PCI0_MINIMUM_GRANT      0x3E    // Maximum Grant                ro
124#define PCI0_MAXIMUM_LATENCY    0x3F    // Maximum Latency              ro
125
126// Type 1 PCI offsets
127#define PCI1_BASE_ADDR0         0x10    // Base Address 0               rw
128#define PCI1_BASE_ADDR1         0x14    // Base Address 1               rw
129#define PCI1_PRI_BUS_NUM        0x18    // Primary Bus Number           rw
130#define PCI1_SEC_BUS_NUM        0x19    // Secondary Bus Number         rw
131#define PCI1_SUB_BUS_NUM        0x1A    // Subordinate Bus Number       rw
132#define PCI1_SEC_LAT_TIMER      0x1B    // Secondary Latency Timer      ro+
133#define PCI1_IO_BASE            0x1C    // I/O Base                     rw
134#define PCI1_IO_LIMIT           0x1D    // I/O Limit                    rw
135#define PCI1_SECONDARY_STATUS   0x1E    // Secondary Status             rw
136#define PCI1_MEM_BASE           0x20    // Memory Base                  rw
137#define PCI1_MEM_LIMIT          0x22    // Memory Limit                 rw
138#define PCI1_PRF_MEM_BASE       0x24    // Prefetchable Memory Base     rw
139#define PCI1_PRF_MEM_LIMIT      0x26    // Prefetchable Memory Limit    rw
140#define PCI1_PRF_BASE_UPPER     0x28    // Prefetchable Base Upper 32   rw
141#define PCI1_PRF_LIMIT_UPPER    0x2C    // Prefetchable Limit Upper 32  rw
142#define PCI1_IO_BASE_UPPER      0x30    // I/O Base Upper 16 bits       rw
143#define PCI1_IO_LIMIT_UPPER     0x32    // I/O Limit Upper 16 bits      rw
144#define PCI1_RESERVED           0x34    // Reserved                     ro
145#define PCI1_ROM_BASE_ADDR      0x38    // Expansion ROM Base Address   rw
146#define PCI1_INTR_LINE          0x3C    // Interrupt Line               rw
147#define PCI1_INTR_PIN           0x3D    // Interrupt Pin                ro
148#define PCI1_BRIDGE_CTRL        0x3E    // Bridge Control               rw
149
150// Device specific offsets
151#define PCI_DEVICE_SPECIFIC             0x40    // 192 bytes
152#define PCI_CONFIG_SIZE         0xFF
153
154// Some Vendor IDs
155#define PCI_VENDOR_DEC                  0x1011
156#define PCI_VENDOR_NCR                  0x101A
157#define PCI_VENDOR_QLOGIC               0x1077
158#define PCI_VENDOR_SIMOS                0x1291
159
160// Some Product IDs
161#define PCI_PRODUCT_DEC_PZA             0x0008
162#define PCI_PRODUCT_NCR_810             0x0001
163#define PCI_PRODUCT_QLOGIC_ISP1020      0x1020
164#define PCI_PRODUCT_SIMOS_SIMOS         0x1291
165#define PCI_PRODUCT_SIMOS_ETHER         0x1292
166
167/**
168 * PCIe capability list offsets internal to the entry.
169 * Actual offsets in the PCI config space are defined in
170 * the python files setting up the system.
171 */
172#define PMCAP_ID 0x00
173#define PMCAP_PC 0x02
174#define PMCAP_PMCS 0x04
175#define PMCAP_SIZE 0x06
176
177#define MSICAP_ID 0x00
178#define MSICAP_MC 0x02
179#define MSICAP_MA 0x04
180#define MSICAP_MUA 0x08
181#define MSICAP_MD 0x0C
182#define MSICAP_MMASK 0x10
183#define MSICAP_MPEND 0x14
184#define MSICAP_SIZE 0x18
185
186#define MSIXCAP_ID 0x00
187#define MSIXCAP_MXC 0x02
188#define MSIXCAP_MTAB 0x04
189#define MSIXCAP_MPBA 0x08
190#define MSIXCAP_SIZE 0x0C
191
192#define PXCAP_ID 0x00
193#define PXCAP_PXCAP 0x02
194#define PXCAP_PXDCAP 0x04
195#define PXCAP_PXDC 0x08
196#define PXCAP_PXDS 0x0A
197#define PXCAP_PXLCAP 0x0C
198#define PXCAP_PXLC 0x10
199#define PXCAP_PXLS 0x12
200#define PXCAP_PXDCAP2 0x24
201#define PXCAP_PXDC2 0x28
202#define PXCAP_SIZE 0x30
203
204/** @struct PMCAP
205 *  Defines the Power Management capability register and all its associated
206 *  bitfields for a PCIe device.
207 */
208union PMCAP {
209    uint8_t data[6];
210    struct {
211        uint16_t pid;  /* 0:7  cid
212                        * 8:15 next
213                        */
214        uint16_t pc;   /* 0:2   vs
215                        * 3     pmec
216                        * 4     reserved
217                        * 5     dsi
218                        * 6:8   auxc
219                        * 9     d1s
220                        * 10    d2s
221                        * 11:15 psup
222                        */
223        uint16_t pmcs; /* 0:1   ps
224                        * 2     reserved
225                        * 3     nsfrst
226                        * 4:7   reserved
227                        * 8     pmee
228                        * 9:12  dse
229                        * 13:14 dsc
230                        * 15    pmes
231                        */
232    };
233};
234
235/** @struct MSICAP
236 *  Defines the MSI Capability register and its associated bitfields for
237 *  the a PCI/PCIe device.  Both the MSI capability and the MSIX capability
238 *  can be filled in if a device model supports both, but only 1 of
239 *  MSI/MSIX/INTx interrupt mode can be selected at a given time.
240 */
241union MSICAP {
242    uint8_t data[24];
243    struct {
244        uint16_t mid;  /* 0:7  cid
245                        *  8:15 next
246                        */
247        uint16_t mc;   /* 0     msie;
248                        * 1:3   mmc;
249                        * 4:6   mme;
250                        * 7     c64;
251                        * 8     pvm;
252                        * 9:15  reserved;
253                        */
254        uint32_t ma;   /* 0:1  reserved
255                        * 2:31 addr
256                        */
257        uint32_t mua;
258        uint16_t md;
259        uint32_t mmask;
260        uint32_t mpend;
261   };
262};
263
264/** @struct MSIX
265 *  Defines the MSI-X Capability register and its associated bitfields for
266 *  a PCIe device.
267 */
268union MSIXCAP {
269    uint8_t data[12];
270    struct {
271        uint16_t mxid; /* 0:7  cid
272                        *  8:15 next
273                        */
274        uint16_t mxc;  /* 0:10  ts;
275                        * 11:13 reserved;
276                        * 14    fm;
277                        * 15    mxe;
278                        */
279        uint32_t mtab; /* 0:2   tbir;
280                        * 3:31  to;
281                        */
282        uint32_t mpba; /* 0:2   pbir;
283                        * 3:31>  pbao;
284                        */
285    };
286};
287
288union MSIXTable {
289    struct {
290        uint32_t addr_lo;
291        uint32_t addr_hi;
292        uint32_t msg_data;
293        uint32_t vec_ctrl;
294    } fields;
295    uint32_t data[4];
296};
297
298#define MSIXVECS_PER_PBA 64
299struct MSIXPbaEntry {
300    uint64_t bits;
301};
302
303/** @struct PXCAP
304 *  Defines the PCI Express capability register and its associated bitfields
305 *  for a PCIe device.
306 */
307struct PXCAP {
308    uint8_t data[48];
309    struct {
310        uint16_t pxid; /* 0:7  cid
311                        *  8:15 next
312                        */
313        uint16_t pxcap; /* 0:3   ver;
314                         * 4:7   dpt;
315                         * 8     si;
316                         * 9:13  imn;
317                         * 14:15 reserved;
318                         */
319        uint32_t pxdcap; /* 0:2   mps;
320                          * 3:4   pfs;
321                          * 5     etfs;
322                          * 6:8   l0sl;
323                          * 9:11  l1l;
324                          * 12:14 reserved;
325                          * 15    rer;
326                          * 16:17 reserved;
327                          * 18:25 csplv;
328                          * 26:27 cspls;
329                          * 28    flrc;
330                          * 29:31 reserved;
331                          */
332        uint16_t pxdc; /* 0     cere;
333                        * 1     nfere;
334                        * 2     fere;
335                        * 3     urre;
336                        * 4     ero;
337                        * 5:7   mps;
338                        * 8     ete;
339                        * 9     pfe;
340                        * 10    appme;
341                        * 11    ens;
342                        * 12:14 mrrs;
343                        * 15    func_reset;
344                        */
345        uint16_t pxds; /* 0     ced;
346                        * 1     nfed;
347                        * 2     fed;
348                        * 3     urd;
349                        * 4     apd;
350                        * 5     tp;
351                        * 6:15  reserved;
352                        */
353        uint32_t pxlcap; /* 0:3   sls;
354                          * 4:9   mlw;
355                          * 10:11 aspms;
356                          * 12:14 l0sel;
357                          * 15:17 l1el;
358                          * 18    cpm;
359                          * 19    sderc;
360                          * 20    dllla;
361                          * 21    lbnc;
362                          * 22:23 reserved;
363                          * 24:31 pn;
364                          */
365        uint16_t pxlc; /* 0:1   aspmc;
366                        * 2     reserved;
367                        * 3     rcb;
368                        * 4:5   reserved;
369                        * 6     ccc;
370                        * 7     es;
371                        * 8     ecpm;
372                        * 9     hawd;
373                        * 10:15 reserved;
374                        */
375        uint16_t pxls; /* 0:3   cls;
376                        * 4:9   nlw;
377                        * 10:11 reserved;
378                        * 12    slot_clk_config;
379                        * 13:15 reserved;
380                        */
381        uint8_t reserved[20];
382        uint32_t pxdcap2; /* 0:3   ctrs;
383                           * 4     ctds;
384                           * 5     arifs;
385                           * 6     aors;
386                           * 7     aocs32;
387                           * 8     aocs64;
388                           * 9     ccs128;
389                           * 10    nprpr;
390                           * 11    ltrs;
391                           * 12:13 tphcs;
392                           * 14:17 reserved;
393                           * 18:19 obffs;
394                           * 20    effs;
395                           * 21    eetps;
396                           * 22:23 meetp;
397                           * 24:31 reserved;
398                           */
399        uint32_t pxdc2; /* 0:3   ctv;
400                         * 4     ctd;
401                         * 5:9   reserved;
402                         * 10    ltrme;
403                         * 11:12 reserved;
404                         * 13:14 obffe;
405                         * 15:31 reserved;
406                         */
407    };
408};
409#endif // __PCIREG_H__
410