device.hh revision 795
114283Sgiacomo.travaglini@arm.com/* 214283Sgiacomo.travaglini@arm.com * Copyright (c) 2003 The Regents of The University of Michigan 314283Sgiacomo.travaglini@arm.com * All rights reserved. 414283Sgiacomo.travaglini@arm.com * 514283Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 614283Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 714283Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 814283Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 914283Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1014283Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 1114283Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 1214283Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 1314283Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 1414283Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 1514283Sgiacomo.travaglini@arm.com * 1614283Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1714283Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1814283Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1914283Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2014283Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2114283Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2214283Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2314283Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2414283Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2514283Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2614283Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2714283Sgiacomo.travaglini@arm.com */ 2814283Sgiacomo.travaglini@arm.com 2914283Sgiacomo.travaglini@arm.com/* @file 3014283Sgiacomo.travaglini@arm.com * PCI configspace devices 3114283Sgiacomo.travaglini@arm.com */ 3214283Sgiacomo.travaglini@arm.com 3314283Sgiacomo.travaglini@arm.com#ifndef __PCI_DEV_HH__ 3414283Sgiacomo.travaglini@arm.com#define __PCI_DEV_HH__ 3514283Sgiacomo.travaglini@arm.com 3614283Sgiacomo.travaglini@arm.com#include "mem/functional_mem/mmap_device.hh" 3714283Sgiacomo.travaglini@arm.com#include "dev/pcireg.h" 3814283Sgiacomo.travaglini@arm.com 3914283Sgiacomo.travaglini@arm.comclass PCIConfigAll; 4014283Sgiacomo.travaglini@arm.com 4114283Sgiacomo.travaglini@arm.com/** 4214283Sgiacomo.travaglini@arm.com * PCI device, base implemnation is only config space. 4314283Sgiacomo.travaglini@arm.com * Each device is connected to a PCIConfigSpace device 4414283Sgiacomo.travaglini@arm.com * which returns -1 for everything but the pcidevs that 4514283Sgiacomo.travaglini@arm.com * register with it. This object registers with the PCIConfig space 4614283Sgiacomo.travaglini@arm.com * object. 4714283Sgiacomo.travaglini@arm.com */ 4814283Sgiacomo.travaglini@arm.comclass PciDev : public MmapDevice 4914283Sgiacomo.travaglini@arm.com{ 5014283Sgiacomo.travaglini@arm.com private: 5114283Sgiacomo.travaglini@arm.com uint32_t Bus; 5214283Sgiacomo.travaglini@arm.com uint32_t Device; 5314283Sgiacomo.travaglini@arm.com uint32_t Function; 54 public: 55 PciDev(const std::string &name, PCIConfigAll *cf, uint32_t bus, 56 uint32_t dev, uint32_t func); 57 58 PCIConfigAll *ConfigSpace; 59 PCIConfig config; 60 uint32_t BARSize[6]; 61 Addr BARAddrs[6]; 62 63 virtual void WriteConfig(int offset, int size, uint32_t data); 64 virtual void ReadConfig(int offset, int size, uint8_t *data); 65 66 67 virtual void serialize(std::ostream &os); 68 virtual void unserialize(Checkpoint *cp, const std::string §ion); 69}; 70 71#endif // __PCI_DEV_HH__ 72