device.hh revision 4762
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 * Andrew Schultz 30 * Nathan Binkert 31 */ 32 33/* @file 34 * Interface for devices using PCI configuration 35 */ 36 37#ifndef __DEV_PCIDEV_HH__ 38#define __DEV_PCIDEV_HH__ 39 40#include <cstring> 41 42#include "dev/io_device.hh" 43#include "dev/pcireg.h" 44#include "dev/platform.hh" 45#include "params/PciDevice.hh" 46#include "sim/byteswap.hh" 47 48#define BAR_IO_MASK 0x3 49#define BAR_MEM_MASK 0xF 50#define BAR_IO_SPACE_BIT 0x1 51#define BAR_IO_SPACE(x) ((x) & BAR_IO_SPACE_BIT) 52#define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2); 53 54 55/** 56 * This class encapulates the first 64 bytes of a singles PCI 57 * devices config space that in configured by the configuration file. 58 */ 59class PciConfigData : public SimObject 60{ 61 public: 62 /** 63 * Constructor to initialize the devices config space to 0. 64 */ 65 PciConfigData(const std::string &name) 66 : SimObject(name) 67 { 68 std::memset(config.data, 0, sizeof(config.data)); 69 std::memset(BARSize, 0, sizeof(BARSize)); 70 } 71 72 /** The first 64 bytes */ 73 PCIConfig config; 74 75 /** The size of the BARs */ 76 uint32_t BARSize[6]; 77}; 78 79 80/** 81 * PCI device, base implementation is only config space. 82 */ 83class PciDev : public DmaDevice 84{ 85 class PciConfigPort : public SimpleTimingPort 86 { 87 protected: 88 PciDev *device; 89 90 virtual Tick recvAtomic(PacketPtr pkt); 91 92 virtual void getDeviceAddressRanges(AddrRangeList &resp, 93 bool &snoop); 94 95 Platform *platform; 96 97 int busId; 98 int deviceId; 99 int functionId; 100 101 Addr configAddr; 102 103 public: 104 PciConfigPort(PciDev *dev, int busid, int devid, int funcid, 105 Platform *p); 106 }; 107 108 public: 109 typedef PciDeviceParams Params; 110 const Params * 111 params() const 112 { 113 return dynamic_cast<const Params *>(_params); 114 } 115 116 protected: 117 /** The current config space. Unlike the PciConfigData this is 118 * updated during simulation while continues to reflect what was 119 * in the config file. 120 */ 121 PCIConfig config; 122 123 /** The size of the BARs */ 124 uint32_t BARSize[6]; 125 126 /** The current address mapping of the BARs */ 127 Addr BARAddrs[6]; 128 129 /** 130 * Does the given address lie within the space mapped by the given 131 * base address register? 132 */ 133 bool 134 isBAR(Addr addr, int bar) const 135 { 136 assert(bar >= 0 && bar < 6); 137 return BARAddrs[bar] <= addr && addr < BARAddrs[bar] + BARSize[bar]; 138 } 139 140 /** 141 * Which base address register (if any) maps the given address? 142 * @return The BAR number (0-5 inclusive), or -1 if none. 143 */ 144 int 145 getBAR(Addr addr) 146 { 147 for (int i = 0; i <= 5; ++i) 148 if (isBAR(addr, i)) 149 return i; 150 151 return -1; 152 } 153 154 /** 155 * Which base address register (if any) maps the given address? 156 * @param addr The address to check. 157 * @retval bar The BAR number (0-5 inclusive), 158 * only valid if return value is true. 159 * @retval offs The offset from the base address, 160 * only valid if return value is true. 161 * @return True iff address maps to a base address register's region. 162 */ 163 bool 164 getBAR(Addr addr, int &bar, Addr &offs) 165 { 166 int b = getBAR(addr); 167 if (b < 0) 168 return false; 169 170 offs = addr - BARAddrs[b]; 171 bar = b; 172 return true; 173 } 174 175 protected: 176 Platform *plat; 177 PciConfigData *configData; 178 Tick pioDelay; 179 Tick configDelay; 180 PciConfigPort *configPort; 181 182 /** 183 * Write to the PCI config space data that is stored locally. This may be 184 * overridden by the device but at some point it will eventually call this 185 * for normal operations that it does not need to override. 186 * @param pkt packet containing the write the offset into config space 187 */ 188 virtual Tick writeConfig(PacketPtr pkt); 189 190 191 /** 192 * Read from the PCI config space data that is stored locally. This may be 193 * overridden by the device but at some point it will eventually call this 194 * for normal operations that it does not need to override. 195 * @param pkt packet containing the write the offset into config space 196 */ 197 virtual Tick readConfig(PacketPtr pkt); 198 199 public: 200 Addr pciToDma(Addr pciAddr) const 201 { return plat->pciToDma(pciAddr); } 202 203 void 204 intrPost() 205 { plat->postPciInt(letoh(configData->config.interruptLine)); } 206 207 void 208 intrClear() 209 { plat->clearPciInt(letoh(configData->config.interruptLine)); } 210 211 uint8_t 212 interruptLine() 213 { return letoh(configData->config.interruptLine); } 214 215 /** return the address ranges that this device responds to. 216 * @params range_list range list to populate with ranges 217 */ 218 void addressRanges(AddrRangeList &range_list); 219 220 /** 221 * Constructor for PCI Dev. This function copies data from the 222 * config file object PCIConfigData and registers the device with 223 * a PciConfigAll object. 224 */ 225 PciDev(Params *params); 226 227 virtual void init(); 228 229 /** 230 * Serialize this object to the given output stream. 231 * @param os The stream to serialize to. 232 */ 233 virtual void serialize(std::ostream &os); 234 235 /** 236 * Reconstruct the state of this object from a checkpoint. 237 * @param cp The checkpoint use. 238 * @param section The section name of this object 239 */ 240 virtual void unserialize(Checkpoint *cp, const std::string §ion); 241 242 243 virtual unsigned int drain(Event *de); 244 245 virtual Port *getPort(const std::string &if_name, int idx = -1) 246 { 247 if (if_name == "config") { 248 if (configPort != NULL) 249 panic("pciconfig port already connected to."); 250 configPort = new PciConfigPort(this, params()->pci_bus, 251 params()->pci_dev, params()->pci_func, 252 params()->platform); 253 return configPort; 254 } 255 return DmaDevice::getPort(if_name, idx); 256 } 257 258}; 259#endif // __DEV_PCIDEV_HH__ 260