device.hh revision 3349
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 * Andrew Schultz 30 * Nathan Binkert 31 */ 32 33/* @file 34 * Interface for devices using PCI configuration 35 */ 36 37#ifndef __DEV_PCIDEV_HH__ 38#define __DEV_PCIDEV_HH__ 39 40#include "dev/io_device.hh" 41#include "dev/pcireg.h" 42#include "dev/platform.hh" 43#include "sim/byteswap.hh" 44 45#define BAR_IO_MASK 0x3 46#define BAR_MEM_MASK 0xF 47#define BAR_IO_SPACE_BIT 0x1 48#define BAR_IO_SPACE(x) ((x) & BAR_IO_SPACE_BIT) 49#define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2); 50 51 52/** 53 * This class encapulates the first 64 bytes of a singles PCI 54 * devices config space that in configured by the configuration file. 55 */ 56class PciConfigData : public SimObject 57{ 58 public: 59 /** 60 * Constructor to initialize the devices config space to 0. 61 */ 62 PciConfigData(const std::string &name) 63 : SimObject(name) 64 { 65 memset(config.data, 0, sizeof(config.data)); 66 memset(BARSize, 0, sizeof(BARSize)); 67 } 68 69 /** The first 64 bytes */ 70 PCIConfig config; 71 72 /** The size of the BARs */ 73 uint32_t BARSize[6]; 74}; 75 76 77/** 78 * PCI device, base implementation is only config space. 79 */ 80class PciDev : public DmaDevice 81{ 82 class PciConfigPort : public SimpleTimingPort 83 { 84 protected: 85 PciDev *device; 86 87 virtual Tick recvAtomic(PacketPtr pkt); 88 89 virtual void getDeviceAddressRanges(AddrRangeList &resp, 90 AddrRangeList &snoop); 91 92 Platform *platform; 93 94 int busId; 95 int deviceId; 96 int functionId; 97 98 Addr configAddr; 99 100 public: 101 PciConfigPort(PciDev *dev, int busid, int devid, int funcid, 102 Platform *p); 103 }; 104 105 public: 106 struct Params : public PioDevice::Params 107 { 108 /** 109 * A pointer to the object that contains the first 64 bytes of 110 * config space 111 */ 112 PciConfigData *configData; 113 114 /** The bus number we are on */ 115 uint32_t busNum; 116 117 /** The device number we have */ 118 uint32_t deviceNum; 119 120 /** The function number */ 121 uint32_t functionNum; 122 123 /** The latency for pio accesses. */ 124 Tick pio_delay; 125 126 /** The latency for a config access. */ 127 Tick config_delay; 128 }; 129 130 public: 131 const Params *params() const { return (const Params *)_params; } 132 133 protected: 134 /** The current config space. Unlike the PciConfigData this is 135 * updated during simulation while continues to reflect what was 136 * in the config file. 137 */ 138 PCIConfig config; 139 140 /** The size of the BARs */ 141 uint32_t BARSize[6]; 142 143 /** The current address mapping of the BARs */ 144 Addr BARAddrs[6]; 145 146 /** 147 * Does the given address lie within the space mapped by the given 148 * base address register? 149 */ 150 bool 151 isBAR(Addr addr, int bar) const 152 { 153 assert(bar >= 0 && bar < 6); 154 return BARAddrs[bar] <= addr && addr < BARAddrs[bar] + BARSize[bar]; 155 } 156 157 /** 158 * Which base address register (if any) maps the given address? 159 * @return The BAR number (0-5 inclusive), or -1 if none. 160 */ 161 int 162 getBAR(Addr addr) 163 { 164 for (int i = 0; i <= 5; ++i) 165 if (isBAR(addr, i)) 166 return i; 167 168 return -1; 169 } 170 171 /** 172 * Which base address register (if any) maps the given address? 173 * @param addr The address to check. 174 * @retval bar The BAR number (0-5 inclusive), 175 * only valid if return value is true. 176 * @retval offs The offset from the base address, 177 * only valid if return value is true. 178 * @return True iff address maps to a base address register's region. 179 */ 180 bool 181 getBAR(Addr addr, int &bar, Addr &offs) 182 { 183 int b = getBAR(addr); 184 if (b < 0) 185 return false; 186 187 offs = addr - BARAddrs[b]; 188 bar = b; 189 return true; 190 } 191 192 protected: 193 Platform *plat; 194 PciConfigData *configData; 195 Tick pioDelay; 196 Tick configDelay; 197 PciConfigPort *configPort; 198 199 /** 200 * Write to the PCI config space data that is stored locally. This may be 201 * overridden by the device but at some point it will eventually call this 202 * for normal operations that it does not need to override. 203 * @param pkt packet containing the write the offset into config space 204 */ 205 virtual Tick writeConfig(PacketPtr pkt); 206 207 208 /** 209 * Read from the PCI config space data that is stored locally. This may be 210 * overridden by the device but at some point it will eventually call this 211 * for normal operations that it does not need to override. 212 * @param pkt packet containing the write the offset into config space 213 */ 214 virtual Tick readConfig(PacketPtr pkt); 215 216 public: 217 Addr pciToDma(Addr pciAddr) const 218 { return plat->pciToDma(pciAddr); } 219 220 void 221 intrPost() 222 { plat->postPciInt(letoh(configData->config.interruptLine)); } 223 224 void 225 intrClear() 226 { plat->clearPciInt(letoh(configData->config.interruptLine)); } 227 228 uint8_t 229 interruptLine() 230 { return letoh(configData->config.interruptLine); } 231 232 /** return the address ranges that this device responds to. 233 * @params range_list range list to populate with ranges 234 */ 235 void addressRanges(AddrRangeList &range_list); 236 237 /** 238 * Constructor for PCI Dev. This function copies data from the 239 * config file object PCIConfigData and registers the device with 240 * a PciConfigAll object. 241 */ 242 PciDev(Params *params); 243 244 virtual void init(); 245 246 /** 247 * Serialize this object to the given output stream. 248 * @param os The stream to serialize to. 249 */ 250 virtual void serialize(std::ostream &os); 251 252 /** 253 * Reconstruct the state of this object from a checkpoint. 254 * @param cp The checkpoint use. 255 * @param section The section name of this object 256 */ 257 virtual void unserialize(Checkpoint *cp, const std::string §ion); 258 259 260 virtual unsigned int drain(Event *de); 261 262 virtual Port *getPort(const std::string &if_name, int idx = -1) 263 { 264 if (if_name == "config") { 265 if (configPort != NULL) 266 panic("pciconfig port already connected to."); 267 configPort = new PciConfigPort(this, params()->busNum, 268 params()->deviceNum, params()->functionNum, 269 params()->platform); 270 return configPort; 271 } 272 return DmaDevice::getPort(if_name, idx); 273 } 274 275}; 276#endif // __DEV_PCIDEV_HH__ 277