device.hh revision 11260
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2013 ARM Limited 37338SAli.Saidi@ARM.com * All rights reserved 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137338SAli.Saidi@ARM.com * 141762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 412SN/A * Andrew Schultz 422SN/A * Nathan Binkert 438779Sgblack@eecs.umich.edu */ 448779Sgblack@eecs.umich.edu 458779Sgblack@eecs.umich.edu/* @file 462439SN/A * Interface for devices using PCI configuration 478779Sgblack@eecs.umich.edu */ 488229Snate@binkert.org 496216Snate@binkert.org#ifndef __DEV_PCI_DEVICE_HH__ 50146SN/A#define __DEV_PCI_DEVICE_HH__ 51146SN/A 52146SN/A#include <cstring> 53146SN/A#include <vector> 54146SN/A 55146SN/A#include "dev/dma_device.hh" 566216Snate@binkert.org#include "dev/pci/host.hh" 576658Snate@binkert.org#include "dev/pci/pcireg.h" 588229Snate@binkert.org#include "params/PciDevice.hh" 591717SN/A#include "sim/byteswap.hh" 608887Sgeoffrey.blake@arm.com 618887Sgeoffrey.blake@arm.com#define BAR_IO_MASK 0x3 62146SN/A#define BAR_MEM_MASK 0xF 631977SN/A#define BAR_IO_SPACE_BIT 0x1 642683Sktlim@umich.edu#define BAR_IO_SPACE(x) ((x) & BAR_IO_SPACE_BIT) 651717SN/A#define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2); 66146SN/A 672683Sktlim@umich.edu/** 688232Snate@binkert.org * PCI device, base implementation is only config space. 698232Snate@binkert.org */ 708232Snate@binkert.orgclass PciDevice : public DmaDevice 718779Sgblack@eecs.umich.edu{ 723348Sbinkertn@umich.edu protected: 736105Ssteve.reinhardt@amd.com const PciBusAddr _busAddr; 746216Snate@binkert.org 752036SN/A /** The current config space. */ 76146SN/A PCIConfig config; 778817Sgblack@eecs.umich.edu 788793Sgblack@eecs.umich.edu /** The capability list structures and base addresses 7956SN/A * @{ 8056SN/A */ 81695SN/A const int PMCAP_BASE; 822901Ssaidi@eecs.umich.edu const int PMCAP_ID_OFFSET; 832SN/A const int PMCAP_PC_OFFSET; 842SN/A const int PMCAP_PMCS_OFFSET; 852449SN/A PMCAP pmcap; 861355SN/A 875529Snate@binkert.org const int MSICAP_BASE; 884495Sacolyte@umich.edu MSICAP msicap; 89224SN/A 908793Sgblack@eecs.umich.edu const int MSIXCAP_BASE; 918793Sgblack@eecs.umich.edu const int MSIXCAP_ID_OFFSET; 928793Sgblack@eecs.umich.edu const int MSIXCAP_MXC_OFFSET; 938820Sgblack@eecs.umich.edu const int MSIXCAP_MTAB_OFFSET; 948820Sgblack@eecs.umich.edu const int MSIXCAP_MPBA_OFFSET; 952SN/A int MSIX_TABLE_OFFSET; 966029Ssteve.reinhardt@amd.com int MSIX_TABLE_END; 972672Sktlim@umich.edu int MSIX_PBA_OFFSET; 982683Sktlim@umich.edu int MSIX_PBA_END; 992SN/A MSIXCAP msixcap; 1008733Sgeoffrey.blake@arm.com 1018733Sgeoffrey.blake@arm.com const int PXCAP_BASE; 1028733Sgeoffrey.blake@arm.com PXCAP pxcap; 1038733Sgeoffrey.blake@arm.com /** @} */ 1048733Sgeoffrey.blake@arm.com 1058733Sgeoffrey.blake@arm.com /** MSIX Table and PBA Structures */ 1068733Sgeoffrey.blake@arm.com std::vector<MSIXTable> msix_table; 1078733Sgeoffrey.blake@arm.com std::vector<MSIXPbaEntry> msix_pba; 1088733Sgeoffrey.blake@arm.com 1098733Sgeoffrey.blake@arm.com /** The size of the BARs */ 1108733Sgeoffrey.blake@arm.com uint32_t BARSize[6]; 1112SN/A 112334SN/A /** The current address mapping of the BARs */ 1138834Satgutier@umich.edu Addr BARAddrs[6]; 1148834Satgutier@umich.edu 115140SN/A /** Whether the BARs are really hardwired legacy IO locations. */ 116334SN/A bool legacyIO[6]; 1172SN/A 1182SN/A /** 1192SN/A * Does the given address lie within the space mapped by the given 1202680Sktlim@umich.edu * base address register? 1214377Sgblack@eecs.umich.edu */ 1225169Ssaidi@eecs.umich.edu bool 1234377Sgblack@eecs.umich.edu isBAR(Addr addr, int bar) const 1244377Sgblack@eecs.umich.edu { 1252SN/A assert(bar >= 0 && bar < 6); 1262SN/A return BARAddrs[bar] <= addr && addr < BARAddrs[bar] + BARSize[bar]; 1272623SN/A } 1282SN/A 1292SN/A /** 1302SN/A * Which base address register (if any) maps the given address? 131180SN/A * @return The BAR number (0-5 inclusive), or -1 if none. 1328737Skoansin.tan@gmail.com */ 133393SN/A int 134393SN/A getBAR(Addr addr) 135393SN/A { 136393SN/A for (int i = 0; i <= 5; ++i) 137384SN/A if (isBAR(addr, i)) 138384SN/A return i; 139393SN/A 1408737Skoansin.tan@gmail.com return -1; 141393SN/A } 142393SN/A 143393SN/A /** 144393SN/A * Which base address register (if any) maps the given address? 145384SN/A * @param addr The address to check. 146189SN/A * @retval bar The BAR number (0-5 inclusive), 147189SN/A * only valid if return value is true. 1482623SN/A * @retval offs The offset from the base address, 1492SN/A * only valid if return value is true. 150729SN/A * @return True iff address maps to a base address register's region. 151334SN/A */ 1522SN/A bool 1532SN/A getBAR(Addr addr, int &bar, Addr &offs) 1542SN/A { 1558834Satgutier@umich.edu int b = getBAR(addr); 1568834Satgutier@umich.edu if (b < 0) 1578834Satgutier@umich.edu return false; 1588834Satgutier@umich.edu 1598834Satgutier@umich.edu offs = addr - BARAddrs[b]; 1608834Satgutier@umich.edu bar = b; 1618834Satgutier@umich.edu return true; 1622SN/A } 1632SN/A 1647897Shestness@cs.utexas.edu public: // Host configuration interface 1657897Shestness@cs.utexas.edu /** 1667897Shestness@cs.utexas.edu * Write to the PCI config space data that is stored locally. This may be 1677897Shestness@cs.utexas.edu * overridden by the device but at some point it will eventually call this 1687897Shestness@cs.utexas.edu * for normal operations that it does not need to override. 1697897Shestness@cs.utexas.edu * @param pkt packet containing the write the offset into config space 1707897Shestness@cs.utexas.edu */ 1717897Shestness@cs.utexas.edu virtual Tick writeConfig(PacketPtr pkt); 1727897Shestness@cs.utexas.edu 1737897Shestness@cs.utexas.edu 1747897Shestness@cs.utexas.edu /** 1757897Shestness@cs.utexas.edu * Read from the PCI config space data that is stored locally. This may be 1767897Shestness@cs.utexas.edu * overridden by the device but at some point it will eventually call this 1777897Shestness@cs.utexas.edu * for normal operations that it does not need to override. 1787897Shestness@cs.utexas.edu * @param pkt packet containing the write the offset into config space 1797897Shestness@cs.utexas.edu */ 1807897Shestness@cs.utexas.edu virtual Tick readConfig(PacketPtr pkt); 1817897Shestness@cs.utexas.edu 1827897Shestness@cs.utexas.edu protected: 1837897Shestness@cs.utexas.edu PciHost::DeviceInterface hostInterface; 1847897Shestness@cs.utexas.edu 1857897Shestness@cs.utexas.edu Tick pioDelay; 1867897Shestness@cs.utexas.edu Tick configDelay; 1877897Shestness@cs.utexas.edu 1887897Shestness@cs.utexas.edu public: 1897897Shestness@cs.utexas.edu Addr pciToDma(Addr pci_addr) const { 1907897Shestness@cs.utexas.edu return hostInterface.dmaAddr(pci_addr); 1917897Shestness@cs.utexas.edu } 1927897Shestness@cs.utexas.edu 1937897Shestness@cs.utexas.edu void intrPost() { hostInterface.postInt(); } 1947897Shestness@cs.utexas.edu void intrClear() { hostInterface.clearInt(); } 1957897Shestness@cs.utexas.edu 1967897Shestness@cs.utexas.edu uint8_t interruptLine() const { return letoh(config.interruptLine); } 1977897Shestness@cs.utexas.edu 1987897Shestness@cs.utexas.edu /** 1997897Shestness@cs.utexas.edu * Determine the address ranges that this device responds to. 2007897Shestness@cs.utexas.edu * 2017897Shestness@cs.utexas.edu * @return a list of non-overlapping address ranges 2027897Shestness@cs.utexas.edu */ 2037897Shestness@cs.utexas.edu AddrRangeList getAddrRanges() const override; 2047897Shestness@cs.utexas.edu 2057897Shestness@cs.utexas.edu /** 2067897Shestness@cs.utexas.edu * Constructor for PCI Dev. This function copies data from the 2077897Shestness@cs.utexas.edu * config file object PCIConfigData and registers the device with 2087897Shestness@cs.utexas.edu * a PciHost object. 2097897Shestness@cs.utexas.edu */ 2107897Shestness@cs.utexas.edu PciDevice(const PciDeviceParams *params); 2117897Shestness@cs.utexas.edu 2127897Shestness@cs.utexas.edu /** 2137897Shestness@cs.utexas.edu * Serialize this object to the given output stream. 2142SN/A * @param os The stream to serialize to. 2157897Shestness@cs.utexas.edu */ 2167897Shestness@cs.utexas.edu void serialize(CheckpointOut &cp) const override; 2177897Shestness@cs.utexas.edu 2187897Shestness@cs.utexas.edu /** 2197897Shestness@cs.utexas.edu * Reconstruct the state of this object from a checkpoint. 2207897Shestness@cs.utexas.edu * @param cp The checkpoint use. 2217897Shestness@cs.utexas.edu * @param section The section name of this object 2227897Shestness@cs.utexas.edu */ 2237897Shestness@cs.utexas.edu void unserialize(CheckpointIn &cp) override; 2247897Shestness@cs.utexas.edu 2257897Shestness@cs.utexas.edu const PciBusAddr &busAddr() const { return _busAddr; } 2267897Shestness@cs.utexas.edu}; 2272SN/A#endif // __DEV_PCI_DEVICE_HH__ 2282SN/A