copy_engine.hh revision 12087:0e082672ac6b
110234Syasuko.eckert@amd.com/* 210234Syasuko.eckert@amd.com * Copyright (c) 2012 ARM Limited 310234Syasuko.eckert@amd.com * All rights reserved 410234Syasuko.eckert@amd.com * 510234Syasuko.eckert@amd.com * The license below extends only to copyright in the software and shall 610234Syasuko.eckert@amd.com * not be construed as granting a license to any other intellectual 710234Syasuko.eckert@amd.com * property including but not limited to intellectual property relating 810234Syasuko.eckert@amd.com * to a hardware implementation of the functionality of the software 910234Syasuko.eckert@amd.com * licensed hereunder. You may use the software subject to the license 1010234Syasuko.eckert@amd.com * terms below provided that you ensure that this notice is replicated 1110234Syasuko.eckert@amd.com * unmodified and in its entirety in all distributions of the software, 1210234Syasuko.eckert@amd.com * modified or unmodified, in source code or in binary form. 1310234Syasuko.eckert@amd.com * 1410234Syasuko.eckert@amd.com * Copyright (c) 2008 The Regents of The University of Michigan 1510234Syasuko.eckert@amd.com * All rights reserved. 1610234Syasuko.eckert@amd.com * 1710234Syasuko.eckert@amd.com * Redistribution and use in source and binary forms, with or without 1810234Syasuko.eckert@amd.com * modification, are permitted provided that the following conditions are 1910234Syasuko.eckert@amd.com * met: redistributions of source code must retain the above copyright 2010234Syasuko.eckert@amd.com * notice, this list of conditions and the following disclaimer; 2110234Syasuko.eckert@amd.com * redistributions in binary form must reproduce the above copyright 2210234Syasuko.eckert@amd.com * notice, this list of conditions and the following disclaimer in the 2310234Syasuko.eckert@amd.com * documentation and/or other materials provided with the distribution; 2410234Syasuko.eckert@amd.com * neither the name of the copyright holders nor the names of its 2510234Syasuko.eckert@amd.com * contributors may be used to endorse or promote products derived from 2610234Syasuko.eckert@amd.com * this software without specific prior written permission. 2710234Syasuko.eckert@amd.com * 2810234Syasuko.eckert@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2910234Syasuko.eckert@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3010234Syasuko.eckert@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3110234Syasuko.eckert@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3210234Syasuko.eckert@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3310234Syasuko.eckert@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3410234Syasuko.eckert@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3510234Syasuko.eckert@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3610234Syasuko.eckert@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3710234Syasuko.eckert@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3810234Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3910234Syasuko.eckert@amd.com * 4010234Syasuko.eckert@amd.com * Authors: Ali Saidi 4110234Syasuko.eckert@amd.com */ 4210234Syasuko.eckert@amd.com 4310234Syasuko.eckert@amd.com/* @file 4410234Syasuko.eckert@amd.com * Device model for Intel's I/O Acceleration Technology (I/OAT). 4510234Syasuko.eckert@amd.com * A DMA asyncronous copy engine 4610234Syasuko.eckert@amd.com */ 4710234Syasuko.eckert@amd.com 4810234Syasuko.eckert@amd.com#ifndef __DEV_PCI_COPY_ENGINE_HH__ 4910234Syasuko.eckert@amd.com#define __DEV_PCI_COPY_ENGINE_HH__ 5010234Syasuko.eckert@amd.com 5110234Syasuko.eckert@amd.com#include <vector> 5210234Syasuko.eckert@amd.com 5310234Syasuko.eckert@amd.com#include "base/cp_annotate.hh" 5410234Syasuko.eckert@amd.com#include "base/statistics.hh" 5510234Syasuko.eckert@amd.com#include "dev/pci/copy_engine_defs.hh" 5610234Syasuko.eckert@amd.com#include "dev/pci/device.hh" 5710234Syasuko.eckert@amd.com#include "params/CopyEngine.hh" 5810234Syasuko.eckert@amd.com#include "sim/drain.hh" 5910234Syasuko.eckert@amd.com#include "sim/eventq.hh" 6010234Syasuko.eckert@amd.com 6110234Syasuko.eckert@amd.comclass CopyEngine : public PciDevice 6210234Syasuko.eckert@amd.com{ 6310234Syasuko.eckert@amd.com class CopyEngineChannel : public Drainable, public Serializable 6410234Syasuko.eckert@amd.com { 6510234Syasuko.eckert@amd.com private: 6610234Syasuko.eckert@amd.com DmaPort cePort; 6710234Syasuko.eckert@amd.com CopyEngine *ce; 6810234Syasuko.eckert@amd.com CopyEngineReg::ChanRegs cr; 6910234Syasuko.eckert@amd.com int channelId; 7010234Syasuko.eckert@amd.com CopyEngineReg::DmaDesc *curDmaDesc; 7110234Syasuko.eckert@amd.com uint8_t *copyBuffer; 72 73 bool busy; 74 bool underReset; 75 bool refreshNext; 76 Addr lastDescriptorAddr; 77 Addr fetchAddress; 78 79 Tick latBeforeBegin; 80 Tick latAfterCompletion; 81 82 uint64_t completionDataReg; 83 84 enum ChannelState { 85 Idle, 86 AddressFetch, 87 DescriptorFetch, 88 DMARead, 89 DMAWrite, 90 CompletionWrite 91 }; 92 93 ChannelState nextState; 94 95 public: 96 CopyEngineChannel(CopyEngine *_ce, int cid); 97 virtual ~CopyEngineChannel(); 98 BaseMasterPort &getMasterPort(); 99 100 std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); } 101 virtual Tick read(PacketPtr pkt) 102 { panic("CopyEngineChannel has no I/O access\n");} 103 virtual Tick write(PacketPtr pkt) 104 { panic("CopyEngineChannel has no I/O access\n"); } 105 106 void channelRead(PacketPtr pkt, Addr daddr, int size); 107 void channelWrite(PacketPtr pkt, Addr daddr, int size); 108 109 DrainState drain() override; 110 void drainResume() override; 111 112 void serialize(CheckpointOut &cp) const override; 113 void unserialize(CheckpointIn &cp) override; 114 115 private: 116 void fetchDescriptor(Addr address); 117 void fetchDescComplete(); 118 EventFunctionWrapper fetchCompleteEvent; 119 120 void fetchNextAddr(Addr address); 121 void fetchAddrComplete(); 122 EventFunctionWrapper addrCompleteEvent; 123 124 void readCopyBytes(); 125 void readCopyBytesComplete(); 126 EventFunctionWrapper readCompleteEvent; 127 128 void writeCopyBytes(); 129 void writeCopyBytesComplete(); 130 EventFunctionWrapper writeCompleteEvent; 131 132 void writeCompletionStatus(); 133 void writeStatusComplete(); 134 EventFunctionWrapper statusCompleteEvent; 135 136 137 void continueProcessing(); 138 void recvCommand(); 139 bool inDrain(); 140 void restartStateMachine(); 141 inline void anBegin(const char *s) 142 { 143 CPA::cpa()->hwBegin(CPA::FL_NONE, ce->sys, 144 channelId, "CopyEngine", s); 145 } 146 147 inline void anWait() 148 { 149 CPA::cpa()->hwWe(CPA::FL_NONE, ce->sys, 150 channelId, "CopyEngine", "DMAUnusedDescQ", channelId); 151 } 152 153 inline void anDq() 154 { 155 CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys, 156 channelId, "CopyEngine", "DMAUnusedDescQ", channelId); 157 } 158 159 inline void anPq() 160 { 161 CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys, 162 channelId, "CopyEngine", "DMAUnusedDescQ", channelId); 163 } 164 165 inline void anQ(const char * s, uint64_t id, int size = 1) 166 { 167 CPA::cpa()->hwQ(CPA::FL_NONE, ce->sys, channelId, 168 "CopyEngine", s, id, NULL, size); 169 } 170 171 }; 172 173 private: 174 175 Stats::Vector bytesCopied; 176 Stats::Vector copiesProcessed; 177 178 // device registers 179 CopyEngineReg::Regs regs; 180 181 // Array of channels each one with regs/dma port/etc 182 std::vector<CopyEngineChannel*> chan; 183 184 public: 185 typedef CopyEngineParams Params; 186 const Params * 187 params() const 188 { 189 return dynamic_cast<const Params *>(_params); 190 } 191 CopyEngine(const Params *params); 192 ~CopyEngine(); 193 194 void regStats() override; 195 196 BaseMasterPort &getMasterPort(const std::string &if_name, 197 PortID idx = InvalidPortID) override; 198 199 Tick read(PacketPtr pkt) override; 200 Tick write(PacketPtr pkt) override; 201 202 void serialize(CheckpointOut &cp) const override; 203 void unserialize(CheckpointIn &cp) override; 204}; 205 206#endif //__DEV_PCI_COPY_ENGINE_HH__ 207 208