PciDevice.py revision 11260
19957SN/A# Copyright (c) 2013 ARM Limited 29957SN/A# All rights reserved 39957SN/A# 49957SN/A# The license below extends only to copyright in the software and shall 59957SN/A# not be construed as granting a license to any other intellectual 69957SN/A# property including but not limited to intellectual property relating 79957SN/A# to a hardware implementation of the functionality of the software 89957SN/A# licensed hereunder. You may use the software subject to the license 99957SN/A# terms below provided that you ensure that this notice is replicated 109957SN/A# unmodified and in its entirety in all distributions of the software, 119957SN/A# modified or unmodified, in source code or in binary form. 129957SN/A# 134486SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 394486SN/A# Authors: Nathan Binkert 404486SN/A 413102SN/Afrom m5.SimObject import SimObject 423102SN/Afrom m5.params import * 433102SN/Afrom m5.proxy import * 4411244SN/Afrom Device import DmaDevice 4511244SN/Afrom PciHost import PciHost 464982SN/A 474982SN/Aclass PciDevice(DmaDevice): 484982SN/A type = 'PciDevice' 499807SN/A cxx_class = 'PciDevice' 5011260Sandreas.sandberg@arm.com cxx_header = "dev/pci/device.hh" 514982SN/A abstract = True 5211244SN/A 5311244SN/A host = Param.PciHost(Parent.any, "PCI host") 544982SN/A pci_bus = Param.Int("PCI bus") 554982SN/A pci_dev = Param.Int("PCI device number") 564982SN/A pci_func = Param.Int("PCI function code") 5711244SN/A 589198SN/A pio_latency = Param.Latency('30ns', "Programmed IO latency") 594982SN/A config_latency = Param.Latency('20ns', "Config read or write latency") 604982SN/A 611310SN/A VendorID = Param.UInt16("Vendor ID") 621310SN/A DeviceID = Param.UInt16("Device ID") 631310SN/A Command = Param.UInt16(0, "Command") 641310SN/A Status = Param.UInt16(0, "Status") 651310SN/A Revision = Param.UInt8(0, "Device") 661310SN/A ProgIF = Param.UInt8(0, "Programming Interface") 671310SN/A SubClassCode = Param.UInt8(0, "Sub-Class Code") 681310SN/A ClassCode = Param.UInt8(0, "Class Code") 691310SN/A CacheLineSize = Param.UInt8(0, "System Cacheline Size") 701310SN/A LatencyTimer = Param.UInt8(0, "PCI Latency Timer") 711310SN/A HeaderType = Param.UInt8(0, "PCI Header Type") 721310SN/A BIST = Param.UInt8(0, "Built In Self Test") 731310SN/A 741310SN/A BAR0 = Param.UInt32(0x00, "Base Address Register 0") 751310SN/A BAR1 = Param.UInt32(0x00, "Base Address Register 1") 761310SN/A BAR2 = Param.UInt32(0x00, "Base Address Register 2") 771310SN/A BAR3 = Param.UInt32(0x00, "Base Address Register 3") 781310SN/A BAR4 = Param.UInt32(0x00, "Base Address Register 4") 791310SN/A BAR5 = Param.UInt32(0x00, "Base Address Register 5") 801990SN/A BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size") 811990SN/A BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size") 821990SN/A BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size") 831990SN/A BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size") 841990SN/A BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size") 851990SN/A BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size") 865834SN/A BAR0LegacyIO = Param.Bool(False, "Whether BAR0 is hardwired legacy IO") 875834SN/A BAR1LegacyIO = Param.Bool(False, "Whether BAR1 is hardwired legacy IO") 885834SN/A BAR2LegacyIO = Param.Bool(False, "Whether BAR2 is hardwired legacy IO") 895834SN/A BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO") 905834SN/A BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO") 915834SN/A BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO") 9210359SN/A LegacyIOBase = Param.Addr(0x0, "Base Address for Legacy IO") 931310SN/A 941310SN/A CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") 951310SN/A SubsystemID = Param.UInt16(0x00, "Subsystem ID") 961310SN/A SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID") 971310SN/A ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address") 989957SN/A CapabilityPtr = Param.UInt8(0x00, "Capability List Pointer offset") 991310SN/A InterruptLine = Param.UInt8(0x00, "Interrupt Line") 1001310SN/A InterruptPin = Param.UInt8(0x00, "Interrupt Pin") 1011310SN/A MaximumLatency = Param.UInt8(0x00, "Maximum Latency") 1021310SN/A MinimumGrant = Param.UInt8(0x00, "Minimum Grant") 1031310SN/A 1049957SN/A # Capabilities List structures for PCIe devices 1059957SN/A # PMCAP - PCI Power Management Capability 1069957SN/A PMCAPBaseOffset = \ 1079957SN/A Param.UInt8(0x00, "Base offset of PMCAP in PCI Config space") 1089957SN/A PMCAPNextCapability = \ 1099957SN/A Param.UInt8(0x00, "Pointer to next capability block") 1109957SN/A PMCAPCapId = \ 1119957SN/A Param.UInt8(0x00, "Specifies this is the Power Management capability") 1129957SN/A PMCAPCapabilities = \ 1139957SN/A Param.UInt16(0x0000, "PCI Power Management Capabilities Register") 1149957SN/A PMCAPCtrlStatus = \ 1159957SN/A Param.UInt16(0x0000, "PCI Power Management Control and Status") 1162846SN/A 1179957SN/A # MSICAP - Message Signaled Interrupt Capability 1189957SN/A MSICAPBaseOffset = \ 1199957SN/A Param.UInt8(0x00, "Base offset of MSICAP in PCI Config space") 1209957SN/A MSICAPNextCapability = \ 1219957SN/A Param.UInt8(0x00, "Pointer to next capability block") 1229957SN/A MSICAPCapId = Param.UInt8(0x00, "Specifies this is the MSI Capability") 1239957SN/A MSICAPMsgCtrl = Param.UInt16(0x0000, "MSI Message Control") 1249957SN/A MSICAPMsgAddr = Param.UInt32(0x00000000, "MSI Message Address") 1259957SN/A MSICAPMsgUpperAddr = Param.UInt32(0x00000000, "MSI Message Upper Address") 1269957SN/A MSICAPMsgData = Param.UInt16(0x0000, "MSI Message Data") 1279957SN/A MSICAPMaskBits = Param.UInt32(0x00000000, "MSI Interrupt Mask Bits") 1289957SN/A MSICAPPendingBits = Param.UInt32(0x00000000, "MSI Pending Bits") 1299957SN/A 1309957SN/A # MSIXCAP - MSI-X Capability 1319957SN/A MSIXCAPBaseOffset = \ 1329957SN/A Param.UInt8(0x00, "Base offset of MSIXCAP in PCI Config space") 1339957SN/A MSIXCAPNextCapability = \ 1349957SN/A Param.UInt8(0x00, "Pointer to next capability block") 1359957SN/A MSIXCAPCapId = Param.UInt8(0x00, "Specifices this the MSI-X Capability") 1369957SN/A MSIXMsgCtrl = Param.UInt16(0x0000, "MSI-X Message Control") 1379957SN/A MSIXTableOffset = \ 1389957SN/A Param.UInt32(0x00000000, "MSI-X Table Offset and Table BIR") 1399957SN/A MSIXPbaOffset = Param.UInt32(0x00000000, "MSI-X PBA Offset and PBA BIR") 1409957SN/A 1419957SN/A # PXCAP - PCI Express Capability 1429957SN/A PXCAPBaseOffset = \ 1439957SN/A Param.UInt8(0x00, "Base offset of PXCAP in PCI Config space") 1449957SN/A PXCAPNextCapability = Param.UInt8(0x00, "Pointer to next capability block") 1459957SN/A PXCAPCapId = Param.UInt8(0x00, "Specifies this is the PCIe Capability") 1469957SN/A PXCAPCapabilities = Param.UInt16(0x0000, "PCIe Capabilities") 1479957SN/A PXCAPDevCapabilities = Param.UInt32(0x00000000, "PCIe Device Capabilities") 1489957SN/A PXCAPDevCtrl = Param.UInt16(0x0000, "PCIe Device Control") 1499957SN/A PXCAPDevStatus = Param.UInt16(0x0000, "PCIe Device Status") 1509957SN/A PXCAPLinkCap = Param.UInt32(0x00000000, "PCIe Link Capabilities") 1519957SN/A PXCAPLinkCtrl = Param.UInt16(0x0000, "PCIe Link Control") 1529957SN/A PXCAPLinkStatus = Param.UInt16(0x0000, "PCIe Link Status") 1539957SN/A PXCAPDevCap2 = Param.UInt32(0x00000000, "PCIe Device Capabilities 2") 1549957SN/A PXCAPDevCtrl2 = Param.UInt32(0x00000000, "PCIe Device Control 2") 155