CopyEngine.py revision 8841 
110319SAndreas.Sandberg@ARM.com# Copyright (c) 2008 The Regents of The University of Michigan
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510319SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are
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710319SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer;
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1310319SAndreas.Sandberg@ARM.com# this software without specific prior written permission.
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2710319SAndreas.Sandberg@ARM.com# Authors: Ali Saidi
2810319SAndreas.Sandberg@ARM.com
2910319SAndreas.Sandberg@ARM.comfrom m5.SimObject import SimObject
3010319SAndreas.Sandberg@ARM.comfrom m5.params import *
3110319SAndreas.Sandberg@ARM.comfrom m5.proxy import *
3210319SAndreas.Sandberg@ARM.comfrom Pci import PciDevice
3310319SAndreas.Sandberg@ARM.com
3410319SAndreas.Sandberg@ARM.comclass CopyEngine(PciDevice):
3510319SAndreas.Sandberg@ARM.com    type = 'CopyEngine'
3610319SAndreas.Sandberg@ARM.com    dma = VectorMasterPort("Copy engine DMA port")
3710319SAndreas.Sandberg@ARM.com    VendorID = 0x8086
3810319SAndreas.Sandberg@ARM.com    DeviceID = 0x1a38
3910319SAndreas.Sandberg@ARM.com    Revision = 0xA2 # CM2 stepping (newest listed)
4010319SAndreas.Sandberg@ARM.com    SubsystemID = 0
41    SubsystemVendorID = 0
42    Status = 0x0000
43    SubClassCode = 0x08
44    ClassCode = 0x80
45    ProgIF = 0x00
46    MaximumLatency = 0x00
47    MinimumGrant = 0xff
48    InterruptLine = 0x20
49    InterruptPin = 0x01
50    BAR0Size = '1kB'
51
52    ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
53    XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that are supported")
54
55
56    clock = Param.Clock('500MHz', "Clock speed of the device")
57    latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is seen before it's proccessed")
58    latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is complete before it's reported as such")
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