sinic.hh revision 5603
12101SN/A/* 22084SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32754Sksewell@umich.edu * All rights reserved. 42754Sksewell@umich.edu * 52754Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62754Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72754Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82754Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92754Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102754Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112754Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122754Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132754Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142754Sksewell@umich.edu * this software without specific prior written permission. 152754Sksewell@umich.edu * 162754Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172754Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182754Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192754Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202754Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212754Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222754Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232754Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242754Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252754Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262754Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272754Sksewell@umich.edu * 282754Sksewell@umich.edu * Authors: Nathan Binkert 292754Sksewell@umich.edu */ 302754Sksewell@umich.edu 312084SN/A#ifndef __DEV_SINIC_HH__ 322084SN/A#define __DEV_SINIC_HH__ 332084SN/A 342084SN/A#include "base/inet.hh" 352084SN/A#include "base/statistics.hh" 362084SN/A#include "dev/etherint.hh" 372084SN/A#include "dev/etherpkt.hh" 382084SN/A#include "dev/io_device.hh" 392084SN/A#include "dev/pcidev.hh" 402101SN/A#include "dev/pktfifo.hh" 412084SN/A#include "dev/sinicreg.hh" 422084SN/A#include "params/Sinic.hh" 432084SN/A#include "sim/eventq.hh" 442084SN/A 452084SN/Anamespace Sinic { 462084SN/A 472084SN/Aclass Interface; 482101SN/Aclass Base : public PciDev 492084SN/A{ 502084SN/A protected: 512084SN/A bool rxEnable; 522084SN/A bool txEnable; 532084SN/A Tick clock; 542084SN/A inline Tick ticks(int numCycles) const { return numCycles * clock; } 552084SN/A 562084SN/A protected: 572084SN/A Tick intrDelay; 582084SN/A Tick intrTick; 592084SN/A bool cpuIntrEnable; 602084SN/A bool cpuPendingIntr; 612084SN/A void cpuIntrPost(Tick when); 622084SN/A void cpuInterrupt(); 632084SN/A void cpuIntrClear(); 642084SN/A 652084SN/A typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent; 662084SN/A friend void IntrEvent::process(); 672686Sksewell@umich.edu IntrEvent *intrEvent; 682084SN/A Interface *interface; 692084SN/A 702084SN/A bool cpuIntrPending() const; 712084SN/A void cpuIntrAck() { cpuIntrClear(); } 722084SN/A 732101SN/A/** 742101SN/A * Serialization stuff 752084SN/A */ 762750Sksewell@umich.edu public: 772750Sksewell@umich.edu virtual void serialize(std::ostream &os); 782084SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 792084SN/A 802084SN/A/** 812084SN/A * Construction/Destruction/Parameters 822084SN/A */ 832084SN/A public: 842084SN/A typedef SinicParams Params; 852084SN/A const Params *params() const { return (const Params *)_params; } 862084SN/A Base(const Params *p); 872239SN/A}; 882084SN/A 892084SN/Aclass Device : public Base 902084SN/A{ 912750Sksewell@umich.edu protected: 922750Sksewell@umich.edu /** Receive State Machine States */ 932750Sksewell@umich.edu enum RxState { 942750Sksewell@umich.edu rxIdle, 952750Sksewell@umich.edu rxFifoBlock, 962750Sksewell@umich.edu rxBeginCopy, 972750Sksewell@umich.edu rxCopy, 982750Sksewell@umich.edu rxCopyDone 992750Sksewell@umich.edu }; 1002750Sksewell@umich.edu 1012750Sksewell@umich.edu /** Transmit State Machine states */ 1022750Sksewell@umich.edu enum TxState { 1032084SN/A txIdle, 1042084SN/A txFifoBlock, 1052101SN/A txBeginCopy, 1062750Sksewell@umich.edu txCopy, 1072750Sksewell@umich.edu txCopyDone 1082750Sksewell@umich.edu }; 1092750Sksewell@umich.edu 1102750Sksewell@umich.edu /** device register file */ 1112750Sksewell@umich.edu struct { 1122239SN/A uint32_t Config; // 0x00 1132750Sksewell@umich.edu uint32_t Command; // 0x04 1142750Sksewell@umich.edu uint32_t IntrStatus; // 0x08 1152750Sksewell@umich.edu uint32_t IntrMask; // 0x0c 1162750Sksewell@umich.edu uint32_t RxMaxCopy; // 0x10 1172750Sksewell@umich.edu uint32_t TxMaxCopy; // 0x14 1182750Sksewell@umich.edu uint32_t ZeroCopySize; // 0x18 1192750Sksewell@umich.edu uint32_t ZeroCopyMark; // 0x1c 1202750Sksewell@umich.edu uint32_t VirtualCount; // 0x20 1212084SN/A uint32_t RxMaxIntr; // 0x24 1222084SN/A uint32_t RxFifoSize; // 0x28 1232084SN/A uint32_t TxFifoSize; // 0x2c 1242084SN/A uint32_t RxFifoLow; // 0x30 1252084SN/A uint32_t TxFifoLow; // 0x34 1262084SN/A uint32_t RxFifoHigh; // 0x38 1272084SN/A uint32_t TxFifoHigh; // 0x3c 1283951Sgblack@eecs.umich.edu uint64_t RxData; // 0x40 1292084SN/A uint64_t RxDone; // 0x48 1302084SN/A uint64_t RxWait; // 0x50 1312084SN/A uint64_t TxData; // 0x58 1322084SN/A uint64_t TxDone; // 0x60 1332084SN/A uint64_t TxWait; // 0x68 1342084SN/A uint64_t HwAddr; // 0x70 1352084SN/A uint64_t RxStatus; // 0x78 1362470SN/A } regs; 1372686Sksewell@umich.edu 1382470SN/A struct VirtualReg { 1392470SN/A uint64_t RxData; 140 uint64_t RxDone; 141 uint64_t TxData; 142 uint64_t TxDone; 143 144 PacketFifo::iterator rxIndex; 145 int rxPacketOffset; 146 int rxPacketBytes; 147 uint64_t rxDoneData; 148 149 Counter rxUnique; 150 Counter txUnique; 151 152 VirtualReg() 153 : RxData(0), RxDone(0), TxData(0), TxDone(0), 154 rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0) 155 { } 156 }; 157 typedef std::vector<VirtualReg> VirtualRegs; 158 typedef std::list<int> VirtualList; 159 Counter rxUnique; 160 Counter txUnique; 161 VirtualRegs virtualRegs; 162 VirtualList rxList; 163 VirtualList rxBusy; 164 int rxActive; 165 VirtualList txList; 166 167 int rxBusyCount; 168 int rxMappedCount; 169 int rxDirtyCount; 170 171 uint8_t ®Data8(Addr daddr) { return *((uint8_t *)®s + daddr); } 172 uint32_t ®Data32(Addr daddr) { return *(uint32_t *)®Data8(daddr); } 173 uint64_t ®Data64(Addr daddr) { return *(uint64_t *)®Data8(daddr); } 174 175 protected: 176 RxState rxState; 177 PacketFifo rxFifo; 178 PacketFifo::iterator rxFifoPtr; 179 bool rxEmpty; 180 bool rxLow; 181 Addr rxDmaAddr; 182 uint8_t *rxDmaData; 183 int rxDmaLen; 184 185 TxState txState; 186 PacketFifo txFifo; 187 bool txFull; 188 EthPacketPtr txPacket; 189 int txPacketOffset; 190 int txPacketBytes; 191 Addr txDmaAddr; 192 uint8_t *txDmaData; 193 int txDmaLen; 194 195 protected: 196 void reset(); 197 198 void rxKick(); 199 Tick rxKickTick; 200 typedef EventWrapper<Device, &Device::rxKick> RxKickEvent; 201 friend void RxKickEvent::process(); 202 203 void txKick(); 204 Tick txKickTick; 205 typedef EventWrapper<Device, &Device::txKick> TxKickEvent; 206 friend void TxKickEvent::process(); 207 208 /** 209 * Retransmit event 210 */ 211 void transmit(); 212 void txEventTransmit() 213 { 214 transmit(); 215 if (txState == txFifoBlock) 216 txKick(); 217 } 218 typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent; 219 friend void TxEvent::process(); 220 TxEvent txEvent; 221 222 void txDump() const; 223 void rxDump() const; 224 225 /** 226 * receive address filter 227 */ 228 bool rxFilter(const EthPacketPtr &packet); 229 230/** 231 * device configuration 232 */ 233 void changeConfig(uint32_t newconfig); 234 void command(uint32_t command); 235 236/** 237 * device ethernet interface 238 */ 239 public: 240 bool recvPacket(EthPacketPtr packet); 241 void transferDone(); 242 virtual EtherInt *getEthPort(const std::string &if_name, int idx); 243 244/** 245 * DMA parameters 246 */ 247 protected: 248 void rxDmaDone(); 249 friend class EventWrapper<Device, &Device::rxDmaDone>; 250 EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent; 251 252 void txDmaDone(); 253 friend class EventWrapper<Device, &Device::txDmaDone>; 254 EventWrapper<Device, &Device::txDmaDone> txDmaEvent; 255 256 Tick dmaReadDelay; 257 Tick dmaReadFactor; 258 Tick dmaWriteDelay; 259 Tick dmaWriteFactor; 260 261/** 262 * Interrupt management 263 */ 264 protected: 265 void devIntrPost(uint32_t interrupts); 266 void devIntrClear(uint32_t interrupts = Regs::Intr_All); 267 void devIntrChangeMask(uint32_t newmask); 268 269/** 270 * Memory Interface 271 */ 272 public: 273 virtual Tick read(PacketPtr pkt); 274 virtual Tick write(PacketPtr pkt); 275 virtual void resume(); 276 277 void prepareIO(int cpu, int index); 278 void prepareRead(int cpu, int index); 279 void prepareWrite(int cpu, int index); 280 // Fault iprRead(Addr daddr, int cpu, uint64_t &result); 281 282/** 283 * Statistics 284 */ 285 private: 286 Stats::Scalar<> rxBytes; 287 Stats::Formula rxBandwidth; 288 Stats::Scalar<> rxPackets; 289 Stats::Formula rxPacketRate; 290 Stats::Scalar<> rxIpPackets; 291 Stats::Scalar<> rxTcpPackets; 292 Stats::Scalar<> rxUdpPackets; 293 Stats::Scalar<> rxIpChecksums; 294 Stats::Scalar<> rxTcpChecksums; 295 Stats::Scalar<> rxUdpChecksums; 296 297 Stats::Scalar<> txBytes; 298 Stats::Formula txBandwidth; 299 Stats::Formula totBandwidth; 300 Stats::Formula totPackets; 301 Stats::Formula totBytes; 302 Stats::Formula totPacketRate; 303 Stats::Scalar<> txPackets; 304 Stats::Formula txPacketRate; 305 Stats::Scalar<> txIpPackets; 306 Stats::Scalar<> txTcpPackets; 307 Stats::Scalar<> txUdpPackets; 308 Stats::Scalar<> txIpChecksums; 309 Stats::Scalar<> txTcpChecksums; 310 Stats::Scalar<> txUdpChecksums; 311 312 Stats::Scalar<> totalVnicDistance; 313 Stats::Scalar<> numVnicDistance; 314 Stats::Scalar<> maxVnicDistance; 315 Stats::Formula avgVnicDistance; 316 317 int _maxVnicDistance; 318 319 public: 320 virtual void regStats(); 321 virtual void resetStats(); 322 323/** 324 * Serialization stuff 325 */ 326 public: 327 virtual void serialize(std::ostream &os); 328 virtual void unserialize(Checkpoint *cp, const std::string §ion); 329 330 public: 331 Device(const Params *p); 332 ~Device(); 333}; 334 335/* 336 * Ethernet Interface for an Ethernet Device 337 */ 338class Interface : public EtherInt 339{ 340 private: 341 Device *dev; 342 343 public: 344 Interface(const std::string &name, Device *d) 345 : EtherInt(name), dev(d) 346 { } 347 348 virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); } 349 virtual void sendDone() { dev->transferDone(); } 350}; 351 352/* namespace Sinic */ } 353 354#endif // __DEV_SINIC_HH__ 355