sinic.hh revision 1156
1/* 2 * Copyright (c) 2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __DEV_SINIC_HH__ 30#define __DEV_SINIC_HH__ 31 32#include "base/inet.hh" 33#include "base/statistics.hh" 34#include "dev/etherint.hh" 35#include "dev/etherpkt.hh" 36#include "dev/io_device.hh" 37#include "dev/pcidev.hh" 38#include "dev/pktfifo.hh" 39#include "dev/sinicreg.hh" 40#include "mem/bus/bus.hh" 41#include "sim/eventq.hh" 42 43namespace Sinic { 44 45class Interface; 46class Base : public PciDev 47{ 48 protected: 49 bool rxEnable; 50 bool txEnable; 51 52 protected: 53 Tick intrDelay; 54 Tick intrTick; 55 bool cpuIntrEnable; 56 bool cpuPendingIntr; 57 void cpuIntrPost(Tick when); 58 void cpuInterrupt(); 59 void cpuIntrClear(); 60 61 typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent; 62 friend class IntrEvent; 63 IntrEvent *intrEvent; 64 Interface *interface; 65 66 bool cpuIntrPending() const; 67 void cpuIntrAck() { cpuIntrClear(); } 68 69/** 70 * Serialization stuff 71 */ 72 public: 73 virtual void serialize(std::ostream &os); 74 virtual void unserialize(Checkpoint *cp, const std::string §ion); 75 76/** 77 * Construction/Destruction/Parameters 78 */ 79 public: 80 struct Params : public PciDev::Params 81 { 82 Tick intr_delay; 83 }; 84 85 Base(Params *p); 86}; 87 88class Device : public Base 89{ 90 protected: 91 Platform *plat; 92 PhysicalMemory *physmem; 93 94 protected: 95 /** Receive State Machine States */ 96 enum RxState { 97 rxIdle, 98 rxFifoBlock, 99 rxBeginCopy, 100 rxCopy, 101 rxCopyDone 102 }; 103 104 /** Transmit State Machine states */ 105 enum TxState { 106 txIdle, 107 txFifoBlock, 108 txBeginCopy, 109 txCopy, 110 txCopyDone 111 }; 112 113 /** device register file */ 114 struct { 115 uint32_t Config; 116 uint32_t RxMaxCopy; 117 uint32_t TxMaxCopy; 118 uint32_t RxThreshold; 119 uint32_t TxThreshold; 120 uint32_t IntrStatus; 121 uint32_t IntrMask; 122 uint64_t RxData; 123 uint64_t RxDone; 124 uint64_t TxData; 125 uint64_t TxDone; 126 } regs; 127 128 private: 129 Addr addr; 130 static const Addr size = Regs::Size; 131 132 protected: 133 RxState rxState; 134 PacketFifo rxFifo; 135 PacketPtr rxPacket; 136 uint8_t *rxPacketBufPtr; 137 int rxPktBytes; 138 uint64_t rxDoneData; 139 Addr rxDmaAddr; 140 uint8_t *rxDmaData; 141 int rxDmaLen; 142 143 TxState txState; 144 PacketFifo txFifo; 145 PacketPtr txPacket; 146 uint8_t *txPacketBufPtr; 147 int txPktBytes; 148 Addr txDmaAddr; 149 uint8_t *txDmaData; 150 int txDmaLen; 151 152 protected: 153 void reset(); 154 155 void rxKick(); 156 Tick rxKickTick; 157 typedef EventWrapper<Device, &Device::rxKick> RxKickEvent; 158 friend class RxKickEvent; 159 160 void txKick(); 161 Tick txKickTick; 162 typedef EventWrapper<Device, &Device::txKick> TxKickEvent; 163 friend class TxKickEvent; 164 165 /** 166 * Retransmit event 167 */ 168 void transmit(); 169 void txEventTransmit() 170 { 171 transmit(); 172 if (txState == txFifoBlock) 173 txKick(); 174 } 175 typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent; 176 friend class TxEvent; 177 TxEvent txEvent; 178 179 void txDump() const; 180 void rxDump() const; 181 182 /** 183 * receive address filter 184 */ 185 bool rxFilter(const PacketPtr &packet); 186 187/** 188 * device configuration 189 */ 190 void changeConfig(uint32_t newconfig); 191 192/** 193 * device ethernet interface 194 */ 195 public: 196 bool recvPacket(PacketPtr packet); 197 void transferDone(); 198 void setInterface(Interface *i) { assert(!interface); interface = i; } 199 200/** 201 * DMA parameters 202 */ 203 protected: 204 void rxDmaCopy(); 205 void rxDmaDone(); 206 friend class EventWrapper<Device, &Device::rxDmaDone>; 207 EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent; 208 209 void txDmaCopy(); 210 void txDmaDone(); 211 friend class EventWrapper<Device, &Device::txDmaDone>; 212 EventWrapper<Device, &Device::rxDmaDone> txDmaEvent; 213 214 Tick dmaReadDelay; 215 Tick dmaReadFactor; 216 Tick dmaWriteDelay; 217 Tick dmaWriteFactor; 218 219/** 220 * PIO parameters 221 */ 222 protected: 223 MemReqPtr rxPioRequest; 224 MemReqPtr txPioRequest; 225 226/** 227 * Interrupt management 228 */ 229 protected: 230 void devIntrPost(uint32_t interrupts); 231 void devIntrClear(uint32_t interrupts = Regs::Intr_All); 232 void devIntrChangeMask(uint32_t newmask); 233 234/** 235 * PCI Configuration interface 236 */ 237 public: 238 virtual void WriteConfig(int offset, int size, uint32_t data); 239 240/** 241 * Memory Interface 242 */ 243 public: 244 virtual Fault read(MemReqPtr &req, uint8_t *data); 245 virtual Fault write(MemReqPtr &req, const uint8_t *data); 246 Tick cacheAccess(MemReqPtr &req); 247 248/** 249 * Statistics 250 */ 251 private: 252 Stats::Scalar<> rxBytes; 253 Stats::Formula rxBandwidth; 254 Stats::Scalar<> rxPackets; 255 Stats::Formula rxPacketRate; 256 Stats::Scalar<> rxIpPackets; 257 Stats::Scalar<> rxTcpPackets; 258 Stats::Scalar<> rxUdpPackets; 259 Stats::Scalar<> rxIpChecksums; 260 Stats::Scalar<> rxTcpChecksums; 261 Stats::Scalar<> rxUdpChecksums; 262 263 Stats::Scalar<> txBytes; 264 Stats::Formula txBandwidth; 265 Stats::Scalar<> txPackets; 266 Stats::Formula txPacketRate; 267 Stats::Scalar<> txIpPackets; 268 Stats::Scalar<> txTcpPackets; 269 Stats::Scalar<> txUdpPackets; 270 Stats::Scalar<> txIpChecksums; 271 Stats::Scalar<> txTcpChecksums; 272 Stats::Scalar<> txUdpChecksums; 273 274 public: 275 virtual void regStats(); 276 277/** 278 * Serialization stuff 279 */ 280 public: 281 virtual void serialize(std::ostream &os); 282 virtual void unserialize(Checkpoint *cp, const std::string §ion); 283 284/** 285 * Construction/Destruction/Parameters 286 */ 287 public: 288 struct Params : public Base::Params 289 { 290 IntrControl *i; 291 PhysicalMemory *pmem; 292 Tick tx_delay; 293 Tick rx_delay; 294 HierParams *hier; 295 Bus *header_bus; 296 Bus *payload_bus; 297 Tick pio_latency; 298 PhysicalMemory *physmem; 299 IntrControl *intctrl; 300 bool rx_filter; 301 Net::EthAddr eaddr; 302 uint32_t rx_max_copy; 303 uint32_t tx_max_copy; 304 uint32_t rx_fifo_size; 305 uint32_t tx_fifo_size; 306 uint32_t rx_fifo_threshold; 307 uint32_t tx_fifo_threshold; 308 Tick dma_read_delay; 309 Tick dma_read_factor; 310 Tick dma_write_delay; 311 Tick dma_write_factor; 312 }; 313 314 protected: 315 const Params *params() const { return (const Params *)_params; } 316 317 public: 318 Device(Params *params); 319 ~Device(); 320}; 321 322/* 323 * Ethernet Interface for an Ethernet Device 324 */ 325class Interface : public EtherInt 326{ 327 private: 328 Device *dev; 329 330 public: 331 Interface(const std::string &name, Device *d) 332 : EtherInt(name), dev(d) { dev->setInterface(this); } 333 334 virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); } 335 virtual void sendDone() { dev->transferDone(); } 336}; 337 338/* namespace Sinic */ } 339 340#endif // __DEV_SINIC_HH__ 341