sinic.hh revision 6227 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31#ifndef __DEV_SINIC_HH__
32#define __DEV_SINIC_HH__
33
34#include "base/inet.hh"
35#include "base/statistics.hh"
36#include "dev/etherint.hh"
37#include "dev/etherpkt.hh"
38#include "dev/io_device.hh"
39#include "dev/pcidev.hh"
40#include "dev/pktfifo.hh"
41#include "dev/sinicreg.hh"
42#include "params/Sinic.hh"
43#include "sim/eventq.hh"
44
45namespace Sinic {
46
47class Interface;
48class Base : public PciDev
49{
50  protected:
51    bool rxEnable;
52    bool txEnable;
53    Tick clock;
54    inline Tick ticks(int numCycles) const { return numCycles * clock; }
55
56  protected:
57    Tick intrDelay;
58    Tick intrTick;
59    bool cpuIntrEnable;
60    bool cpuPendingIntr;
61    void cpuIntrPost(Tick when);
62    void cpuInterrupt();
63    void cpuIntrClear();
64
65    typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent;
66    friend void IntrEvent::process();
67    IntrEvent *intrEvent;
68    Interface *interface;
69
70    bool cpuIntrPending() const;
71    void cpuIntrAck() { cpuIntrClear(); }
72
73/**
74 * Serialization stuff
75 */
76  public:
77    virtual void serialize(std::ostream &os);
78    virtual void unserialize(Checkpoint *cp, const std::string &section);
79
80/**
81 * Construction/Destruction/Parameters
82 */
83  public:
84    typedef SinicParams Params;
85    const Params *params() const { return (const Params *)_params; }
86    Base(const Params *p);
87};
88
89class Device : public Base
90{
91  protected:
92    /** Receive State Machine States */
93    enum RxState {
94        rxIdle,
95        rxFifoBlock,
96        rxBeginCopy,
97        rxCopy,
98        rxCopyDone
99    };
100
101    /** Transmit State Machine states */
102    enum TxState {
103        txIdle,
104        txFifoBlock,
105        txBeginCopy,
106        txCopy,
107        txCopyDone
108    };
109
110    /** device register file */
111    struct {
112        uint32_t Config;       // 0x00
113        uint32_t Command;      // 0x04
114        uint32_t IntrStatus;   // 0x08
115        uint32_t IntrMask;     // 0x0c
116        uint32_t RxMaxCopy;    // 0x10
117        uint32_t TxMaxCopy;    // 0x14
118        uint32_t ZeroCopySize; // 0x18
119        uint32_t ZeroCopyMark; // 0x1c
120        uint32_t VirtualCount; // 0x20
121        uint32_t RxMaxIntr;    // 0x24
122        uint32_t RxFifoSize;   // 0x28
123        uint32_t TxFifoSize;   // 0x2c
124        uint32_t RxFifoLow;    // 0x30
125        uint32_t TxFifoLow;    // 0x34
126        uint32_t RxFifoHigh;   // 0x38
127        uint32_t TxFifoHigh;   // 0x3c
128        uint64_t RxData;       // 0x40
129        uint64_t RxDone;       // 0x48
130        uint64_t RxWait;       // 0x50
131        uint64_t TxData;       // 0x58
132        uint64_t TxDone;       // 0x60
133        uint64_t TxWait;       // 0x68
134        uint64_t HwAddr;       // 0x70
135        uint64_t RxStatus;     // 0x78
136    } regs;
137
138    struct VirtualReg {
139        uint64_t RxData;
140        uint64_t RxDone;
141        uint64_t TxData;
142        uint64_t TxDone;
143
144        PacketFifo::iterator rxIndex;
145        unsigned rxPacketOffset;
146        unsigned rxPacketBytes;
147        uint64_t rxDoneData;
148
149        Counter rxUnique;
150        Counter txUnique;
151
152        VirtualReg()
153            : RxData(0), RxDone(0), TxData(0), TxDone(0),
154              rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0)
155        { }
156    };
157    typedef std::vector<VirtualReg> VirtualRegs;
158    typedef std::list<unsigned> VirtualList;
159    Counter rxUnique;
160    Counter txUnique;
161    VirtualRegs virtualRegs;
162    VirtualList rxList;
163    VirtualList rxBusy;
164    int rxActive;
165    VirtualList txList;
166
167    int rxBusyCount;
168    int rxMappedCount;
169    int rxDirtyCount;
170
171    uint8_t  &regData8(Addr daddr) { return *((uint8_t *)&regs + daddr); }
172    uint32_t &regData32(Addr daddr) { return *(uint32_t *)&regData8(daddr); }
173    uint64_t &regData64(Addr daddr) { return *(uint64_t *)&regData8(daddr); }
174
175  protected:
176    RxState rxState;
177    PacketFifo rxFifo;
178    PacketFifo::iterator rxFifoPtr;
179    bool rxEmpty;
180    bool rxLow;
181    Addr rxDmaAddr;
182    uint8_t *rxDmaData;
183    unsigned rxDmaLen;
184
185    TxState txState;
186    PacketFifo txFifo;
187    bool txFull;
188    EthPacketPtr txPacket;
189    int txPacketOffset;
190    int txPacketBytes;
191    Addr txDmaAddr;
192    uint8_t *txDmaData;
193    int txDmaLen;
194
195  protected:
196    void reset();
197
198    void rxKick();
199    Tick rxKickTick;
200    typedef EventWrapper<Device, &Device::rxKick> RxKickEvent;
201    friend void RxKickEvent::process();
202
203    void txKick();
204    Tick txKickTick;
205    typedef EventWrapper<Device, &Device::txKick> TxKickEvent;
206    friend void TxKickEvent::process();
207
208    /**
209     * Retransmit event
210     */
211    void transmit();
212    void txEventTransmit()
213    {
214        transmit();
215        if (txState == txFifoBlock)
216            txKick();
217    }
218    typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent;
219    friend void TxEvent::process();
220    TxEvent txEvent;
221
222    void txDump() const;
223    void rxDump() const;
224
225    /**
226     * receive address filter
227     */
228    bool rxFilter(const EthPacketPtr &packet);
229
230/**
231 * device configuration
232 */
233    void changeConfig(uint32_t newconfig);
234    void command(uint32_t command);
235
236/**
237 * device ethernet interface
238 */
239  public:
240    bool recvPacket(EthPacketPtr packet);
241    void transferDone();
242    virtual EtherInt *getEthPort(const std::string &if_name, int idx);
243
244/**
245 * DMA parameters
246 */
247  protected:
248    void rxDmaDone();
249    friend class EventWrapper<Device, &Device::rxDmaDone>;
250    EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent;
251
252    void txDmaDone();
253    friend class EventWrapper<Device, &Device::txDmaDone>;
254    EventWrapper<Device, &Device::txDmaDone> txDmaEvent;
255
256    Tick dmaReadDelay;
257    Tick dmaReadFactor;
258    Tick dmaWriteDelay;
259    Tick dmaWriteFactor;
260
261/**
262 * Interrupt management
263 */
264  protected:
265    void devIntrPost(uint32_t interrupts);
266    void devIntrClear(uint32_t interrupts = Regs::Intr_All);
267    void devIntrChangeMask(uint32_t newmask);
268
269/**
270 * Memory Interface
271 */
272  public:
273    virtual Tick read(PacketPtr pkt);
274    virtual Tick write(PacketPtr pkt);
275    virtual void resume();
276
277    void prepareIO(int cpu, int index);
278    void prepareRead(int cpu, int index);
279    void prepareWrite(int cpu, int index);
280 //   Fault iprRead(Addr daddr, int cpu, uint64_t &result);
281
282/**
283 * Statistics
284 */
285  private:
286    Stats::Scalar rxBytes;
287    Stats::Formula  rxBandwidth;
288    Stats::Scalar rxPackets;
289    Stats::Formula  rxPacketRate;
290    Stats::Scalar rxIpPackets;
291    Stats::Scalar rxTcpPackets;
292    Stats::Scalar rxUdpPackets;
293    Stats::Scalar rxIpChecksums;
294    Stats::Scalar rxTcpChecksums;
295    Stats::Scalar rxUdpChecksums;
296
297    Stats::Scalar txBytes;
298    Stats::Formula  txBandwidth;
299    Stats::Formula totBandwidth;
300    Stats::Formula totPackets;
301    Stats::Formula totBytes;
302    Stats::Formula totPacketRate;
303    Stats::Scalar txPackets;
304    Stats::Formula  txPacketRate;
305    Stats::Scalar txIpPackets;
306    Stats::Scalar txTcpPackets;
307    Stats::Scalar txUdpPackets;
308    Stats::Scalar txIpChecksums;
309    Stats::Scalar txTcpChecksums;
310    Stats::Scalar txUdpChecksums;
311
312    Stats::Scalar totalVnicDistance;
313    Stats::Scalar numVnicDistance;
314    Stats::Scalar maxVnicDistance;
315    Stats::Formula avgVnicDistance;
316
317    int _maxVnicDistance;
318
319  public:
320    virtual void regStats();
321    virtual void resetStats();
322
323/**
324 * Serialization stuff
325 */
326  public:
327    virtual void serialize(std::ostream &os);
328    virtual void unserialize(Checkpoint *cp, const std::string &section);
329
330  public:
331    Device(const Params *p);
332    ~Device();
333};
334
335/*
336 * Ethernet Interface for an Ethernet Device
337 */
338class Interface : public EtherInt
339{
340  private:
341    Device *dev;
342
343  public:
344    Interface(const std::string &name, Device *d)
345        : EtherInt(name), dev(d)
346    { }
347
348    virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
349    virtual void sendDone() { dev->transferDone(); }
350};
351
352/* namespace Sinic */ }
353
354#endif // __DEV_SINIC_HH__
355