sinic.hh revision 2566
113996Sgiacomo.travaglini@arm.com/* 213996Sgiacomo.travaglini@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 313996Sgiacomo.travaglini@arm.com * All rights reserved. 413996Sgiacomo.travaglini@arm.com * 513996Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 613996Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 713996Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 813996Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 913996Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1013996Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 1113996Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 1213996Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 1313996Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 1413996Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 1513996Sgiacomo.travaglini@arm.com * 1613996Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1713996Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1813996Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1913996Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2013996Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2113996Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2213996Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2313996Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2413996Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2513996Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2613996Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2713996Sgiacomo.travaglini@arm.com */ 2813996Sgiacomo.travaglini@arm.com 2913996Sgiacomo.travaglini@arm.com#ifndef __DEV_SINIC_HH__ 3013996Sgiacomo.travaglini@arm.com#define __DEV_SINIC_HH__ 3113996Sgiacomo.travaglini@arm.com 3213996Sgiacomo.travaglini@arm.com#include "base/inet.hh" 3313996Sgiacomo.travaglini@arm.com#include "base/statistics.hh" 3413996Sgiacomo.travaglini@arm.com#include "dev/etherint.hh" 3513996Sgiacomo.travaglini@arm.com#include "dev/etherpkt.hh" 3613996Sgiacomo.travaglini@arm.com#include "dev/io_device.hh" 3713996Sgiacomo.travaglini@arm.com#include "dev/pcidev.hh" 3813996Sgiacomo.travaglini@arm.com#include "dev/pktfifo.hh" 3913996Sgiacomo.travaglini@arm.com#include "dev/sinicreg.hh" 4013996Sgiacomo.travaglini@arm.com#include "sim/eventq.hh" 4113996Sgiacomo.travaglini@arm.com 4213996Sgiacomo.travaglini@arm.comnamespace Sinic { 4313996Sgiacomo.travaglini@arm.com 4413996Sgiacomo.travaglini@arm.comclass Interface; 4513996Sgiacomo.travaglini@arm.comclass Base : public PciDev 4613996Sgiacomo.travaglini@arm.com{ 4713996Sgiacomo.travaglini@arm.com protected: 4813996Sgiacomo.travaglini@arm.com bool rxEnable; 4913996Sgiacomo.travaglini@arm.com bool txEnable; 5013996Sgiacomo.travaglini@arm.com Tick clock; 5113996Sgiacomo.travaglini@arm.com inline Tick cycles(int numCycles) const { return numCycles * clock; } 5213996Sgiacomo.travaglini@arm.com 5313996Sgiacomo.travaglini@arm.com protected: 5413996Sgiacomo.travaglini@arm.com Tick intrDelay; 5514181Sgiacomo.travaglini@arm.com Tick intrTick; 5614181Sgiacomo.travaglini@arm.com bool cpuIntrEnable; 5713996Sgiacomo.travaglini@arm.com bool cpuPendingIntr; 5813996Sgiacomo.travaglini@arm.com void cpuIntrPost(Tick when); 5913996Sgiacomo.travaglini@arm.com void cpuInterrupt(); 6013996Sgiacomo.travaglini@arm.com void cpuIntrClear(); 6113996Sgiacomo.travaglini@arm.com 6213996Sgiacomo.travaglini@arm.com typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent; 6313996Sgiacomo.travaglini@arm.com friend void IntrEvent::process(); 6413996Sgiacomo.travaglini@arm.com IntrEvent *intrEvent; 6513996Sgiacomo.travaglini@arm.com Interface *interface; 6613996Sgiacomo.travaglini@arm.com 6713996Sgiacomo.travaglini@arm.com bool cpuIntrPending() const; 6813996Sgiacomo.travaglini@arm.com void cpuIntrAck() { cpuIntrClear(); } 6913996Sgiacomo.travaglini@arm.com 7013996Sgiacomo.travaglini@arm.com/** 7113996Sgiacomo.travaglini@arm.com * Serialization stuff 7213996Sgiacomo.travaglini@arm.com */ 7313996Sgiacomo.travaglini@arm.com public: 7413996Sgiacomo.travaglini@arm.com virtual void serialize(std::ostream &os); 7513996Sgiacomo.travaglini@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 7613996Sgiacomo.travaglini@arm.com 7713996Sgiacomo.travaglini@arm.com/** 7813996Sgiacomo.travaglini@arm.com * Construction/Destruction/Parameters 7913996Sgiacomo.travaglini@arm.com */ 8013996Sgiacomo.travaglini@arm.com public: 8113996Sgiacomo.travaglini@arm.com struct Params : public PciDev::Params 8213996Sgiacomo.travaglini@arm.com { 8313996Sgiacomo.travaglini@arm.com Tick clock; 8413996Sgiacomo.travaglini@arm.com Tick intr_delay; 8513996Sgiacomo.travaglini@arm.com }; 8613996Sgiacomo.travaglini@arm.com 8713996Sgiacomo.travaglini@arm.com Base(Params *p); 8813996Sgiacomo.travaglini@arm.com}; 8913996Sgiacomo.travaglini@arm.com 9013996Sgiacomo.travaglini@arm.comclass Device : public Base 9113996Sgiacomo.travaglini@arm.com{ 9213996Sgiacomo.travaglini@arm.com protected: 9313996Sgiacomo.travaglini@arm.com /** Receive State Machine States */ 9413996Sgiacomo.travaglini@arm.com enum RxState { 9513996Sgiacomo.travaglini@arm.com rxIdle, 9613996Sgiacomo.travaglini@arm.com rxFifoBlock, 9713996Sgiacomo.travaglini@arm.com rxBeginCopy, 9813996Sgiacomo.travaglini@arm.com rxCopy, 9913996Sgiacomo.travaglini@arm.com rxCopyDone 10013996Sgiacomo.travaglini@arm.com }; 10113996Sgiacomo.travaglini@arm.com 10213996Sgiacomo.travaglini@arm.com /** Transmit State Machine states */ 10313996Sgiacomo.travaglini@arm.com enum TxState { 10413996Sgiacomo.travaglini@arm.com txIdle, 10513996Sgiacomo.travaglini@arm.com txFifoBlock, 10613996Sgiacomo.travaglini@arm.com txBeginCopy, 10713996Sgiacomo.travaglini@arm.com txCopy, 10813996Sgiacomo.travaglini@arm.com txCopyDone 10913996Sgiacomo.travaglini@arm.com }; 11013996Sgiacomo.travaglini@arm.com 11113996Sgiacomo.travaglini@arm.com /** device register file */ 11213996Sgiacomo.travaglini@arm.com struct { 11313996Sgiacomo.travaglini@arm.com uint32_t Config; // 0x00 11413996Sgiacomo.travaglini@arm.com uint32_t Command; // 0x04 11513996Sgiacomo.travaglini@arm.com uint32_t IntrStatus; // 0x08 11613996Sgiacomo.travaglini@arm.com uint32_t IntrMask; // 0x0c 11713996Sgiacomo.travaglini@arm.com uint32_t RxMaxCopy; // 0x10 11813996Sgiacomo.travaglini@arm.com uint32_t TxMaxCopy; // 0x14 11913996Sgiacomo.travaglini@arm.com uint32_t RxMaxIntr; // 0x18 12013996Sgiacomo.travaglini@arm.com uint32_t Reserved0; // 0x1c 12113996Sgiacomo.travaglini@arm.com uint32_t RxFifoSize; // 0x20 12213996Sgiacomo.travaglini@arm.com uint32_t TxFifoSize; // 0x24 12313996Sgiacomo.travaglini@arm.com uint32_t RxFifoMark; // 0x28 12413996Sgiacomo.travaglini@arm.com uint32_t TxFifoMark; // 0x2c 12513996Sgiacomo.travaglini@arm.com uint64_t RxData; // 0x30 12613996Sgiacomo.travaglini@arm.com uint64_t RxDone; // 0x38 12713996Sgiacomo.travaglini@arm.com uint64_t RxWait; // 0x40 12813996Sgiacomo.travaglini@arm.com uint64_t TxData; // 0x48 12913996Sgiacomo.travaglini@arm.com uint64_t TxDone; // 0x50 13013996Sgiacomo.travaglini@arm.com uint64_t TxWait; // 0x58 13113996Sgiacomo.travaglini@arm.com uint64_t HwAddr; // 0x60 13213996Sgiacomo.travaglini@arm.com } regs; 13313996Sgiacomo.travaglini@arm.com 13413996Sgiacomo.travaglini@arm.com struct VirtualReg { 13513996Sgiacomo.travaglini@arm.com uint64_t RxData; 13613996Sgiacomo.travaglini@arm.com uint64_t RxDone; 13713996Sgiacomo.travaglini@arm.com uint64_t TxData; 13813996Sgiacomo.travaglini@arm.com uint64_t TxDone; 13913996Sgiacomo.travaglini@arm.com 14013996Sgiacomo.travaglini@arm.com PacketFifo::iterator rxPacket; 14113996Sgiacomo.travaglini@arm.com int rxPacketOffset; 14213996Sgiacomo.travaglini@arm.com int rxPacketBytes; 14313996Sgiacomo.travaglini@arm.com uint64_t rxDoneData; 14413996Sgiacomo.travaglini@arm.com 14513996Sgiacomo.travaglini@arm.com VirtualReg() 14613996Sgiacomo.travaglini@arm.com : RxData(0), RxDone(0), TxData(0), TxDone(0), 14713996Sgiacomo.travaglini@arm.com rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0) 14813996Sgiacomo.travaglini@arm.com { } 14914188Sgiacomo.travaglini@arm.com }; 15013996Sgiacomo.travaglini@arm.com typedef std::vector<VirtualReg> VirtualRegs; 15113996Sgiacomo.travaglini@arm.com typedef std::list<int> VirtualList; 15213996Sgiacomo.travaglini@arm.com VirtualRegs virtualRegs; 15313996Sgiacomo.travaglini@arm.com VirtualList rxList; 15413996Sgiacomo.travaglini@arm.com VirtualList txList; 15513996Sgiacomo.travaglini@arm.com 15613996Sgiacomo.travaglini@arm.com uint8_t ®Data8(Addr daddr) { return *((uint8_t *)®s + daddr); } 15713996Sgiacomo.travaglini@arm.com uint32_t ®Data32(Addr daddr) { return *(uint32_t *)®Data8(daddr); } 15813996Sgiacomo.travaglini@arm.com uint64_t ®Data64(Addr daddr) { return *(uint64_t *)®Data8(daddr); } 15913996Sgiacomo.travaglini@arm.com 16014188Sgiacomo.travaglini@arm.com protected: 16113996Sgiacomo.travaglini@arm.com RxState rxState; 16213996Sgiacomo.travaglini@arm.com PacketFifo rxFifo; 16313996Sgiacomo.travaglini@arm.com PacketFifo::iterator rxFifoPtr; 16413996Sgiacomo.travaglini@arm.com bool rxEmpty; 16513996Sgiacomo.travaglini@arm.com Addr rxDmaAddr; 16613996Sgiacomo.travaglini@arm.com uint8_t *rxDmaData; 16713996Sgiacomo.travaglini@arm.com int rxDmaLen; 16813996Sgiacomo.travaglini@arm.com 16913996Sgiacomo.travaglini@arm.com TxState txState; 17013996Sgiacomo.travaglini@arm.com PacketFifo txFifo; 17113996Sgiacomo.travaglini@arm.com bool txFull; 17214188Sgiacomo.travaglini@arm.com EthPacketPtr txPacket; 17313996Sgiacomo.travaglini@arm.com int txPacketOffset; 17413996Sgiacomo.travaglini@arm.com int txPacketBytes; 17513996Sgiacomo.travaglini@arm.com Addr txDmaAddr; 17613996Sgiacomo.travaglini@arm.com uint8_t *txDmaData; 17713996Sgiacomo.travaglini@arm.com int txDmaLen; 17813996Sgiacomo.travaglini@arm.com 17913996Sgiacomo.travaglini@arm.com protected: 18013996Sgiacomo.travaglini@arm.com void reset(); 18113996Sgiacomo.travaglini@arm.com 18214188Sgiacomo.travaglini@arm.com void rxKick(); 18313996Sgiacomo.travaglini@arm.com Tick rxKickTick; 18414188Sgiacomo.travaglini@arm.com typedef EventWrapper<Device, &Device::rxKick> RxKickEvent; 18513996Sgiacomo.travaglini@arm.com friend void RxKickEvent::process(); 18613996Sgiacomo.travaglini@arm.com 18713996Sgiacomo.travaglini@arm.com void txKick(); 18813996Sgiacomo.travaglini@arm.com Tick txKickTick; 18913996Sgiacomo.travaglini@arm.com typedef EventWrapper<Device, &Device::txKick> TxKickEvent; 19013996Sgiacomo.travaglini@arm.com friend void TxKickEvent::process(); 19113996Sgiacomo.travaglini@arm.com 19213996Sgiacomo.travaglini@arm.com /** 19313996Sgiacomo.travaglini@arm.com * Retransmit event 19413996Sgiacomo.travaglini@arm.com */ 19513996Sgiacomo.travaglini@arm.com void transmit(); 19614188Sgiacomo.travaglini@arm.com void txEventTransmit() 19714188Sgiacomo.travaglini@arm.com { 19813996Sgiacomo.travaglini@arm.com transmit(); 19913996Sgiacomo.travaglini@arm.com if (txState == txFifoBlock) 20013996Sgiacomo.travaglini@arm.com txKick(); 20113996Sgiacomo.travaglini@arm.com } 20213996Sgiacomo.travaglini@arm.com typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent; 20313996Sgiacomo.travaglini@arm.com friend void TxEvent::process(); 20413996Sgiacomo.travaglini@arm.com TxEvent txEvent; 20513996Sgiacomo.travaglini@arm.com 20613996Sgiacomo.travaglini@arm.com void txDump() const; 20713996Sgiacomo.travaglini@arm.com void rxDump() const; 20814188Sgiacomo.travaglini@arm.com 20913996Sgiacomo.travaglini@arm.com /** 21014188Sgiacomo.travaglini@arm.com * receive address filter 21113996Sgiacomo.travaglini@arm.com */ 21213996Sgiacomo.travaglini@arm.com bool rxFilter(const EthPacketPtr &packet); 21313996Sgiacomo.travaglini@arm.com 21413996Sgiacomo.travaglini@arm.com/** 21513996Sgiacomo.travaglini@arm.com * device configuration 21613996Sgiacomo.travaglini@arm.com */ 21713996Sgiacomo.travaglini@arm.com void changeConfig(uint32_t newconfig); 21813996Sgiacomo.travaglini@arm.com void command(uint32_t command); 21913996Sgiacomo.travaglini@arm.com 22013996Sgiacomo.travaglini@arm.com/** 22113996Sgiacomo.travaglini@arm.com * device ethernet interface 22213996Sgiacomo.travaglini@arm.com */ 22314181Sgiacomo.travaglini@arm.com public: 22413996Sgiacomo.travaglini@arm.com bool recvPacket(EthPacketPtr packet); 22513996Sgiacomo.travaglini@arm.com void transferDone(); 22613996Sgiacomo.travaglini@arm.com void setInterface(Interface *i) { assert(!interface); interface = i; } 22713996Sgiacomo.travaglini@arm.com 22813996Sgiacomo.travaglini@arm.com/** 22913996Sgiacomo.travaglini@arm.com * DMA parameters 23014181Sgiacomo.travaglini@arm.com */ 23114181Sgiacomo.travaglini@arm.com protected: 23213996Sgiacomo.travaglini@arm.com void rxDmaDone(); 23313996Sgiacomo.travaglini@arm.com friend class EventWrapper<Device, &Device::rxDmaDone>; 23413996Sgiacomo.travaglini@arm.com EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent; 23513996Sgiacomo.travaglini@arm.com 23613996Sgiacomo.travaglini@arm.com void txDmaDone(); 23713996Sgiacomo.travaglini@arm.com friend class EventWrapper<Device, &Device::txDmaDone>; 23813996Sgiacomo.travaglini@arm.com EventWrapper<Device, &Device::txDmaDone> txDmaEvent; 23913996Sgiacomo.travaglini@arm.com 24013996Sgiacomo.travaglini@arm.com Tick dmaReadDelay; 24113996Sgiacomo.travaglini@arm.com Tick dmaReadFactor; 24213996Sgiacomo.travaglini@arm.com Tick dmaWriteDelay; 24313996Sgiacomo.travaglini@arm.com Tick dmaWriteFactor; 24413996Sgiacomo.travaglini@arm.com 24513996Sgiacomo.travaglini@arm.com/** 24613996Sgiacomo.travaglini@arm.com * Interrupt management 24713996Sgiacomo.travaglini@arm.com */ 24813996Sgiacomo.travaglini@arm.com protected: 24913996Sgiacomo.travaglini@arm.com void devIntrPost(uint32_t interrupts); 25013996Sgiacomo.travaglini@arm.com void devIntrClear(uint32_t interrupts = Regs::Intr_All); 25113996Sgiacomo.travaglini@arm.com void devIntrChangeMask(uint32_t newmask); 25213996Sgiacomo.travaglini@arm.com 25313996Sgiacomo.travaglini@arm.com/** 25413996Sgiacomo.travaglini@arm.com * Memory Interface 25513996Sgiacomo.travaglini@arm.com */ 25613996Sgiacomo.travaglini@arm.com public: 25713996Sgiacomo.travaglini@arm.com virtual Tick read(Packet &pkt); 25813996Sgiacomo.travaglini@arm.com virtual Tick write(Packet &pkt); 25913996Sgiacomo.travaglini@arm.com 26013996Sgiacomo.travaglini@arm.com void prepareIO(int cpu, int index); 26113996Sgiacomo.travaglini@arm.com void prepareRead(int cpu, int index); 26213996Sgiacomo.travaglini@arm.com void prepareWrite(int cpu, int index); 26313996Sgiacomo.travaglini@arm.com // Fault iprRead(Addr daddr, int cpu, uint64_t &result); 26413996Sgiacomo.travaglini@arm.com 26513996Sgiacomo.travaglini@arm.com/** 26613996Sgiacomo.travaglini@arm.com * Statistics 26713996Sgiacomo.travaglini@arm.com */ 26813996Sgiacomo.travaglini@arm.com private: 26913996Sgiacomo.travaglini@arm.com Stats::Scalar<> rxBytes; 27013996Sgiacomo.travaglini@arm.com Stats::Formula rxBandwidth; 27113996Sgiacomo.travaglini@arm.com Stats::Scalar<> rxPackets; 27213996Sgiacomo.travaglini@arm.com Stats::Formula rxPacketRate; 27313996Sgiacomo.travaglini@arm.com Stats::Scalar<> rxIpPackets; 27413996Sgiacomo.travaglini@arm.com Stats::Scalar<> rxTcpPackets; 27513996Sgiacomo.travaglini@arm.com Stats::Scalar<> rxUdpPackets; 27613996Sgiacomo.travaglini@arm.com Stats::Scalar<> rxIpChecksums; 27713996Sgiacomo.travaglini@arm.com Stats::Scalar<> rxTcpChecksums; 27813996Sgiacomo.travaglini@arm.com Stats::Scalar<> rxUdpChecksums; 27913996Sgiacomo.travaglini@arm.com 28013996Sgiacomo.travaglini@arm.com Stats::Scalar<> txBytes; 28113996Sgiacomo.travaglini@arm.com Stats::Formula txBandwidth; 28213996Sgiacomo.travaglini@arm.com Stats::Formula totBandwidth; 28313996Sgiacomo.travaglini@arm.com Stats::Formula totPackets; 28413996Sgiacomo.travaglini@arm.com Stats::Formula totBytes; 28513996Sgiacomo.travaglini@arm.com Stats::Formula totPacketRate; 28613996Sgiacomo.travaglini@arm.com Stats::Scalar<> txPackets; 28713996Sgiacomo.travaglini@arm.com Stats::Formula txPacketRate; 28813996Sgiacomo.travaglini@arm.com Stats::Scalar<> txIpPackets; 28913996Sgiacomo.travaglini@arm.com Stats::Scalar<> txTcpPackets; 29013996Sgiacomo.travaglini@arm.com Stats::Scalar<> txUdpPackets; 29113996Sgiacomo.travaglini@arm.com Stats::Scalar<> txIpChecksums; 29213996Sgiacomo.travaglini@arm.com Stats::Scalar<> txTcpChecksums; 29313996Sgiacomo.travaglini@arm.com Stats::Scalar<> txUdpChecksums; 29413996Sgiacomo.travaglini@arm.com 29513996Sgiacomo.travaglini@arm.com public: 29613996Sgiacomo.travaglini@arm.com virtual void regStats(); 29713996Sgiacomo.travaglini@arm.com 29813996Sgiacomo.travaglini@arm.com/** 29913996Sgiacomo.travaglini@arm.com * Serialization stuff 30013996Sgiacomo.travaglini@arm.com */ 30113996Sgiacomo.travaglini@arm.com public: 30213996Sgiacomo.travaglini@arm.com virtual void serialize(std::ostream &os); 30313996Sgiacomo.travaglini@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 30413996Sgiacomo.travaglini@arm.com 30513996Sgiacomo.travaglini@arm.com/** 30613996Sgiacomo.travaglini@arm.com * Construction/Destruction/Parameters 30713996Sgiacomo.travaglini@arm.com */ 30813996Sgiacomo.travaglini@arm.com public: 30913996Sgiacomo.travaglini@arm.com struct Params : public Base::Params 31013996Sgiacomo.travaglini@arm.com { 31113996Sgiacomo.travaglini@arm.com Tick tx_delay; 31213996Sgiacomo.travaglini@arm.com Tick rx_delay; 31313996Sgiacomo.travaglini@arm.com bool rx_filter; 31413996Sgiacomo.travaglini@arm.com Net::EthAddr eaddr; 31513996Sgiacomo.travaglini@arm.com uint32_t rx_max_copy; 31613996Sgiacomo.travaglini@arm.com uint32_t tx_max_copy; 31714181Sgiacomo.travaglini@arm.com uint32_t rx_max_intr; 31814181Sgiacomo.travaglini@arm.com uint32_t rx_fifo_size; 31913996Sgiacomo.travaglini@arm.com uint32_t tx_fifo_size; 32013996Sgiacomo.travaglini@arm.com uint32_t rx_fifo_threshold; 32113996Sgiacomo.travaglini@arm.com uint32_t tx_fifo_threshold; 32213996Sgiacomo.travaglini@arm.com Tick dma_read_delay; 32313996Sgiacomo.travaglini@arm.com Tick dma_read_factor; 32414181Sgiacomo.travaglini@arm.com Tick dma_write_delay; 32514181Sgiacomo.travaglini@arm.com Tick dma_write_factor; 32614181Sgiacomo.travaglini@arm.com bool rx_thread; 32713996Sgiacomo.travaglini@arm.com bool tx_thread; 32813996Sgiacomo.travaglini@arm.com bool rss; 32913996Sgiacomo.travaglini@arm.com }; 33013996Sgiacomo.travaglini@arm.com 33113996Sgiacomo.travaglini@arm.com protected: 33213996Sgiacomo.travaglini@arm.com const Params *params() const { return (const Params *)_params; } 33313996Sgiacomo.travaglini@arm.com 33413996Sgiacomo.travaglini@arm.com public: 33513996Sgiacomo.travaglini@arm.com Device(Params *params); 33613996Sgiacomo.travaglini@arm.com ~Device(); 33713996Sgiacomo.travaglini@arm.com}; 33813996Sgiacomo.travaglini@arm.com 33913996Sgiacomo.travaglini@arm.com/* 34013996Sgiacomo.travaglini@arm.com * Ethernet Interface for an Ethernet Device 34113996Sgiacomo.travaglini@arm.com */ 34213996Sgiacomo.travaglini@arm.comclass Interface : public EtherInt 34313996Sgiacomo.travaglini@arm.com{ 34413996Sgiacomo.travaglini@arm.com private: 34513996Sgiacomo.travaglini@arm.com Device *dev; 34613996Sgiacomo.travaglini@arm.com 34713996Sgiacomo.travaglini@arm.com public: 34813996Sgiacomo.travaglini@arm.com Interface(const std::string &name, Device *d) 34913996Sgiacomo.travaglini@arm.com : EtherInt(name), dev(d) { dev->setInterface(this); } 35013996Sgiacomo.travaglini@arm.com 35113996Sgiacomo.travaglini@arm.com virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); } 35213996Sgiacomo.travaglini@arm.com virtual void sendDone() { dev->transferDone(); } 35313996Sgiacomo.travaglini@arm.com}; 35413996Sgiacomo.travaglini@arm.com 35513996Sgiacomo.travaglini@arm.com/* namespace Sinic */ } 35613996Sgiacomo.travaglini@arm.com 35713996Sgiacomo.travaglini@arm.com#endif // __DEV_SINIC_HH__ 35813996Sgiacomo.travaglini@arm.com