sinic.hh revision 11005
12623SN/A/* 22623SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#ifndef __DEV_SINIC_HH__ 328105Sgblack@eecs.umich.edu#define __DEV_SINIC_HH__ 332623SN/A 344040Ssaidi@eecs.umich.edu#include "base/inet.hh" 356658Snate@binkert.org#include "base/statistics.hh" 362623SN/A#include "dev/etherdevice.hh" 372623SN/A#include "dev/etherint.hh" 383348Sbinkertn@umich.edu#include "dev/etherpkt.hh" 393348Sbinkertn@umich.edu#include "dev/io_device.hh" 404762Snate@binkert.org#include "dev/pcidev.hh" 417678Sgblack@eecs.umich.edu#include "dev/pktfifo.hh" 422901Ssaidi@eecs.umich.edu#include "dev/sinicreg.hh" 432623SN/A#include "params/Sinic.hh" 442623SN/A#include "sim/eventq.hh" 452623SN/A 462623SN/Anamespace Sinic { 472623SN/A 485606Snate@binkert.orgclass Interface; 492623SN/Aclass Base : public EtherDevBase 502623SN/A{ 512623SN/A protected: 522623SN/A bool rxEnable; 532623SN/A bool txEnable; 542623SN/A 552623SN/A protected: 562623SN/A Tick intrDelay; 572623SN/A Tick intrTick; 582623SN/A bool cpuIntrEnable; 592623SN/A bool cpuPendingIntr; 605336Shines@cs.fsu.edu void cpuIntrPost(Tick when); 612623SN/A void cpuInterrupt(); 624873Sstever@eecs.umich.edu void cpuIntrClear(); 632623SN/A 642623SN/A typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent; 652856Srdreslin@umich.edu friend void IntrEvent::process(); 666227Snate@binkert.org IntrEvent *intrEvent; 672856Srdreslin@umich.edu Interface *interface; 682856Srdreslin@umich.edu 692856Srdreslin@umich.edu bool cpuIntrPending() const; 702856Srdreslin@umich.edu void cpuIntrAck() { cpuIntrClear(); } 712856Srdreslin@umich.edu 724968Sacolyte@umich.edu/** 734968Sacolyte@umich.edu * Serialization stuff 744968Sacolyte@umich.edu */ 754968Sacolyte@umich.edu public: 762856Srdreslin@umich.edu void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 772856Srdreslin@umich.edu void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 782856Srdreslin@umich.edu 792623SN/A/** 802623SN/A * Construction/Destruction/Parameters 812623SN/A */ 822623SN/A public: 832623SN/A typedef SinicParams Params; 842623SN/A const Params *params() const { return (const Params *)_params; } 856221Snate@binkert.org Base(const Params *p); 866221Snate@binkert.org}; 872680Sktlim@umich.edu 882623SN/Aclass Device : public Base 892623SN/A{ 905714Shsul@eecs.umich.edu protected: 912623SN/A /** Receive State Machine States */ 922623SN/A enum RxState { 934968Sacolyte@umich.edu rxIdle, 944968Sacolyte@umich.edu rxFifoBlock, 954968Sacolyte@umich.edu rxBeginCopy, 964968Sacolyte@umich.edu rxCopy, 974968Sacolyte@umich.edu rxCopyDone 984968Sacolyte@umich.edu }; 995714Shsul@eecs.umich.edu 1005712Shsul@eecs.umich.edu /** Transmit State Machine states */ 1015712Shsul@eecs.umich.edu enum TxState { 1025712Shsul@eecs.umich.edu txIdle, 1032623SN/A txFifoBlock, 1042623SN/A txBeginCopy, 1052623SN/A txCopy, 1063349Sbinkertn@umich.edu txCopyDone 1072623SN/A }; 1083184Srdreslin@umich.edu 1092623SN/A /** device register file */ 1102623SN/A struct { 1112623SN/A uint32_t Config; // 0x00 1122623SN/A uint32_t Command; // 0x04 1133349Sbinkertn@umich.edu uint32_t IntrStatus; // 0x08 1142623SN/A uint32_t IntrMask; // 0x0c 1153310Srdreslin@umich.edu uint32_t RxMaxCopy; // 0x10 1163649Srdreslin@umich.edu uint32_t TxMaxCopy; // 0x14 1172623SN/A uint32_t ZeroCopySize; // 0x18 1182623SN/A uint32_t ZeroCopyMark; // 0x1c 1192623SN/A uint32_t VirtualCount; // 0x20 1203349Sbinkertn@umich.edu uint32_t RxMaxIntr; // 0x24 1212623SN/A uint32_t RxFifoSize; // 0x28 1223184Srdreslin@umich.edu uint32_t TxFifoSize; // 0x2c 1233184Srdreslin@umich.edu uint32_t RxFifoLow; // 0x30 1242623SN/A uint32_t TxFifoLow; // 0x34 1252623SN/A uint32_t RxFifoHigh; // 0x38 1262623SN/A uint32_t TxFifoHigh; // 0x3c 1272623SN/A uint64_t RxData; // 0x40 1282623SN/A uint64_t RxDone; // 0x48 1293647Srdreslin@umich.edu uint64_t RxWait; // 0x50 1303647Srdreslin@umich.edu uint64_t TxData; // 0x58 1313647Srdreslin@umich.edu uint64_t TxDone; // 0x60 1323647Srdreslin@umich.edu uint64_t TxWait; // 0x68 1333647Srdreslin@umich.edu uint64_t HwAddr; // 0x70 1342626SN/A uint64_t RxStatus; // 0x78 1353647Srdreslin@umich.edu } regs; 1362626SN/A 1372623SN/A struct VirtualReg { 1382623SN/A uint64_t RxData; 1392623SN/A uint64_t RxDone; 1402657Ssaidi@eecs.umich.edu uint64_t TxData; 1412623SN/A uint64_t TxDone; 1422623SN/A 1432623SN/A PacketFifo::iterator rxIndex; 1442623SN/A unsigned rxPacketOffset; 1452623SN/A unsigned rxPacketBytes; 1464192Sktlim@umich.edu uint64_t rxDoneData; 1474192Sktlim@umich.edu 1484192Sktlim@umich.edu Counter rxUnique; 1494192Sktlim@umich.edu Counter txUnique; 1504192Sktlim@umich.edu 1514192Sktlim@umich.edu VirtualReg() 1524192Sktlim@umich.edu : RxData(0), RxDone(0), TxData(0), TxDone(0), 1534192Sktlim@umich.edu rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0) 1545497Ssaidi@eecs.umich.edu { } 1554192Sktlim@umich.edu }; 1564192Sktlim@umich.edu typedef std::vector<VirtualReg> VirtualRegs; 1572623SN/A typedef std::list<unsigned> VirtualList; 1585529Snate@binkert.org Counter rxUnique; 1596078Sgblack@eecs.umich.edu Counter txUnique; 1605487Snate@binkert.org VirtualRegs virtualRegs; 1615487Snate@binkert.org VirtualList rxList; 1624968Sacolyte@umich.edu VirtualList rxBusy; 1634968Sacolyte@umich.edu int rxActive; 1642623SN/A VirtualList txList; 1652623SN/A 1662623SN/A int rxBusyCount; 1673647Srdreslin@umich.edu int rxMappedCount; 1683647Srdreslin@umich.edu int rxDirtyCount; 1693647Srdreslin@umich.edu 1702623SN/A uint8_t ®Data8(Addr daddr) { return *((uint8_t *)®s + daddr); } 1712623SN/A uint32_t ®Data32(Addr daddr) { return *(uint32_t *)®Data8(daddr); } 1722623SN/A uint64_t ®Data64(Addr daddr) { return *(uint64_t *)®Data8(daddr); } 1732623SN/A 1742623SN/A protected: 1756775SBrad.Beckmann@amd.com RxState rxState; 1766775SBrad.Beckmann@amd.com PacketFifo rxFifo; 1776775SBrad.Beckmann@amd.com PacketFifo::iterator rxFifoPtr; 1782623SN/A bool rxEmpty; 1792623SN/A bool rxLow; 1802623SN/A Addr rxDmaAddr; 1812623SN/A uint8_t *rxDmaData; 1822623SN/A unsigned rxDmaLen; 1832915Sktlim@umich.edu 1842915Sktlim@umich.edu TxState txState; 1856078Sgblack@eecs.umich.edu PacketFifo txFifo; 1863145Shsul@eecs.umich.edu bool txFull; 1872623SN/A EthPacketPtr txPacket; 1882623SN/A int txPacketOffset; 1892623SN/A int txPacketBytes; 1902623SN/A Addr txDmaAddr; 1912623SN/A uint8_t *txDmaData; 1922623SN/A int txDmaLen; 1932623SN/A 1942915Sktlim@umich.edu protected: 1952915Sktlim@umich.edu void reset(); 1966078Sgblack@eecs.umich.edu 1973145Shsul@eecs.umich.edu void rxKick(); 1982915Sktlim@umich.edu Tick rxKickTick; 1992915Sktlim@umich.edu typedef EventWrapper<Device, &Device::rxKick> RxKickEvent; 2002915Sktlim@umich.edu friend void RxKickEvent::process(); 2012915Sktlim@umich.edu 2022915Sktlim@umich.edu void txKick(); 2032915Sktlim@umich.edu Tick txKickTick; 2045220Ssaidi@eecs.umich.edu typedef EventWrapper<Device, &Device::txKick> TxKickEvent; 2055220Ssaidi@eecs.umich.edu friend void TxKickEvent::process(); 2065220Ssaidi@eecs.umich.edu 2074940Snate@binkert.org /** 2085220Ssaidi@eecs.umich.edu * Retransmit event 2093324Shsul@eecs.umich.edu */ 2105220Ssaidi@eecs.umich.edu void transmit(); 2115220Ssaidi@eecs.umich.edu void txEventTransmit() 2125606Snate@binkert.org { 2135606Snate@binkert.org transmit(); 2142915Sktlim@umich.edu if (txState == txFifoBlock) 2157897Shestness@cs.utexas.edu txKick(); 2162623SN/A } 2172623SN/A typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent; 2182623SN/A friend void TxEvent::process(); 2192798Sktlim@umich.edu TxEvent txEvent; 2202623SN/A 2215496Ssaidi@eecs.umich.edu void txDump() const; 2222798Sktlim@umich.edu void rxDump() const; 2232623SN/A 2242798Sktlim@umich.edu /** 2252623SN/A * receive address filter 2262623SN/A */ 2272623SN/A bool rxFilter(const EthPacketPtr &packet); 2282623SN/A 2292623SN/A/** 2302623SN/A * device configuration 2314192Sktlim@umich.edu */ 2322623SN/A void changeConfig(uint32_t newconfig); 2332623SN/A void command(uint32_t command); 2342623SN/A 2352680Sktlim@umich.edu/** 2362623SN/A * device ethernet interface 2376221Snate@binkert.org */ 2386221Snate@binkert.org public: 2392680Sktlim@umich.edu bool recvPacket(EthPacketPtr packet); 2402680Sktlim@umich.edu void transferDone(); 2412623SN/A virtual EtherInt *getEthPort(const std::string &if_name, int idx); 2425606Snate@binkert.org 2432623SN/A/** 2442623SN/A * DMA parameters 2452623SN/A */ 2463512Sktlim@umich.edu protected: 2473512Sktlim@umich.edu void rxDmaDone(); 2483512Sktlim@umich.edu friend class EventWrapper<Device, &Device::rxDmaDone>; 2495169Ssaidi@eecs.umich.edu EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent; 2505712Shsul@eecs.umich.edu 2515712Shsul@eecs.umich.edu void txDmaDone(); 2525712Shsul@eecs.umich.edu friend class EventWrapper<Device, &Device::txDmaDone>; 2532623SN/A EventWrapper<Device, &Device::txDmaDone> txDmaEvent; 2542623SN/A 2552623SN/A Tick dmaReadDelay; 2562623SN/A Tick dmaReadFactor; 2572623SN/A Tick dmaWriteDelay; 2582623SN/A Tick dmaWriteFactor; 2594940Snate@binkert.org 2604940Snate@binkert.org/** 2612623SN/A * Interrupt management 2622683Sktlim@umich.edu */ 2632623SN/A protected: 2642623SN/A void devIntrPost(uint32_t interrupts); 2652623SN/A void devIntrClear(uint32_t interrupts = Regs::Intr_All); 2662623SN/A void devIntrChangeMask(uint32_t newmask); 2672623SN/A 2685101Ssaidi@eecs.umich.edu/** 2693686Sktlim@umich.edu * Memory Interface 2703430Sgblack@eecs.umich.edu */ 2717823Ssteve.reinhardt@amd.com public: 2722623SN/A virtual Tick read(PacketPtr pkt); 2732623SN/A virtual Tick write(PacketPtr pkt); 2742623SN/A virtual void drainResume() M5_ATTR_OVERRIDE; 2752623SN/A 2762623SN/A void prepareIO(ContextID cpu, int index); 2772623SN/A void prepareRead(ContextID cpu, int index); 2782623SN/A void prepareWrite(ContextID cpu, int index); 2794940Snate@binkert.org // Fault iprRead(Addr daddr, ContextID cpu, uint64_t &result); 2804940Snate@binkert.org 2812623SN/A/** 2822683Sktlim@umich.edu * Statistics 2832623SN/A */ 2846043Sgblack@eecs.umich.edu private: 2856043Sgblack@eecs.umich.edu Stats::Scalar totalVnicDistance; 2866043Sgblack@eecs.umich.edu Stats::Scalar numVnicDistance; 2872623SN/A Stats::Scalar maxVnicDistance; 2882626SN/A Stats::Formula avgVnicDistance; 2892626SN/A 2902626SN/A int _maxVnicDistance; 2912626SN/A 2925606Snate@binkert.org public: 2932623SN/A virtual void regStats(); 2942623SN/A virtual void resetStats(); 2952623SN/A 2962623SN/A/** 2972623SN/A * Serialization stuff 2982623SN/A */ 2992623SN/A public: 3007520Sgblack@eecs.umich.edu void serializeOld(CheckpointOut &cp) M5_ATTR_OVERRIDE; 3017520Sgblack@eecs.umich.edu void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 3022623SN/A 3033169Sstever@eecs.umich.edu public: 3044870Sstever@eecs.umich.edu Device(const Params *p); 3052623SN/A ~Device(); 3062623SN/A}; 3072623SN/A 3082623SN/A/* 3092623SN/A * Ethernet Interface for an Ethernet Device 3104999Sgblack@eecs.umich.edu */ 3116227Snate@binkert.orgclass Interface : public EtherInt 3124999Sgblack@eecs.umich.edu{ 3137520Sgblack@eecs.umich.edu private: 3142623SN/A Device *dev; 3154999Sgblack@eecs.umich.edu 3164999Sgblack@eecs.umich.edu public: 3177520Sgblack@eecs.umich.edu Interface(const std::string &name, Device *d) 3184999Sgblack@eecs.umich.edu : EtherInt(name), dev(d) 3197520Sgblack@eecs.umich.edu { } 3207520Sgblack@eecs.umich.edu 3214999Sgblack@eecs.umich.edu virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); } 3224999Sgblack@eecs.umich.edu virtual void sendDone() { dev->transferDone(); } 3234999Sgblack@eecs.umich.edu}; 3247520Sgblack@eecs.umich.edu 3257720Sgblack@eecs.umich.edu} // namespace Sinic 3264999Sgblack@eecs.umich.edu 3274999Sgblack@eecs.umich.edu#endif // __DEV_SINIC_HH__ 3286023Snate@binkert.org