sinic.cc revision 2566 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cstdio>
30#include <deque>
31#include <limits>
32#include <string>
33
34#include "base/inet.hh"
35#include "cpu/exec_context.hh"
36#include "cpu/intr_control.hh"
37#include "dev/etherlink.hh"
38#include "dev/sinic.hh"
39#include "dev/pciconfigall.hh"
40#include "mem/packet.hh"
41#include "sim/builder.hh"
42#include "sim/debug.hh"
43#include "sim/eventq.hh"
44#include "sim/host.hh"
45#include "sim/stats.hh"
46#include "arch/vtophys.hh"
47
48using namespace Net;
49using namespace TheISA;
50
51namespace Sinic {
52
53const char *RxStateStrings[] =
54{
55    "rxIdle",
56    "rxFifoBlock",
57    "rxBeginCopy",
58    "rxCopy",
59    "rxCopyDone"
60};
61
62const char *TxStateStrings[] =
63{
64    "txIdle",
65    "txFifoBlock",
66    "txBeginCopy",
67    "txCopy",
68    "txCopyDone"
69};
70
71
72///////////////////////////////////////////////////////////////////////
73//
74// Sinic PCI Device
75//
76Base::Base(Params *p)
77    : PciDev(p), rxEnable(false), txEnable(false), clock(p->clock),
78      intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false),
79      cpuPendingIntr(false), intrEvent(0), interface(NULL)
80{
81}
82
83Device::Device(Params *p)
84    : Base(p), rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size),
85      rxKickTick(0), txKickTick(0),
86      txEvent(this), rxDmaEvent(this), txDmaEvent(this),
87      dmaReadDelay(p->dma_read_delay), dmaReadFactor(p->dma_read_factor),
88      dmaWriteDelay(p->dma_write_delay), dmaWriteFactor(p->dma_write_factor)
89{
90    reset();
91
92}
93
94Device::~Device()
95{}
96
97void
98Device::regStats()
99{
100    rxBytes
101        .name(name() + ".rxBytes")
102        .desc("Bytes Received")
103        .prereq(rxBytes)
104        ;
105
106    rxBandwidth
107        .name(name() + ".rxBandwidth")
108        .desc("Receive Bandwidth (bits/s)")
109        .precision(0)
110        .prereq(rxBytes)
111        ;
112
113    rxPackets
114        .name(name() + ".rxPackets")
115        .desc("Number of Packets Received")
116        .prereq(rxBytes)
117        ;
118
119    rxPacketRate
120        .name(name() + ".rxPPS")
121        .desc("Packet Reception Rate (packets/s)")
122        .precision(0)
123        .prereq(rxBytes)
124        ;
125
126    rxIpPackets
127        .name(name() + ".rxIpPackets")
128        .desc("Number of IP Packets Received")
129        .prereq(rxBytes)
130        ;
131
132    rxTcpPackets
133        .name(name() + ".rxTcpPackets")
134        .desc("Number of Packets Received")
135        .prereq(rxBytes)
136        ;
137
138    rxUdpPackets
139        .name(name() + ".rxUdpPackets")
140        .desc("Number of UDP Packets Received")
141        .prereq(rxBytes)
142        ;
143
144    rxIpChecksums
145        .name(name() + ".rxIpChecksums")
146        .desc("Number of rx IP Checksums done by device")
147        .precision(0)
148        .prereq(rxBytes)
149        ;
150
151    rxTcpChecksums
152        .name(name() + ".rxTcpChecksums")
153        .desc("Number of rx TCP Checksums done by device")
154        .precision(0)
155        .prereq(rxBytes)
156        ;
157
158    rxUdpChecksums
159        .name(name() + ".rxUdpChecksums")
160        .desc("Number of rx UDP Checksums done by device")
161        .precision(0)
162        .prereq(rxBytes)
163        ;
164
165    totBandwidth
166        .name(name() + ".totBandwidth")
167        .desc("Total Bandwidth (bits/s)")
168        .precision(0)
169        .prereq(totBytes)
170        ;
171
172    totPackets
173        .name(name() + ".totPackets")
174        .desc("Total Packets")
175        .precision(0)
176        .prereq(totBytes)
177        ;
178
179    totBytes
180        .name(name() + ".totBytes")
181        .desc("Total Bytes")
182        .precision(0)
183        .prereq(totBytes)
184        ;
185
186    totPacketRate
187        .name(name() + ".totPPS")
188        .desc("Total Tranmission Rate (packets/s)")
189        .precision(0)
190        .prereq(totBytes)
191        ;
192
193    txBytes
194        .name(name() + ".txBytes")
195        .desc("Bytes Transmitted")
196        .prereq(txBytes)
197        ;
198
199    txBandwidth
200        .name(name() + ".txBandwidth")
201        .desc("Transmit Bandwidth (bits/s)")
202        .precision(0)
203        .prereq(txBytes)
204        ;
205
206    txPackets
207        .name(name() + ".txPackets")
208        .desc("Number of Packets Transmitted")
209        .prereq(txBytes)
210        ;
211
212    txPacketRate
213        .name(name() + ".txPPS")
214        .desc("Packet Tranmission Rate (packets/s)")
215        .precision(0)
216        .prereq(txBytes)
217        ;
218
219    txIpPackets
220        .name(name() + ".txIpPackets")
221        .desc("Number of IP Packets Transmitted")
222        .prereq(txBytes)
223        ;
224
225    txTcpPackets
226        .name(name() + ".txTcpPackets")
227        .desc("Number of TCP Packets Transmitted")
228        .prereq(txBytes)
229        ;
230
231    txUdpPackets
232        .name(name() + ".txUdpPackets")
233        .desc("Number of Packets Transmitted")
234        .prereq(txBytes)
235        ;
236
237    txIpChecksums
238        .name(name() + ".txIpChecksums")
239        .desc("Number of tx IP Checksums done by device")
240        .precision(0)
241        .prereq(txBytes)
242        ;
243
244    txTcpChecksums
245        .name(name() + ".txTcpChecksums")
246        .desc("Number of tx TCP Checksums done by device")
247        .precision(0)
248        .prereq(txBytes)
249        ;
250
251    txUdpChecksums
252        .name(name() + ".txUdpChecksums")
253        .desc("Number of tx UDP Checksums done by device")
254        .precision(0)
255        .prereq(txBytes)
256        ;
257
258    txBandwidth = txBytes * Stats::constant(8) / simSeconds;
259    rxBandwidth = rxBytes * Stats::constant(8) / simSeconds;
260    totBandwidth = txBandwidth + rxBandwidth;
261    totBytes = txBytes + rxBytes;
262    totPackets = txPackets + rxPackets;
263    txPacketRate = txPackets / simSeconds;
264    rxPacketRate = rxPackets / simSeconds;
265}
266
267void
268Device::prepareIO(int cpu, int index)
269{
270    int size = virtualRegs.size();
271    if (index < size)
272        return;
273
274    virtualRegs.resize(index + 1);
275    for (int i = size; i <= index; ++i)
276        virtualRegs[i].rxPacket = rxFifo.end();
277}
278
279void
280Device::prepareRead(int cpu, int index)
281{
282    using namespace Regs;
283    prepareIO(cpu, index);
284
285    VirtualReg &vnic = virtualRegs[index];
286
287    // update rx registers
288    uint64_t rxdone = vnic.RxDone;
289    rxdone = set_RxDone_Packets(rxdone, rxFifo.packets());
290    regs.RxData = vnic.RxData;
291    regs.RxDone = rxdone;
292    regs.RxWait = rxdone;
293
294    // update tx regsiters
295    uint64_t txdone = vnic.TxDone;
296    txdone = set_TxDone_Packets(txdone, txFifo.packets());
297    txdone = set_TxDone_Full(txdone, txFifo.avail() < regs.TxMaxCopy);
298    txdone = set_TxDone_Low(txdone, txFifo.size() < regs.TxFifoMark);
299    regs.TxData = vnic.TxData;
300    regs.TxDone = txdone;
301    regs.TxWait = txdone;
302}
303
304void
305Device::prepareWrite(int cpu, int index)
306{
307    prepareIO(cpu, index);
308}
309
310/**
311 * I/O read of device register
312 */
313Tick
314Device::read(Packet &pkt)
315{
316    assert(config.command & PCI_CMD_MSE);
317    assert(pkt.addr >= BARAddrs[0] && pkt.size < BARSize[0]);
318
319    int cpu = pkt.req->getCpuNum();
320    Addr daddr = pkt.addr - BARAddrs[0];
321    Addr index = daddr >> Regs::VirtualShift;
322    Addr raddr = daddr & Regs::VirtualMask;
323
324    pkt.time = curTick + pioDelay;
325    pkt.allocate();
326
327    if (!regValid(raddr))
328        panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d",
329                cpu, daddr, pkt.addr, pkt.size);
330
331    const Regs::Info &info = regInfo(raddr);
332    if (!info.read)
333        panic("reading %s (write only): cpu=%d da=%#x pa=%#x size=%d",
334                info.name, cpu, daddr, pkt.addr, pkt.size);
335
336    if (pkt.size != info.size)
337        panic("invalid size for reg %s: cpu=%d da=%#x pa=%#x size=%d",
338                info.name, cpu, daddr, pkt.addr, pkt.size);
339
340    prepareRead(cpu, index);
341
342    uint64_t value = 0;
343    if (pkt.size == 4) {
344        uint32_t reg = regData32(raddr);
345        pkt.set(reg);
346        value = reg;
347    }
348
349    if (pkt.size == 8) {
350        uint64_t reg = regData64(raddr);
351        pkt.set(reg);
352        value = reg;
353    }
354
355    DPRINTF(EthernetPIO,
356            "read %s cpu=%d da=%#x pa=%#x size=%d val=%#x\n",
357            info.name, cpu, daddr, pkt.addr, pkt.size, value);
358
359    // reading the interrupt status register has the side effect of
360    // clearing it
361    if (raddr == Regs::IntrStatus)
362        devIntrClear();
363
364    return pioDelay;
365}
366
367/**
368 * IPR read of device register
369
370    Fault
371Device::iprRead(Addr daddr, int cpu, uint64_t &result)
372{
373    if (!regValid(daddr))
374        panic("invalid address: da=%#x", daddr);
375
376    const Regs::Info &info = regInfo(daddr);
377    if (!info.read)
378        panic("reading %s (write only): cpu=%d da=%#x", info.name, cpu, daddr);
379
380    DPRINTF(EthernetPIO, "IPR read %s: cpu=%d da=%#x\n",
381            info.name, cpu, daddr);
382
383    prepareRead(cpu, 0);
384
385    if (info.size == 4)
386        result = regData32(daddr);
387
388    if (info.size == 8)
389        result = regData64(daddr);
390
391    DPRINTF(EthernetPIO, "IPR read %s: cpu=%s da=%#x val=%#x\n",
392            info.name, cpu, result);
393
394    return NoFault;
395}
396*/
397/**
398 * I/O write of device register
399 */
400Tick
401Device::write(Packet &pkt)
402{
403    assert(config.command & PCI_CMD_MSE);
404    assert(pkt.addr >= BARAddrs[0] && pkt.size < BARSize[0]);
405
406    int cpu = pkt.req->getCpuNum();
407    Addr daddr = pkt.addr - BARAddrs[0];
408    Addr index = daddr >> Regs::VirtualShift;
409    Addr raddr = daddr & Regs::VirtualMask;
410
411    pkt.time = curTick + pioDelay;
412
413    if (!regValid(raddr))
414        panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d",
415                cpu, daddr, pkt.addr, pkt.size);
416
417    const Regs::Info &info = regInfo(raddr);
418    if (!info.write)
419        panic("write %s (read only): cpu=%d da=%#x pa=%#x size=%d",
420                info.name, cpu, daddr, pkt.addr, pkt.size);
421
422    if (pkt.size != info.size)
423        panic("invalid size for reg %s: cpu=%d da=%#x pa=%#x size=%d",
424                info.name, cpu, daddr, pkt.addr, pkt.size);
425
426    VirtualReg &vnic = virtualRegs[index];
427
428    DPRINTF(EthernetPIO,
429            "write %s: cpu=%d val=%#x da=%#x pa=%#x size=%d\n",
430            info.name, cpu, info.size == 4 ? pkt.get<uint32_t>() :
431            pkt.get<uint64_t>(), daddr, pkt.addr, pkt.size);
432
433    prepareWrite(cpu, index);
434
435    switch (raddr) {
436      case Regs::Config:
437        changeConfig(pkt.get<uint32_t>());
438        break;
439
440      case Regs::Command:
441        command(pkt.get<uint32_t>());
442        break;
443
444      case Regs::IntrStatus:
445        devIntrClear(regs.IntrStatus & pkt.get<uint32_t>());
446        break;
447
448      case Regs::IntrMask:
449        devIntrChangeMask(pkt.get<uint32_t>());
450        break;
451
452      case Regs::RxData:
453        if (Regs::get_RxDone_Busy(vnic.RxDone))
454            panic("receive machine busy with another request! rxState=%s",
455                  RxStateStrings[rxState]);
456
457        vnic.RxDone = Regs::RxDone_Busy;
458        vnic.RxData = pkt.get<uint64_t>();
459        rxList.push_back(index);
460        if (rxEnable && rxState == rxIdle) {
461            rxState = rxFifoBlock;
462            rxKick();
463        }
464        break;
465
466      case Regs::TxData:
467        if (Regs::get_TxDone_Busy(vnic.TxDone))
468            panic("transmit machine busy with another request! txState=%s",
469                  TxStateStrings[txState]);
470
471        vnic.TxDone = Regs::TxDone_Busy;
472        vnic.TxData = pkt.get<uint64_t>();
473        if (txList.empty() || txList.front() != index)
474            txList.push_back(index);
475        if (txEnable && txState == txIdle && txList.front() == index) {
476            txState = txFifoBlock;
477            txKick();
478        }
479        break;
480    }
481
482    return pioDelay;
483}
484
485void
486Device::devIntrPost(uint32_t interrupts)
487{
488    if ((interrupts & Regs::Intr_Res))
489        panic("Cannot set a reserved interrupt");
490
491    regs.IntrStatus |= interrupts;
492
493    DPRINTF(EthernetIntr,
494            "interrupt written to intStatus: intr=%#x status=%#x mask=%#x\n",
495            interrupts, regs.IntrStatus, regs.IntrMask);
496
497    interrupts = regs.IntrStatus & regs.IntrMask;
498
499    // Intr_RxHigh is special, we only signal it if we've emptied the fifo
500    // and then filled it above the high watermark
501    if (rxEmpty)
502        rxEmpty = false;
503    else
504        interrupts &= ~Regs::Intr_RxHigh;
505
506    // Intr_TxLow is special, we only signal it if we've filled up the fifo
507    // and then dropped below the low watermark
508    if (txFull)
509        txFull = false;
510    else
511        interrupts &= ~Regs::Intr_TxLow;
512
513    if (interrupts) {
514        Tick when = curTick;
515        if ((interrupts & Regs::Intr_NoDelay) == 0)
516            when += intrDelay;
517        cpuIntrPost(when);
518    }
519}
520
521void
522Device::devIntrClear(uint32_t interrupts)
523{
524    if ((interrupts & Regs::Intr_Res))
525        panic("Cannot clear a reserved interrupt");
526
527    regs.IntrStatus &= ~interrupts;
528
529    DPRINTF(EthernetIntr,
530            "interrupt cleared from intStatus: intr=%x status=%x mask=%x\n",
531            interrupts, regs.IntrStatus, regs.IntrMask);
532
533    if (!(regs.IntrStatus & regs.IntrMask))
534        cpuIntrClear();
535}
536
537void
538Device::devIntrChangeMask(uint32_t newmask)
539{
540    if (regs.IntrMask == newmask)
541        return;
542
543    regs.IntrMask = newmask;
544
545    DPRINTF(EthernetIntr,
546            "interrupt mask changed: intStatus=%x intMask=%x masked=%x\n",
547            regs.IntrStatus, regs.IntrMask, regs.IntrStatus & regs.IntrMask);
548
549    if (regs.IntrStatus & regs.IntrMask)
550        cpuIntrPost(curTick);
551    else
552        cpuIntrClear();
553}
554
555void
556Base::cpuIntrPost(Tick when)
557{
558    // If the interrupt you want to post is later than an interrupt
559    // already scheduled, just let it post in the coming one and don't
560    // schedule another.
561    // HOWEVER, must be sure that the scheduled intrTick is in the
562    // future (this was formerly the source of a bug)
563    /**
564     * @todo this warning should be removed and the intrTick code should
565     * be fixed.
566     */
567    assert(when >= curTick);
568    assert(intrTick >= curTick || intrTick == 0);
569    if (!cpuIntrEnable) {
570        DPRINTF(EthernetIntr, "interrupts not enabled.\n",
571                intrTick);
572        return;
573    }
574
575    if (when > intrTick && intrTick != 0) {
576        DPRINTF(EthernetIntr, "don't need to schedule event...intrTick=%d\n",
577                intrTick);
578        return;
579    }
580
581    intrTick = when;
582    if (intrTick < curTick) {
583        debug_break();
584        intrTick = curTick;
585    }
586
587    DPRINTF(EthernetIntr, "going to schedule an interrupt for intrTick=%d\n",
588            intrTick);
589
590    if (intrEvent)
591        intrEvent->squash();
592    intrEvent = new IntrEvent(this, true);
593    intrEvent->schedule(intrTick);
594}
595
596void
597Base::cpuInterrupt()
598{
599    assert(intrTick == curTick);
600
601    // Whether or not there's a pending interrupt, we don't care about
602    // it anymore
603    intrEvent = 0;
604    intrTick = 0;
605
606    // Don't send an interrupt if there's already one
607    if (cpuPendingIntr) {
608        DPRINTF(EthernetIntr,
609                "would send an interrupt now, but there's already pending\n");
610    } else {
611        // Send interrupt
612        cpuPendingIntr = true;
613
614        DPRINTF(EthernetIntr, "posting interrupt\n");
615        intrPost();
616    }
617}
618
619void
620Base::cpuIntrClear()
621{
622    if (!cpuPendingIntr)
623        return;
624
625    if (intrEvent) {
626        intrEvent->squash();
627        intrEvent = 0;
628    }
629
630    intrTick = 0;
631
632    cpuPendingIntr = false;
633
634    DPRINTF(EthernetIntr, "clearing cchip interrupt\n");
635    intrClear();
636}
637
638bool
639Base::cpuIntrPending() const
640{ return cpuPendingIntr; }
641
642void
643Device::changeConfig(uint32_t newconf)
644{
645    uint32_t changed = regs.Config ^ newconf;
646    if (!changed)
647        return;
648
649    regs.Config = newconf;
650
651    if ((changed & Regs::Config_IntEn)) {
652        cpuIntrEnable = regs.Config & Regs::Config_IntEn;
653        if (cpuIntrEnable) {
654            if (regs.IntrStatus & regs.IntrMask)
655                cpuIntrPost(curTick);
656        } else {
657            cpuIntrClear();
658        }
659    }
660
661    if ((changed & Regs::Config_TxEn)) {
662        txEnable = regs.Config & Regs::Config_TxEn;
663        if (txEnable)
664            txKick();
665    }
666
667    if ((changed & Regs::Config_RxEn)) {
668        rxEnable = regs.Config & Regs::Config_RxEn;
669        if (rxEnable)
670            rxKick();
671    }
672}
673
674void
675Device::command(uint32_t command)
676{
677    if (command & Regs::Command_Intr)
678        devIntrPost(Regs::Intr_Soft);
679
680    if (command & Regs::Command_Reset)
681        reset();
682}
683
684void
685Device::reset()
686{
687    using namespace Regs;
688
689    memset(&regs, 0, sizeof(regs));
690
691    regs.Config = 0;
692    if (params()->rx_thread)
693        regs.Config |= Config_RxThread;
694    if (params()->tx_thread)
695        regs.Config |= Config_TxThread;
696    if (params()->rss)
697        regs.Config |= Config_RSS;
698    regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow;
699    regs.RxMaxCopy = params()->rx_max_copy;
700    regs.TxMaxCopy = params()->tx_max_copy;
701    regs.RxMaxIntr = params()->rx_max_intr;
702    regs.RxFifoSize = params()->rx_fifo_size;
703    regs.TxFifoSize = params()->tx_fifo_size;
704    regs.RxFifoMark = params()->rx_fifo_threshold;
705    regs.TxFifoMark = params()->tx_fifo_threshold;
706    regs.HwAddr = params()->eaddr;
707
708    rxList.clear();
709    txList.clear();
710
711    rxState = rxIdle;
712    txState = txIdle;
713
714    rxFifo.clear();
715    rxFifoPtr = rxFifo.end();
716    txFifo.clear();
717    rxEmpty = false;
718    txFull = false;
719
720    int size = virtualRegs.size();
721    virtualRegs.clear();
722    virtualRegs.resize(size);
723    for (int i = 0; i < size; ++i)
724        virtualRegs[i].rxPacket = rxFifo.end();
725}
726
727void
728Device::rxDmaDone()
729{
730    assert(rxState == rxCopy);
731    rxState = rxCopyDone;
732    DPRINTF(EthernetDMA, "rx dma write paddr=%#x len=%d\n",
733            rxDmaAddr, rxDmaLen);
734    DDUMP(EthernetData, rxDmaData, rxDmaLen);
735
736    // If the transmit state machine  has a pending DMA, let it go first
737    if (txState == txBeginCopy)
738        txKick();
739
740    rxKick();
741}
742
743void
744Device::rxKick()
745{
746    VirtualReg *vnic;
747
748    DPRINTF(EthernetSM, "receive kick rxState=%s (rxFifo.size=%d)\n",
749            RxStateStrings[rxState], rxFifo.size());
750
751    if (rxKickTick > curTick) {
752        DPRINTF(EthernetSM, "receive kick exiting, can't run till %d\n",
753                rxKickTick);
754        return;
755    }
756
757  next:
758    if (rxState == rxIdle)
759        goto exit;
760
761    assert(!rxList.empty());
762    vnic = &virtualRegs[rxList.front()];
763
764    DPRINTF(EthernetSM, "processing rxState=%s for virtual nic %d\n",
765            RxStateStrings[rxState], rxList.front());
766
767    switch (rxState) {
768      case rxFifoBlock:
769        if (vnic->rxPacket != rxFifo.end()) {
770            rxState = rxBeginCopy;
771            break;
772        }
773
774        if (rxFifoPtr == rxFifo.end()) {
775            DPRINTF(EthernetSM, "receive waiting for data.  Nothing to do.\n");
776            goto exit;
777        }
778
779        assert(!rxFifo.empty());
780
781        // Grab a new packet from the fifo.
782        vnic->rxPacket = rxFifoPtr++;
783        vnic->rxPacketOffset = 0;
784        vnic->rxPacketBytes = (*vnic->rxPacket)->length;
785        assert(vnic->rxPacketBytes);
786
787        vnic->rxDoneData = 0;
788        /* scope for variables */ {
789            IpPtr ip(*vnic->rxPacket);
790            if (ip) {
791                vnic->rxDoneData |= Regs::RxDone_IpPacket;
792                rxIpChecksums++;
793                if (cksum(ip) != 0) {
794                    DPRINTF(EthernetCksum, "Rx IP Checksum Error\n");
795                    vnic->rxDoneData |= Regs::RxDone_IpError;
796                }
797                TcpPtr tcp(ip);
798                UdpPtr udp(ip);
799                if (tcp) {
800                    vnic->rxDoneData |= Regs::RxDone_TcpPacket;
801                    rxTcpChecksums++;
802                    if (cksum(tcp) != 0) {
803                        DPRINTF(EthernetCksum, "Rx TCP Checksum Error\n");
804                        vnic->rxDoneData |= Regs::RxDone_TcpError;
805                    }
806                } else if (udp) {
807                    vnic->rxDoneData |= Regs::RxDone_UdpPacket;
808                    rxUdpChecksums++;
809                    if (cksum(udp) != 0) {
810                        DPRINTF(EthernetCksum, "Rx UDP Checksum Error\n");
811                        vnic->rxDoneData |= Regs::RxDone_UdpError;
812                    }
813                }
814            }
815        }
816        rxState = rxBeginCopy;
817        break;
818
819      case rxBeginCopy:
820        if (dmaPending())
821            goto exit;
822
823        rxDmaAddr = params()->platform->pciToDma(
824                Regs::get_RxData_Addr(vnic->RxData));
825        rxDmaLen = std::min<int>(Regs::get_RxData_Len(vnic->RxData),
826                            vnic->rxPacketBytes);
827        rxDmaData = (*vnic->rxPacket)->data + vnic->rxPacketOffset;
828        rxState = rxCopy;
829
830        dmaWrite(rxDmaAddr, rxDmaLen, &rxDmaEvent, rxDmaData);
831        break;
832
833      case rxCopy:
834        DPRINTF(EthernetSM, "receive machine still copying\n");
835        goto exit;
836
837      case rxCopyDone:
838        vnic->RxDone = vnic->rxDoneData | rxDmaLen;
839        vnic->RxDone |= Regs::RxDone_Complete;
840
841        if (vnic->rxPacketBytes == rxDmaLen) {
842            DPRINTF(EthernetSM, "rxKick: packet complete on vnic %d\n",
843                    rxList.front());
844            rxFifo.remove(vnic->rxPacket);
845            vnic->rxPacket = rxFifo.end();
846        } else {
847            vnic->RxDone |= Regs::RxDone_More;
848            vnic->rxPacketBytes -= rxDmaLen;
849            vnic->rxPacketOffset += rxDmaLen;
850            DPRINTF(EthernetSM,
851                    "rxKick: packet not complete on vnic %d: %d bytes left\n",
852                    rxList.front(), vnic->rxPacketBytes);
853        }
854
855        rxList.pop_front();
856        rxState = rxList.empty() ? rxIdle : rxFifoBlock;
857
858        if (rxFifo.empty()) {
859            devIntrPost(Regs::Intr_RxEmpty);
860            rxEmpty = true;
861        }
862
863        devIntrPost(Regs::Intr_RxDMA);
864        break;
865
866      default:
867        panic("Invalid rxState!");
868    }
869
870    DPRINTF(EthernetSM, "entering next rxState=%s\n",
871            RxStateStrings[rxState]);
872
873    goto next;
874
875  exit:
876    /**
877     * @todo do we want to schedule a future kick?
878     */
879    DPRINTF(EthernetSM, "rx state machine exited rxState=%s\n",
880            RxStateStrings[rxState]);
881}
882
883void
884Device::txDmaDone()
885{
886    assert(txState == txCopy);
887    txState = txCopyDone;
888    DPRINTF(EthernetDMA, "tx dma read paddr=%#x len=%d\n",
889            txDmaAddr, txDmaLen);
890    DDUMP(EthernetData, txDmaData, txDmaLen);
891
892    // If the receive state machine  has a pending DMA, let it go first
893    if (rxState == rxBeginCopy)
894        rxKick();
895
896    txKick();
897}
898
899void
900Device::transmit()
901{
902    if (txFifo.empty()) {
903        DPRINTF(Ethernet, "nothing to transmit\n");
904        return;
905    }
906
907    uint32_t interrupts;
908    EthPacketPtr packet = txFifo.front();
909    if (!interface->sendPacket(packet)) {
910        DPRINTF(Ethernet, "Packet Transmit: failed txFifo available %d\n",
911                txFifo.avail());
912        goto reschedule;
913    }
914
915    txFifo.pop();
916#if TRACING_ON
917    if (DTRACE(Ethernet)) {
918        IpPtr ip(packet);
919        if (ip) {
920            DPRINTF(Ethernet, "ID is %d\n", ip->id());
921            TcpPtr tcp(ip);
922            if (tcp) {
923                DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n",
924                        tcp->sport(), tcp->dport());
925            }
926        }
927    }
928#endif
929
930    DDUMP(EthernetData, packet->data, packet->length);
931    txBytes += packet->length;
932    txPackets++;
933
934    DPRINTF(Ethernet, "Packet Transmit: successful txFifo Available %d\n",
935            txFifo.avail());
936
937    interrupts = Regs::Intr_TxPacket;
938    if (txFifo.size() < regs.TxFifoMark)
939        interrupts |= Regs::Intr_TxLow;
940    devIntrPost(interrupts);
941
942  reschedule:
943   if (!txFifo.empty() && !txEvent.scheduled()) {
944       DPRINTF(Ethernet, "reschedule transmit\n");
945       txEvent.schedule(curTick + retryTime);
946   }
947}
948
949void
950Device::txKick()
951{
952    VirtualReg *vnic;
953    DPRINTF(EthernetSM, "transmit kick txState=%s (txFifo.size=%d)\n",
954            TxStateStrings[txState], txFifo.size());
955
956    if (txKickTick > curTick) {
957        DPRINTF(EthernetSM, "transmit kick exiting, can't run till %d\n",
958                txKickTick);
959        return;
960    }
961
962  next:
963    if (txState == txIdle)
964        goto exit;
965
966    assert(!txList.empty());
967    vnic = &virtualRegs[txList.front()];
968
969    switch (txState) {
970      case txFifoBlock:
971        assert(Regs::get_TxDone_Busy(vnic->TxData));
972        if (!txPacket) {
973            // Grab a new packet from the fifo.
974            txPacket = new EthPacketData(16384);
975            txPacketOffset = 0;
976        }
977
978        if (txFifo.avail() - txPacket->length <
979            Regs::get_TxData_Len(vnic->TxData)) {
980            DPRINTF(EthernetSM, "transmit fifo full.  Nothing to do.\n");
981            goto exit;
982        }
983
984        txState = txBeginCopy;
985        break;
986
987      case txBeginCopy:
988        if (dmaPending())
989            goto exit;
990
991        txDmaAddr = params()->platform->pciToDma(
992                Regs::get_TxData_Addr(vnic->TxData));
993        txDmaLen = Regs::get_TxData_Len(vnic->TxData);
994        txDmaData = txPacket->data + txPacketOffset;
995        txState = txCopy;
996
997        dmaRead(txDmaAddr, txDmaLen, &txDmaEvent, txDmaData);
998        break;
999
1000      case txCopy:
1001        DPRINTF(EthernetSM, "transmit machine still copying\n");
1002        goto exit;
1003
1004      case txCopyDone:
1005        vnic->TxDone = txDmaLen | Regs::TxDone_Complete;
1006        txPacket->length += txDmaLen;
1007        if ((vnic->TxData & Regs::TxData_More)) {
1008            txPacketOffset += txDmaLen;
1009            txState = txIdle;
1010            devIntrPost(Regs::Intr_TxDMA);
1011            break;
1012        }
1013
1014        assert(txPacket->length <= txFifo.avail());
1015        if ((vnic->TxData & Regs::TxData_Checksum)) {
1016            IpPtr ip(txPacket);
1017            if (ip) {
1018                TcpPtr tcp(ip);
1019                if (tcp) {
1020                    tcp->sum(0);
1021                    tcp->sum(cksum(tcp));
1022                    txTcpChecksums++;
1023                }
1024
1025                UdpPtr udp(ip);
1026                if (udp) {
1027                    udp->sum(0);
1028                    udp->sum(cksum(udp));
1029                    txUdpChecksums++;
1030                }
1031
1032                ip->sum(0);
1033                ip->sum(cksum(ip));
1034                txIpChecksums++;
1035            }
1036        }
1037
1038        txFifo.push(txPacket);
1039        if (txFifo.avail() < regs.TxMaxCopy) {
1040            devIntrPost(Regs::Intr_TxFull);
1041            txFull = true;
1042        }
1043        txPacket = 0;
1044        transmit();
1045        txList.pop_front();
1046        txState = txList.empty() ? txIdle : txFifoBlock;
1047        devIntrPost(Regs::Intr_TxDMA);
1048        break;
1049
1050      default:
1051        panic("Invalid txState!");
1052    }
1053
1054    DPRINTF(EthernetSM, "entering next txState=%s\n",
1055            TxStateStrings[txState]);
1056
1057    goto next;
1058
1059  exit:
1060    /**
1061     * @todo do we want to schedule a future kick?
1062     */
1063    DPRINTF(EthernetSM, "tx state machine exited txState=%s\n",
1064            TxStateStrings[txState]);
1065}
1066
1067void
1068Device::transferDone()
1069{
1070    if (txFifo.empty()) {
1071        DPRINTF(Ethernet, "transfer complete: txFifo empty...nothing to do\n");
1072        return;
1073    }
1074
1075    DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
1076
1077    if (txEvent.scheduled())
1078        txEvent.reschedule(curTick + cycles(1));
1079    else
1080        txEvent.schedule(curTick + cycles(1));
1081}
1082
1083bool
1084Device::rxFilter(const EthPacketPtr &packet)
1085{
1086    if (!Regs::get_Config_Filter(regs.Config))
1087        return false;
1088
1089    panic("receive filter not implemented\n");
1090    bool drop = true;
1091
1092#if 0
1093    string type;
1094
1095    EthHdr *eth = packet->eth();
1096    if (eth->unicast()) {
1097        // If we're accepting all unicast addresses
1098        if (acceptUnicast)
1099            drop = false;
1100
1101        // If we make a perfect match
1102        if (acceptPerfect && params->eaddr == eth.dst())
1103            drop = false;
1104
1105        if (acceptArp && eth->type() == ETH_TYPE_ARP)
1106            drop = false;
1107
1108    } else if (eth->broadcast()) {
1109        // if we're accepting broadcasts
1110        if (acceptBroadcast)
1111            drop = false;
1112
1113    } else if (eth->multicast()) {
1114        // if we're accepting all multicasts
1115        if (acceptMulticast)
1116            drop = false;
1117
1118    }
1119
1120    if (drop) {
1121        DPRINTF(Ethernet, "rxFilter drop\n");
1122        DDUMP(EthernetData, packet->data, packet->length);
1123    }
1124#endif
1125    return drop;
1126}
1127
1128bool
1129Device::recvPacket(EthPacketPtr packet)
1130{
1131    rxBytes += packet->length;
1132    rxPackets++;
1133
1134    DPRINTF(Ethernet, "Receiving packet from wire, rxFifo Available is %d\n",
1135            rxFifo.avail());
1136
1137    if (!rxEnable) {
1138        DPRINTF(Ethernet, "receive disabled...packet dropped\n");
1139        return true;
1140    }
1141
1142    if (rxFilter(packet)) {
1143        DPRINTF(Ethernet, "packet filtered...dropped\n");
1144        return true;
1145    }
1146
1147    if (rxFifo.size() >= regs.RxFifoMark)
1148        devIntrPost(Regs::Intr_RxHigh);
1149
1150    if (!rxFifo.push(packet)) {
1151        DPRINTF(Ethernet,
1152                "packet will not fit in receive buffer...packet dropped\n");
1153        return false;
1154    }
1155
1156    // If we were at the last element, back up one ot go to the new
1157    // last element of the list.
1158    if (rxFifoPtr == rxFifo.end())
1159        --rxFifoPtr;
1160
1161    devIntrPost(Regs::Intr_RxPacket);
1162    rxKick();
1163    return true;
1164}
1165
1166//=====================================================================
1167//
1168//
1169void
1170Base::serialize(std::ostream &os)
1171{
1172    // Serialize the PciDev base class
1173    PciDev::serialize(os);
1174
1175    SERIALIZE_SCALAR(rxEnable);
1176    SERIALIZE_SCALAR(txEnable);
1177    SERIALIZE_SCALAR(cpuIntrEnable);
1178
1179    /*
1180     * Keep track of pending interrupt status.
1181     */
1182    SERIALIZE_SCALAR(intrTick);
1183    SERIALIZE_SCALAR(cpuPendingIntr);
1184    Tick intrEventTick = 0;
1185    if (intrEvent)
1186        intrEventTick = intrEvent->when();
1187    SERIALIZE_SCALAR(intrEventTick);
1188}
1189
1190void
1191Base::unserialize(Checkpoint *cp, const std::string &section)
1192{
1193    // Unserialize the PciDev base class
1194    PciDev::unserialize(cp, section);
1195
1196    UNSERIALIZE_SCALAR(rxEnable);
1197    UNSERIALIZE_SCALAR(txEnable);
1198    UNSERIALIZE_SCALAR(cpuIntrEnable);
1199
1200    /*
1201     * Keep track of pending interrupt status.
1202     */
1203    UNSERIALIZE_SCALAR(intrTick);
1204    UNSERIALIZE_SCALAR(cpuPendingIntr);
1205    Tick intrEventTick;
1206    UNSERIALIZE_SCALAR(intrEventTick);
1207    if (intrEventTick) {
1208        intrEvent = new IntrEvent(this, true);
1209        intrEvent->schedule(intrEventTick);
1210    }
1211}
1212
1213void
1214Device::serialize(std::ostream &os)
1215{
1216    // Serialize the PciDev base class
1217    Base::serialize(os);
1218
1219    if (rxState == rxCopy)
1220        panic("can't serialize with an in flight dma request rxState=%s",
1221              RxStateStrings[rxState]);
1222
1223    if (txState == txCopy)
1224        panic("can't serialize with an in flight dma request txState=%s",
1225              TxStateStrings[txState]);
1226
1227    /*
1228     * Serialize the device registers
1229     */
1230    SERIALIZE_SCALAR(regs.Config);
1231    SERIALIZE_SCALAR(regs.IntrStatus);
1232    SERIALIZE_SCALAR(regs.IntrMask);
1233    SERIALIZE_SCALAR(regs.RxMaxCopy);
1234    SERIALIZE_SCALAR(regs.TxMaxCopy);
1235    SERIALIZE_SCALAR(regs.RxMaxIntr);
1236    SERIALIZE_SCALAR(regs.RxData);
1237    SERIALIZE_SCALAR(regs.RxDone);
1238    SERIALIZE_SCALAR(regs.TxData);
1239    SERIALIZE_SCALAR(regs.TxDone);
1240
1241    /*
1242     * Serialize the virtual nic state
1243     */
1244    int virtualRegsSize = virtualRegs.size();
1245    SERIALIZE_SCALAR(virtualRegsSize);
1246    for (int i = 0; i < virtualRegsSize; ++i) {
1247        VirtualReg *vnic = &virtualRegs[i];
1248
1249        std::string reg = csprintf("vnic%d", i);
1250        paramOut(os, reg + ".RxData", vnic->RxData);
1251        paramOut(os, reg + ".RxDone", vnic->RxDone);
1252        paramOut(os, reg + ".TxData", vnic->TxData);
1253        paramOut(os, reg + ".TxDone", vnic->TxDone);
1254
1255        PacketFifo::iterator rxFifoPtr;
1256
1257        bool rxPacketExists = vnic->rxPacket != rxFifo.end();
1258        paramOut(os, reg + ".rxPacketExists", rxPacketExists);
1259        if (rxPacketExists) {
1260            int rxPacket = 0;
1261            PacketFifo::iterator i = rxFifo.begin();
1262            while (i != vnic->rxPacket) {
1263                assert(i != rxFifo.end());
1264                ++i;
1265                ++rxPacket;
1266            }
1267
1268            paramOut(os, reg + ".rxPacket", rxPacket);
1269            paramOut(os, reg + ".rxPacketOffset", vnic->rxPacketOffset);
1270            paramOut(os, reg + ".rxPacketBytes", vnic->rxPacketBytes);
1271        }
1272        paramOut(os, reg + ".rxDoneData", vnic->rxDoneData);
1273    }
1274
1275    VirtualList::iterator i, end;
1276    int count;
1277
1278    int rxListSize = rxList.size();
1279    SERIALIZE_SCALAR(rxListSize);
1280    for (count = 0, i = rxList.begin(), end = rxList.end(); i != end; ++i)
1281        paramOut(os, csprintf("rxList%d", count++), *i);
1282
1283    int txListSize = txList.size();
1284    SERIALIZE_SCALAR(txListSize);
1285    for (count = 0, i = txList.begin(), end = txList.end(); i != end; ++i)
1286        paramOut(os, csprintf("txList%d", count++), *i);
1287
1288    /*
1289     * Serialize rx state machine
1290     */
1291    int rxState = this->rxState;
1292    SERIALIZE_SCALAR(rxState);
1293    SERIALIZE_SCALAR(rxEmpty);
1294    rxFifo.serialize("rxFifo", os);
1295
1296    /*
1297     * Serialize tx state machine
1298     */
1299    int txState = this->txState;
1300    SERIALIZE_SCALAR(txState);
1301    SERIALIZE_SCALAR(txFull);
1302    txFifo.serialize("txFifo", os);
1303    bool txPacketExists = txPacket;
1304    SERIALIZE_SCALAR(txPacketExists);
1305    if (txPacketExists) {
1306        txPacket->serialize("txPacket", os);
1307        SERIALIZE_SCALAR(txPacketOffset);
1308        SERIALIZE_SCALAR(txPacketBytes);
1309    }
1310
1311    /*
1312     * If there's a pending transmit, store the time so we can
1313     * reschedule it later
1314     */
1315    Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick : 0;
1316    SERIALIZE_SCALAR(transmitTick);
1317}
1318
1319void
1320Device::unserialize(Checkpoint *cp, const std::string &section)
1321{
1322    // Unserialize the PciDev base class
1323    Base::unserialize(cp, section);
1324
1325    /*
1326     * Unserialize the device registers
1327     */
1328    UNSERIALIZE_SCALAR(regs.Config);
1329    UNSERIALIZE_SCALAR(regs.IntrStatus);
1330    UNSERIALIZE_SCALAR(regs.IntrMask);
1331    UNSERIALIZE_SCALAR(regs.RxMaxCopy);
1332    UNSERIALIZE_SCALAR(regs.TxMaxCopy);
1333    UNSERIALIZE_SCALAR(regs.RxMaxIntr);
1334    UNSERIALIZE_SCALAR(regs.RxData);
1335    UNSERIALIZE_SCALAR(regs.RxDone);
1336    UNSERIALIZE_SCALAR(regs.TxData);
1337    UNSERIALIZE_SCALAR(regs.TxDone);
1338
1339    int rxListSize;
1340    UNSERIALIZE_SCALAR(rxListSize);
1341    rxList.clear();
1342    for (int i = 0; i < rxListSize; ++i) {
1343        int value;
1344        paramIn(cp, section, csprintf("rxList%d", i), value);
1345        rxList.push_back(value);
1346    }
1347
1348    int txListSize;
1349    UNSERIALIZE_SCALAR(txListSize);
1350    txList.clear();
1351    for (int i = 0; i < txListSize; ++i) {
1352        int value;
1353        paramIn(cp, section, csprintf("txList%d", i), value);
1354        txList.push_back(value);
1355    }
1356
1357    /*
1358     * Unserialize rx state machine
1359     */
1360    int rxState;
1361    UNSERIALIZE_SCALAR(rxState);
1362    UNSERIALIZE_SCALAR(rxEmpty);
1363    this->rxState = (RxState) rxState;
1364    rxFifo.unserialize("rxFifo", cp, section);
1365
1366    /*
1367     * Unserialize tx state machine
1368     */
1369    int txState;
1370    UNSERIALIZE_SCALAR(txState);
1371    UNSERIALIZE_SCALAR(txFull);
1372    this->txState = (TxState) txState;
1373    txFifo.unserialize("txFifo", cp, section);
1374    bool txPacketExists;
1375    UNSERIALIZE_SCALAR(txPacketExists);
1376    txPacket = 0;
1377    if (txPacketExists) {
1378        txPacket = new EthPacketData(16384);
1379        txPacket->unserialize("txPacket", cp, section);
1380        UNSERIALIZE_SCALAR(txPacketOffset);
1381        UNSERIALIZE_SCALAR(txPacketBytes);
1382    }
1383
1384    /*
1385     * unserialize the virtual nic registers/state
1386     *
1387     * this must be done after the unserialization of the rxFifo
1388     * because the packet iterators depend on the fifo being populated
1389     */
1390    int virtualRegsSize;
1391    UNSERIALIZE_SCALAR(virtualRegsSize);
1392    virtualRegs.clear();
1393    virtualRegs.resize(virtualRegsSize);
1394    for (int i = 0; i < virtualRegsSize; ++i) {
1395        VirtualReg *vnic = &virtualRegs[i];
1396        std::string reg = csprintf("vnic%d", i);
1397
1398        paramIn(cp, section, reg + ".RxData", vnic->RxData);
1399        paramIn(cp, section, reg + ".RxDone", vnic->RxDone);
1400        paramIn(cp, section, reg + ".TxData", vnic->TxData);
1401        paramIn(cp, section, reg + ".TxDone", vnic->TxDone);
1402
1403        bool rxPacketExists;
1404        paramIn(cp, section, reg + ".rxPacketExists", rxPacketExists);
1405        if (rxPacketExists) {
1406            int rxPacket;
1407            paramIn(cp, section, reg + ".rxPacket", rxPacket);
1408            vnic->rxPacket = rxFifo.begin();
1409            while (rxPacket--)
1410                ++vnic->rxPacket;
1411
1412            paramIn(cp, section, reg + ".rxPacketOffset",
1413                    vnic->rxPacketOffset);
1414            paramIn(cp, section, reg + ".rxPacketBytes", vnic->rxPacketBytes);
1415        } else {
1416            vnic->rxPacket = rxFifo.end();
1417        }
1418        paramIn(cp, section, reg + ".rxDoneData", vnic->rxDoneData);
1419    }
1420
1421    /*
1422     * If there's a pending transmit, reschedule it now
1423     */
1424    Tick transmitTick;
1425    UNSERIALIZE_SCALAR(transmitTick);
1426    if (transmitTick)
1427        txEvent.schedule(curTick + transmitTick);
1428
1429    pioPort->sendStatusChange(Port::RangeChange);
1430
1431}
1432
1433
1434BEGIN_DECLARE_SIM_OBJECT_PARAMS(Interface)
1435
1436    SimObjectParam<EtherInt *> peer;
1437    SimObjectParam<Device *> device;
1438
1439END_DECLARE_SIM_OBJECT_PARAMS(Interface)
1440
1441BEGIN_INIT_SIM_OBJECT_PARAMS(Interface)
1442
1443    INIT_PARAM_DFLT(peer, "peer interface", NULL),
1444    INIT_PARAM(device, "Ethernet device of this interface")
1445
1446END_INIT_SIM_OBJECT_PARAMS(Interface)
1447
1448CREATE_SIM_OBJECT(Interface)
1449{
1450    Interface *dev_int = new Interface(getInstanceName(), device);
1451
1452    EtherInt *p = (EtherInt *)peer;
1453    if (p) {
1454        dev_int->setPeer(p);
1455        p->setPeer(dev_int);
1456    }
1457
1458    return dev_int;
1459}
1460
1461REGISTER_SIM_OBJECT("SinicInt", Interface)
1462
1463
1464BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
1465
1466
1467    SimObjectParam<System *> system;
1468    SimObjectParam<Platform *> platform;
1469    SimObjectParam<PciConfigAll *> configspace;
1470    SimObjectParam<PciConfigData *> configdata;
1471    Param<uint32_t> pci_bus;
1472    Param<uint32_t> pci_dev;
1473    Param<uint32_t> pci_func;
1474    Param<Tick> pio_latency;
1475    Param<Tick> intr_delay;
1476
1477    Param<Tick> clock;
1478    Param<Tick> dma_read_delay;
1479    Param<Tick> dma_read_factor;
1480    Param<Tick> dma_write_delay;
1481    Param<Tick> dma_write_factor;
1482
1483    Param<Tick> rx_delay;
1484    Param<Tick> tx_delay;
1485    Param<uint32_t> rx_max_copy;
1486    Param<uint32_t> tx_max_copy;
1487    Param<uint32_t> rx_max_intr;
1488    Param<uint32_t> rx_fifo_size;
1489    Param<uint32_t> tx_fifo_size;
1490    Param<uint32_t> rx_fifo_threshold;
1491    Param<uint32_t> tx_fifo_threshold;
1492
1493    Param<bool> rx_filter;
1494    Param<std::string> hardware_address;
1495    Param<bool> rx_thread;
1496    Param<bool> tx_thread;
1497    Param<bool> rss;
1498
1499END_DECLARE_SIM_OBJECT_PARAMS(Device)
1500
1501BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
1502
1503
1504    INIT_PARAM(system, "System pointer"),
1505    INIT_PARAM(platform, "Platform pointer"),
1506    INIT_PARAM(configspace, "PCI Configspace"),
1507    INIT_PARAM(configdata, "PCI Config data"),
1508    INIT_PARAM(pci_bus, "PCI bus ID"),
1509    INIT_PARAM(pci_dev, "PCI device number"),
1510    INIT_PARAM(pci_func, "PCI function code"),
1511    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
1512    INIT_PARAM(intr_delay, "Interrupt Delay"),
1513    INIT_PARAM(clock, "State machine cycle time"),
1514
1515    INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
1516    INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
1517    INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
1518    INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
1519
1520    INIT_PARAM(rx_delay, "Receive Delay"),
1521    INIT_PARAM(tx_delay, "Transmit Delay"),
1522    INIT_PARAM(rx_max_copy, "rx max copy"),
1523    INIT_PARAM(tx_max_copy, "rx max copy"),
1524    INIT_PARAM(rx_max_intr, "rx max intr"),
1525    INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
1526    INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
1527    INIT_PARAM(rx_fifo_threshold, "max size in bytes of rxFifo"),
1528    INIT_PARAM(tx_fifo_threshold, "max size in bytes of txFifo"),
1529
1530    INIT_PARAM(rx_filter, "Enable Receive Filter"),
1531    INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
1532    INIT_PARAM(rx_thread, ""),
1533    INIT_PARAM(tx_thread, ""),
1534    INIT_PARAM(rss, "")
1535
1536END_INIT_SIM_OBJECT_PARAMS(Device)
1537
1538
1539CREATE_SIM_OBJECT(Device)
1540{
1541    Device::Params *params = new Device::Params;
1542    params->name = getInstanceName();
1543    params->platform = platform;
1544    params->system = system;
1545    params->configSpace = configspace;
1546    params->configData = configdata;
1547    params->busNum = pci_bus;
1548    params->deviceNum = pci_dev;
1549    params->functionNum = pci_func;
1550    params->pio_delay = pio_latency;
1551    params->intr_delay = intr_delay;
1552    params->clock = clock;
1553
1554    params->dma_read_delay = dma_read_delay;
1555    params->dma_read_factor = dma_read_factor;
1556    params->dma_write_delay = dma_write_delay;
1557    params->dma_write_factor = dma_write_factor;
1558
1559    params->tx_delay = tx_delay;
1560    params->rx_delay = rx_delay;
1561    params->rx_max_copy = rx_max_copy;
1562    params->tx_max_copy = tx_max_copy;
1563    params->rx_max_intr = rx_max_intr;
1564    params->rx_fifo_size = rx_fifo_size;
1565    params->tx_fifo_size = tx_fifo_size;
1566    params->rx_fifo_threshold = rx_fifo_threshold;
1567    params->tx_fifo_threshold = tx_fifo_threshold;
1568
1569    params->rx_filter = rx_filter;
1570    params->eaddr = hardware_address;
1571    params->rx_thread = rx_thread;
1572    params->tx_thread = tx_thread;
1573    params->rss = rss;
1574
1575    return new Device(params);
1576}
1577
1578REGISTER_SIM_OBJECT("Sinic", Device)
1579
1580/* namespace Sinic */ }
1581