sinic.cc revision 10913
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 */ 30 31#include <deque> 32#include <limits> 33#include <string> 34 35#ifdef SINIC_VTOPHYS 36#include "arch/vtophys.hh" 37#endif 38#include "base/compiler.hh" 39#include "base/debug.hh" 40#include "base/inet.hh" 41#include "base/types.hh" 42#include "config/the_isa.hh" 43#include "debug/EthernetAll.hh" 44#include "dev/etherlink.hh" 45#include "dev/sinic.hh" 46#include "mem/packet.hh" 47#include "mem/packet_access.hh" 48#include "sim/eventq.hh" 49#include "sim/stats.hh" 50 51using namespace std; 52using namespace Net; 53using namespace TheISA; 54 55namespace Sinic { 56 57const char *RxStateStrings[] = 58{ 59 "rxIdle", 60 "rxFifoBlock", 61 "rxBeginCopy", 62 "rxCopy", 63 "rxCopyDone" 64}; 65 66const char *TxStateStrings[] = 67{ 68 "txIdle", 69 "txFifoBlock", 70 "txBeginCopy", 71 "txCopy", 72 "txCopyDone" 73}; 74 75 76/////////////////////////////////////////////////////////////////////// 77// 78// Sinic PCI Device 79// 80Base::Base(const Params *p) 81 : EtherDevBase(p), rxEnable(false), txEnable(false), 82 intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false), 83 cpuPendingIntr(false), intrEvent(0), interface(NULL) 84{ 85} 86 87Device::Device(const Params *p) 88 : Base(p), rxUnique(0), txUnique(0), 89 virtualRegs(p->virtual_count < 1 ? 1 : p->virtual_count), 90 rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), 91 rxKickTick(0), txKickTick(0), 92 txEvent(this), rxDmaEvent(this), txDmaEvent(this), 93 dmaReadDelay(p->dma_read_delay), dmaReadFactor(p->dma_read_factor), 94 dmaWriteDelay(p->dma_write_delay), dmaWriteFactor(p->dma_write_factor) 95{ 96 interface = new Interface(name() + ".int0", this); 97 reset(); 98 99} 100 101Device::~Device() 102{} 103 104void 105Device::regStats() 106{ 107 Base::regStats(); 108 109 _maxVnicDistance = 0; 110 111 maxVnicDistance 112 .name(name() + ".maxVnicDistance") 113 .desc("maximum vnic distance") 114 ; 115 116 totalVnicDistance 117 .name(name() + ".totalVnicDistance") 118 .desc("total vnic distance") 119 ; 120 numVnicDistance 121 .name(name() + ".numVnicDistance") 122 .desc("number of vnic distance measurements") 123 ; 124 125 avgVnicDistance 126 .name(name() + ".avgVnicDistance") 127 .desc("average vnic distance") 128 ; 129 130 avgVnicDistance = totalVnicDistance / numVnicDistance; 131} 132 133void 134Device::resetStats() 135{ 136 Base::resetStats(); 137 138 _maxVnicDistance = 0; 139} 140 141EtherInt* 142Device::getEthPort(const std::string &if_name, int idx) 143{ 144 if (if_name == "interface") { 145 if (interface->getPeer()) 146 panic("interface already connected to\n"); 147 148 return interface; 149 } 150 return NULL; 151} 152 153 154void 155Device::prepareIO(int cpu, int index) 156{ 157 int size = virtualRegs.size(); 158 if (index > size) 159 panic("Trying to access a vnic that doesn't exist %d > %d\n", 160 index, size); 161} 162 163//add stats for head of line blocking 164//add stats for average fifo length 165//add stats for average number of vnics busy 166 167void 168Device::prepareRead(int cpu, int index) 169{ 170 using namespace Regs; 171 prepareIO(cpu, index); 172 173 VirtualReg &vnic = virtualRegs[index]; 174 175 // update rx registers 176 uint64_t rxdone = vnic.RxDone; 177 rxdone = set_RxDone_Packets(rxdone, rxFifo.countPacketsAfter(rxFifoPtr)); 178 rxdone = set_RxDone_Empty(rxdone, rxFifo.empty()); 179 rxdone = set_RxDone_High(rxdone, rxFifo.size() > regs.RxFifoHigh); 180 rxdone = set_RxDone_NotHigh(rxdone, rxLow); 181 regs.RxData = vnic.RxData; 182 regs.RxDone = rxdone; 183 regs.RxWait = rxdone; 184 185 // update tx regsiters 186 uint64_t txdone = vnic.TxDone; 187 txdone = set_TxDone_Packets(txdone, txFifo.packets()); 188 txdone = set_TxDone_Full(txdone, txFifo.avail() < regs.TxMaxCopy); 189 txdone = set_TxDone_Low(txdone, txFifo.size() < regs.TxFifoLow); 190 regs.TxData = vnic.TxData; 191 regs.TxDone = txdone; 192 regs.TxWait = txdone; 193 194 int head = 0xffff; 195 196 if (!rxFifo.empty()) { 197 int vnic = rxFifo.begin()->priv; 198 if (vnic != -1 && virtualRegs[vnic].rxPacketOffset > 0) 199 head = vnic; 200 } 201 202 regs.RxStatus = set_RxStatus_Head(regs.RxStatus, head); 203 regs.RxStatus = set_RxStatus_Busy(regs.RxStatus, rxBusyCount); 204 regs.RxStatus = set_RxStatus_Mapped(regs.RxStatus, rxMappedCount); 205 regs.RxStatus = set_RxStatus_Dirty(regs.RxStatus, rxDirtyCount); 206} 207 208void 209Device::prepareWrite(int cpu, int index) 210{ 211 prepareIO(cpu, index); 212} 213 214/** 215 * I/O read of device register 216 */ 217Tick 218Device::read(PacketPtr pkt) 219{ 220 assert(config.command & PCI_CMD_MSE); 221 assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]); 222 223 int cpu = pkt->req->contextId(); 224 Addr daddr = pkt->getAddr() - BARAddrs[0]; 225 Addr index = daddr >> Regs::VirtualShift; 226 Addr raddr = daddr & Regs::VirtualMask; 227 228 if (!regValid(raddr)) 229 panic("invalid register: cpu=%d vnic=%d da=%#x pa=%#x size=%d", 230 cpu, index, daddr, pkt->getAddr(), pkt->getSize()); 231 232 const Regs::Info &info = regInfo(raddr); 233 if (!info.read) 234 panic("read %s (write only): " 235 "cpu=%d vnic=%d da=%#x pa=%#x size=%d", 236 info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize()); 237 238 panic("read %s (invalid size): " 239 "cpu=%d vnic=%d da=%#x pa=%#x size=%d", 240 info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize()); 241 242 prepareRead(cpu, index); 243 244 uint64_t value M5_VAR_USED = 0; 245 if (pkt->getSize() == 4) { 246 uint32_t reg = regData32(raddr); 247 pkt->set(reg); 248 value = reg; 249 } 250 251 if (pkt->getSize() == 8) { 252 uint64_t reg = regData64(raddr); 253 pkt->set(reg); 254 value = reg; 255 } 256 257 DPRINTF(EthernetPIO, 258 "read %s: cpu=%d vnic=%d da=%#x pa=%#x size=%d val=%#x\n", 259 info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize(), value); 260 261 // reading the interrupt status register has the side effect of 262 // clearing it 263 if (raddr == Regs::IntrStatus) 264 devIntrClear(); 265 266 return pioDelay; 267} 268 269/** 270 * IPR read of device register 271 272 Fault 273Device::iprRead(Addr daddr, int cpu, uint64_t &result) 274{ 275 if (!regValid(daddr)) 276 panic("invalid address: da=%#x", daddr); 277 278 const Regs::Info &info = regInfo(daddr); 279 if (!info.read) 280 panic("reading %s (write only): cpu=%d da=%#x", info.name, cpu, daddr); 281 282 DPRINTF(EthernetPIO, "IPR read %s: cpu=%d da=%#x\n", 283 info.name, cpu, daddr); 284 285 prepareRead(cpu, 0); 286 287 if (info.size == 4) 288 result = regData32(daddr); 289 290 if (info.size == 8) 291 result = regData64(daddr); 292 293 DPRINTF(EthernetPIO, "IPR read %s: cpu=%s da=%#x val=%#x\n", 294 info.name, cpu, result); 295 296 return NoFault; 297} 298*/ 299/** 300 * I/O write of device register 301 */ 302Tick 303Device::write(PacketPtr pkt) 304{ 305 assert(config.command & PCI_CMD_MSE); 306 assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]); 307 308 int cpu = pkt->req->contextId(); 309 Addr daddr = pkt->getAddr() - BARAddrs[0]; 310 Addr index = daddr >> Regs::VirtualShift; 311 Addr raddr = daddr & Regs::VirtualMask; 312 313 if (!regValid(raddr)) 314 panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d", 315 cpu, daddr, pkt->getAddr(), pkt->getSize()); 316 317 const Regs::Info &info = regInfo(raddr); 318 if (!info.write) 319 panic("write %s (read only): " 320 "cpu=%d vnic=%d da=%#x pa=%#x size=%d", 321 info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize()); 322 323 if (pkt->getSize() != info.size) 324 panic("write %s (invalid size): " 325 "cpu=%d vnic=%d da=%#x pa=%#x size=%d", 326 info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize()); 327 328 VirtualReg &vnic = virtualRegs[index]; 329 330 DPRINTF(EthernetPIO, 331 "write %s vnic %d: cpu=%d val=%#x da=%#x pa=%#x size=%d\n", 332 info.name, index, cpu, info.size == 4 ? pkt->get<uint32_t>() : 333 pkt->get<uint64_t>(), daddr, pkt->getAddr(), pkt->getSize()); 334 335 prepareWrite(cpu, index); 336 337 switch (raddr) { 338 case Regs::Config: 339 changeConfig(pkt->get<uint32_t>()); 340 break; 341 342 case Regs::Command: 343 command(pkt->get<uint32_t>()); 344 break; 345 346 case Regs::IntrStatus: 347 devIntrClear(regs.IntrStatus & pkt->get<uint32_t>()); 348 break; 349 350 case Regs::IntrMask: 351 devIntrChangeMask(pkt->get<uint32_t>()); 352 break; 353 354 case Regs::RxData: 355 if (Regs::get_RxDone_Busy(vnic.RxDone)) 356 panic("receive machine busy with another request! rxState=%s", 357 RxStateStrings[rxState]); 358 359 vnic.rxUnique = rxUnique++; 360 vnic.RxDone = Regs::RxDone_Busy; 361 vnic.RxData = pkt->get<uint64_t>(); 362 rxBusyCount++; 363 364 if (Regs::get_RxData_Vaddr(pkt->get<uint64_t>())) { 365 panic("vtophys not implemented in newmem"); 366#ifdef SINIC_VTOPHYS 367 Addr vaddr = Regs::get_RxData_Addr(reg64); 368 Addr paddr = vtophys(req->xc, vaddr); 369 DPRINTF(EthernetPIO, "write RxData vnic %d (rxunique %d): " 370 "vaddr=%#x, paddr=%#x\n", 371 index, vnic.rxUnique, vaddr, paddr); 372 373 vnic.RxData = Regs::set_RxData_Addr(vnic.RxData, paddr); 374#endif 375 } else { 376 DPRINTF(EthernetPIO, "write RxData vnic %d (rxunique %d)\n", 377 index, vnic.rxUnique); 378 } 379 380 if (vnic.rxIndex == rxFifo.end()) { 381 DPRINTF(EthernetPIO, "request new packet...appending to rxList\n"); 382 rxList.push_back(index); 383 } else { 384 DPRINTF(EthernetPIO, "packet exists...appending to rxBusy\n"); 385 rxBusy.push_back(index); 386 } 387 388 if (rxEnable && (rxState == rxIdle || rxState == rxFifoBlock)) { 389 rxState = rxFifoBlock; 390 rxKick(); 391 } 392 break; 393 394 case Regs::TxData: 395 if (Regs::get_TxDone_Busy(vnic.TxDone)) 396 panic("transmit machine busy with another request! txState=%s", 397 TxStateStrings[txState]); 398 399 vnic.txUnique = txUnique++; 400 vnic.TxDone = Regs::TxDone_Busy; 401 402 if (Regs::get_TxData_Vaddr(pkt->get<uint64_t>())) { 403 panic("vtophys won't work here in newmem.\n"); 404#ifdef SINIC_VTOPHYS 405 Addr vaddr = Regs::get_TxData_Addr(reg64); 406 Addr paddr = vtophys(req->xc, vaddr); 407 DPRINTF(EthernetPIO, "write TxData vnic %d (txunique %d): " 408 "vaddr=%#x, paddr=%#x\n", 409 index, vnic.txUnique, vaddr, paddr); 410 411 vnic.TxData = Regs::set_TxData_Addr(vnic.TxData, paddr); 412#endif 413 } else { 414 DPRINTF(EthernetPIO, "write TxData vnic %d (txunique %d)\n", 415 index, vnic.txUnique); 416 } 417 418 if (txList.empty() || txList.front() != index) 419 txList.push_back(index); 420 if (txEnable && txState == txIdle && txList.front() == index) { 421 txState = txFifoBlock; 422 txKick(); 423 } 424 break; 425 } 426 427 return pioDelay; 428} 429 430void 431Device::devIntrPost(uint32_t interrupts) 432{ 433 if ((interrupts & Regs::Intr_Res)) 434 panic("Cannot set a reserved interrupt"); 435 436 regs.IntrStatus |= interrupts; 437 438 DPRINTF(EthernetIntr, 439 "interrupt written to intStatus: intr=%#x status=%#x mask=%#x\n", 440 interrupts, regs.IntrStatus, regs.IntrMask); 441 442 interrupts = regs.IntrStatus & regs.IntrMask; 443 444 // Intr_RxHigh is special, we only signal it if we've emptied the fifo 445 // and then filled it above the high watermark 446 if (rxEmpty) 447 rxEmpty = false; 448 else 449 interrupts &= ~Regs::Intr_RxHigh; 450 451 // Intr_TxLow is special, we only signal it if we've filled up the fifo 452 // and then dropped below the low watermark 453 if (txFull) 454 txFull = false; 455 else 456 interrupts &= ~Regs::Intr_TxLow; 457 458 if (interrupts) { 459 Tick when = curTick(); 460 if ((interrupts & Regs::Intr_NoDelay) == 0) 461 when += intrDelay; 462 cpuIntrPost(when); 463 } 464} 465 466void 467Device::devIntrClear(uint32_t interrupts) 468{ 469 if ((interrupts & Regs::Intr_Res)) 470 panic("Cannot clear a reserved interrupt"); 471 472 regs.IntrStatus &= ~interrupts; 473 474 DPRINTF(EthernetIntr, 475 "interrupt cleared from intStatus: intr=%x status=%x mask=%x\n", 476 interrupts, regs.IntrStatus, regs.IntrMask); 477 478 if (!(regs.IntrStatus & regs.IntrMask)) 479 cpuIntrClear(); 480} 481 482void 483Device::devIntrChangeMask(uint32_t newmask) 484{ 485 if (regs.IntrMask == newmask) 486 return; 487 488 regs.IntrMask = newmask; 489 490 DPRINTF(EthernetIntr, 491 "interrupt mask changed: intStatus=%x intMask=%x masked=%x\n", 492 regs.IntrStatus, regs.IntrMask, regs.IntrStatus & regs.IntrMask); 493 494 if (regs.IntrStatus & regs.IntrMask) 495 cpuIntrPost(curTick()); 496 else 497 cpuIntrClear(); 498} 499 500void 501Base::cpuIntrPost(Tick when) 502{ 503 // If the interrupt you want to post is later than an interrupt 504 // already scheduled, just let it post in the coming one and don't 505 // schedule another. 506 // HOWEVER, must be sure that the scheduled intrTick is in the 507 // future (this was formerly the source of a bug) 508 /** 509 * @todo this warning should be removed and the intrTick code should 510 * be fixed. 511 */ 512 assert(when >= curTick()); 513 assert(intrTick >= curTick() || intrTick == 0); 514 if (!cpuIntrEnable) { 515 DPRINTF(EthernetIntr, "interrupts not enabled.\n", 516 intrTick); 517 return; 518 } 519 520 if (when > intrTick && intrTick != 0) { 521 DPRINTF(EthernetIntr, "don't need to schedule event...intrTick=%d\n", 522 intrTick); 523 return; 524 } 525 526 intrTick = when; 527 if (intrTick < curTick()) { 528 Debug::breakpoint(); 529 intrTick = curTick(); 530 } 531 532 DPRINTF(EthernetIntr, "going to schedule an interrupt for intrTick=%d\n", 533 intrTick); 534 535 if (intrEvent) 536 intrEvent->squash(); 537 intrEvent = new IntrEvent(this, true); 538 schedule(intrEvent, intrTick); 539} 540 541void 542Base::cpuInterrupt() 543{ 544 assert(intrTick == curTick()); 545 546 // Whether or not there's a pending interrupt, we don't care about 547 // it anymore 548 intrEvent = 0; 549 intrTick = 0; 550 551 // Don't send an interrupt if there's already one 552 if (cpuPendingIntr) { 553 DPRINTF(EthernetIntr, 554 "would send an interrupt now, but there's already pending\n"); 555 } else { 556 // Send interrupt 557 cpuPendingIntr = true; 558 559 DPRINTF(EthernetIntr, "posting interrupt\n"); 560 intrPost(); 561 } 562} 563 564void 565Base::cpuIntrClear() 566{ 567 if (!cpuPendingIntr) 568 return; 569 570 if (intrEvent) { 571 intrEvent->squash(); 572 intrEvent = 0; 573 } 574 575 intrTick = 0; 576 577 cpuPendingIntr = false; 578 579 DPRINTF(EthernetIntr, "clearing cchip interrupt\n"); 580 intrClear(); 581} 582 583bool 584Base::cpuIntrPending() const 585{ return cpuPendingIntr; } 586 587void 588Device::changeConfig(uint32_t newconf) 589{ 590 uint32_t changed = regs.Config ^ newconf; 591 if (!changed) 592 return; 593 594 regs.Config = newconf; 595 596 if ((changed & Regs::Config_IntEn)) { 597 cpuIntrEnable = regs.Config & Regs::Config_IntEn; 598 if (cpuIntrEnable) { 599 if (regs.IntrStatus & regs.IntrMask) 600 cpuIntrPost(curTick()); 601 } else { 602 cpuIntrClear(); 603 } 604 } 605 606 if ((changed & Regs::Config_TxEn)) { 607 txEnable = regs.Config & Regs::Config_TxEn; 608 if (txEnable) 609 txKick(); 610 } 611 612 if ((changed & Regs::Config_RxEn)) { 613 rxEnable = regs.Config & Regs::Config_RxEn; 614 if (rxEnable) 615 rxKick(); 616 } 617} 618 619void 620Device::command(uint32_t command) 621{ 622 if (command & Regs::Command_Intr) 623 devIntrPost(Regs::Intr_Soft); 624 625 if (command & Regs::Command_Reset) 626 reset(); 627} 628 629void 630Device::reset() 631{ 632 using namespace Regs; 633 634 memset(®s, 0, sizeof(regs)); 635 636 regs.Config = 0; 637 if (params()->rx_thread) 638 regs.Config |= Config_RxThread; 639 if (params()->tx_thread) 640 regs.Config |= Config_TxThread; 641 if (params()->rss) 642 regs.Config |= Config_RSS; 643 if (params()->zero_copy) 644 regs.Config |= Config_ZeroCopy; 645 if (params()->delay_copy) 646 regs.Config |= Config_DelayCopy; 647 if (params()->virtual_addr) 648 regs.Config |= Config_Vaddr; 649 650 if (params()->delay_copy && params()->zero_copy) 651 panic("Can't delay copy and zero copy"); 652 653 regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow; 654 regs.RxMaxCopy = params()->rx_max_copy; 655 regs.TxMaxCopy = params()->tx_max_copy; 656 regs.ZeroCopySize = params()->zero_copy_size; 657 regs.ZeroCopyMark = params()->zero_copy_threshold; 658 regs.VirtualCount = params()->virtual_count; 659 regs.RxMaxIntr = params()->rx_max_intr; 660 regs.RxFifoSize = params()->rx_fifo_size; 661 regs.TxFifoSize = params()->tx_fifo_size; 662 regs.RxFifoLow = params()->rx_fifo_low_mark; 663 regs.TxFifoLow = params()->tx_fifo_threshold; 664 regs.RxFifoHigh = params()->rx_fifo_threshold; 665 regs.TxFifoHigh = params()->tx_fifo_high_mark; 666 regs.HwAddr = params()->hardware_address; 667 668 if (regs.RxMaxCopy < regs.ZeroCopyMark) 669 panic("Must be able to copy at least as many bytes as the threshold"); 670 671 if (regs.ZeroCopySize >= regs.ZeroCopyMark) 672 panic("The number of bytes to copy must be less than the threshold"); 673 674 rxList.clear(); 675 rxBusy.clear(); 676 rxActive = -1; 677 txList.clear(); 678 rxBusyCount = 0; 679 rxDirtyCount = 0; 680 rxMappedCount = 0; 681 682 rxState = rxIdle; 683 txState = txIdle; 684 685 rxFifo.clear(); 686 rxFifoPtr = rxFifo.end(); 687 txFifo.clear(); 688 rxEmpty = false; 689 rxLow = true; 690 txFull = false; 691 692 int size = virtualRegs.size(); 693 virtualRegs.clear(); 694 virtualRegs.resize(size); 695 for (int i = 0; i < size; ++i) 696 virtualRegs[i].rxIndex = rxFifo.end(); 697} 698 699void 700Device::rxDmaDone() 701{ 702 assert(rxState == rxCopy); 703 rxState = rxCopyDone; 704 DPRINTF(EthernetDMA, "end rx dma write paddr=%#x len=%d\n", 705 rxDmaAddr, rxDmaLen); 706 DDUMP(EthernetData, rxDmaData, rxDmaLen); 707 708 // If the transmit state machine has a pending DMA, let it go first 709 if (txState == txBeginCopy) 710 txKick(); 711 712 rxKick(); 713} 714 715void 716Device::rxKick() 717{ 718 VirtualReg *vnic = NULL; 719 720 DPRINTF(EthernetSM, "rxKick: rxState=%s (rxFifo.size=%d)\n", 721 RxStateStrings[rxState], rxFifo.size()); 722 723 if (rxKickTick > curTick()) { 724 DPRINTF(EthernetSM, "rxKick: exiting, can't run till %d\n", 725 rxKickTick); 726 return; 727 } 728 729 next: 730 rxFifo.check(); 731 if (rxState == rxIdle) 732 goto exit; 733 734 if (rxActive == -1) { 735 if (rxState != rxFifoBlock) 736 panic("no active vnic while in state %s", RxStateStrings[rxState]); 737 738 DPRINTF(EthernetSM, "processing rxState=%s\n", 739 RxStateStrings[rxState]); 740 } else { 741 vnic = &virtualRegs[rxActive]; 742 DPRINTF(EthernetSM, 743 "processing rxState=%s for vnic %d (rxunique %d)\n", 744 RxStateStrings[rxState], rxActive, vnic->rxUnique); 745 } 746 747 switch (rxState) { 748 case rxFifoBlock: 749 if (DTRACE(EthernetSM)) { 750 PacketFifo::iterator end = rxFifo.end(); 751 int size = virtualRegs.size(); 752 for (int i = 0; i < size; ++i) { 753 VirtualReg *vn = &virtualRegs[i]; 754 bool busy = Regs::get_RxDone_Busy(vn->RxDone); 755 if (vn->rxIndex != end) { 756#ifndef NDEBUG 757 bool dirty = vn->rxPacketOffset > 0; 758 const char *status; 759 760 if (busy && dirty) 761 status = "busy,dirty"; 762 else if (busy) 763 status = "busy"; 764 else if (dirty) 765 status = "dirty"; 766 else 767 status = "mapped"; 768 769 DPRINTF(EthernetSM, 770 "vnic %d %s (rxunique %d), packet %d, slack %d\n", 771 i, status, vn->rxUnique, 772 rxFifo.countPacketsBefore(vn->rxIndex), 773 vn->rxIndex->slack); 774#endif 775 } else if (busy) { 776 DPRINTF(EthernetSM, "vnic %d unmapped (rxunique %d)\n", 777 i, vn->rxUnique); 778 } 779 } 780 } 781 782 if (!rxBusy.empty()) { 783 rxActive = rxBusy.front(); 784 rxBusy.pop_front(); 785 vnic = &virtualRegs[rxActive]; 786 787 if (vnic->rxIndex == rxFifo.end()) 788 panic("continuing vnic without packet\n"); 789 790 DPRINTF(EthernetSM, 791 "continue processing for vnic %d (rxunique %d)\n", 792 rxActive, vnic->rxUnique); 793 794 rxState = rxBeginCopy; 795 796 int vnic_distance = rxFifo.countPacketsBefore(vnic->rxIndex); 797 totalVnicDistance += vnic_distance; 798 numVnicDistance += 1; 799 if (vnic_distance > _maxVnicDistance) { 800 maxVnicDistance = vnic_distance; 801 _maxVnicDistance = vnic_distance; 802 } 803 804 break; 805 } 806 807 if (rxFifoPtr == rxFifo.end()) { 808 DPRINTF(EthernetSM, "receive waiting for data. Nothing to do.\n"); 809 goto exit; 810 } 811 812 if (rxList.empty()) 813 panic("Not idle, but nothing to do!"); 814 815 assert(!rxFifo.empty()); 816 817 rxActive = rxList.front(); 818 rxList.pop_front(); 819 vnic = &virtualRegs[rxActive]; 820 821 DPRINTF(EthernetSM, 822 "processing new packet for vnic %d (rxunique %d)\n", 823 rxActive, vnic->rxUnique); 824 825 // Grab a new packet from the fifo. 826 vnic->rxIndex = rxFifoPtr++; 827 vnic->rxIndex->priv = rxActive; 828 vnic->rxPacketOffset = 0; 829 vnic->rxPacketBytes = vnic->rxIndex->packet->length; 830 assert(vnic->rxPacketBytes); 831 rxMappedCount++; 832 833 vnic->rxDoneData = 0; 834 /* scope for variables */ { 835 IpPtr ip(vnic->rxIndex->packet); 836 if (ip) { 837 DPRINTF(Ethernet, "ID is %d\n", ip->id()); 838 vnic->rxDoneData |= Regs::RxDone_IpPacket; 839 rxIpChecksums++; 840 if (cksum(ip) != 0) { 841 DPRINTF(EthernetCksum, "Rx IP Checksum Error\n"); 842 vnic->rxDoneData |= Regs::RxDone_IpError; 843 } 844 TcpPtr tcp(ip); 845 UdpPtr udp(ip); 846 if (tcp) { 847 DPRINTF(Ethernet, 848 "Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n", 849 tcp->sport(), tcp->dport(), tcp->seq(), 850 tcp->ack()); 851 vnic->rxDoneData |= Regs::RxDone_TcpPacket; 852 rxTcpChecksums++; 853 if (cksum(tcp) != 0) { 854 DPRINTF(EthernetCksum, "Rx TCP Checksum Error\n"); 855 vnic->rxDoneData |= Regs::RxDone_TcpError; 856 } 857 } else if (udp) { 858 vnic->rxDoneData |= Regs::RxDone_UdpPacket; 859 rxUdpChecksums++; 860 if (cksum(udp) != 0) { 861 DPRINTF(EthernetCksum, "Rx UDP Checksum Error\n"); 862 vnic->rxDoneData |= Regs::RxDone_UdpError; 863 } 864 } 865 } 866 } 867 rxState = rxBeginCopy; 868 break; 869 870 case rxBeginCopy: 871 if (dmaPending() || drainState() != DrainState::Running) 872 goto exit; 873 874 rxDmaAddr = params()->platform->pciToDma( 875 Regs::get_RxData_Addr(vnic->RxData)); 876 rxDmaLen = min<unsigned>(Regs::get_RxData_Len(vnic->RxData), 877 vnic->rxPacketBytes); 878 879 /* 880 * if we're doing zero/delay copy and we're below the fifo 881 * threshold, see if we should try to do the zero/defer copy 882 */ 883 if ((Regs::get_Config_ZeroCopy(regs.Config) || 884 Regs::get_Config_DelayCopy(regs.Config)) && 885 !Regs::get_RxData_NoDelay(vnic->RxData) && rxLow) { 886 if (rxDmaLen > regs.ZeroCopyMark) 887 rxDmaLen = regs.ZeroCopySize; 888 } 889 rxDmaData = vnic->rxIndex->packet->data + vnic->rxPacketOffset; 890 rxState = rxCopy; 891 if (rxDmaAddr == 1LL) { 892 rxState = rxCopyDone; 893 break; 894 } 895 896 dmaWrite(rxDmaAddr, rxDmaLen, &rxDmaEvent, rxDmaData); 897 break; 898 899 case rxCopy: 900 DPRINTF(EthernetSM, "receive machine still copying\n"); 901 goto exit; 902 903 case rxCopyDone: 904 vnic->RxDone = vnic->rxDoneData; 905 vnic->RxDone |= Regs::RxDone_Complete; 906 rxBusyCount--; 907 908 if (vnic->rxPacketBytes == rxDmaLen) { 909 if (vnic->rxPacketOffset) 910 rxDirtyCount--; 911 912 // Packet is complete. Indicate how many bytes were copied 913 vnic->RxDone = Regs::set_RxDone_CopyLen(vnic->RxDone, rxDmaLen); 914 915 DPRINTF(EthernetSM, 916 "rxKick: packet complete on vnic %d (rxunique %d)\n", 917 rxActive, vnic->rxUnique); 918 rxFifo.remove(vnic->rxIndex); 919 vnic->rxIndex = rxFifo.end(); 920 rxMappedCount--; 921 } else { 922 if (!vnic->rxPacketOffset) 923 rxDirtyCount++; 924 925 vnic->rxPacketBytes -= rxDmaLen; 926 vnic->rxPacketOffset += rxDmaLen; 927 vnic->RxDone |= Regs::RxDone_More; 928 vnic->RxDone = Regs::set_RxDone_CopyLen(vnic->RxDone, 929 vnic->rxPacketBytes); 930 DPRINTF(EthernetSM, 931 "rxKick: packet not complete on vnic %d (rxunique %d): " 932 "%d bytes left\n", 933 rxActive, vnic->rxUnique, vnic->rxPacketBytes); 934 } 935 936 rxActive = -1; 937 rxState = rxBusy.empty() && rxList.empty() ? rxIdle : rxFifoBlock; 938 939 if (rxFifo.empty()) { 940 devIntrPost(Regs::Intr_RxEmpty); 941 rxEmpty = true; 942 } 943 944 if (rxFifo.size() < regs.RxFifoLow) 945 rxLow = true; 946 947 if (rxFifo.size() > regs.RxFifoHigh) 948 rxLow = false; 949 950 devIntrPost(Regs::Intr_RxDMA); 951 break; 952 953 default: 954 panic("Invalid rxState!"); 955 } 956 957 DPRINTF(EthernetSM, "entering next rxState=%s\n", 958 RxStateStrings[rxState]); 959 960 goto next; 961 962 exit: 963 /** 964 * @todo do we want to schedule a future kick? 965 */ 966 DPRINTF(EthernetSM, "rx state machine exited rxState=%s\n", 967 RxStateStrings[rxState]); 968} 969 970void 971Device::txDmaDone() 972{ 973 assert(txState == txCopy); 974 txState = txCopyDone; 975 DPRINTF(EthernetDMA, "tx dma read paddr=%#x len=%d\n", 976 txDmaAddr, txDmaLen); 977 DDUMP(EthernetData, txDmaData, txDmaLen); 978 979 // If the receive state machine has a pending DMA, let it go first 980 if (rxState == rxBeginCopy) 981 rxKick(); 982 983 txKick(); 984} 985 986void 987Device::transmit() 988{ 989 if (txFifo.empty()) { 990 DPRINTF(Ethernet, "nothing to transmit\n"); 991 return; 992 } 993 994 uint32_t interrupts; 995 EthPacketPtr packet = txFifo.front(); 996 if (!interface->sendPacket(packet)) { 997 DPRINTF(Ethernet, "Packet Transmit: failed txFifo available %d\n", 998 txFifo.avail()); 999 return; 1000 } 1001 1002 txFifo.pop(); 1003#if TRACING_ON 1004 if (DTRACE(Ethernet)) { 1005 IpPtr ip(packet); 1006 if (ip) { 1007 DPRINTF(Ethernet, "ID is %d\n", ip->id()); 1008 TcpPtr tcp(ip); 1009 if (tcp) { 1010 DPRINTF(Ethernet, 1011 "Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n", 1012 tcp->sport(), tcp->dport(), tcp->seq(), 1013 tcp->ack()); 1014 } 1015 } 1016 } 1017#endif 1018 1019 DDUMP(EthernetData, packet->data, packet->length); 1020 txBytes += packet->length; 1021 txPackets++; 1022 1023 DPRINTF(Ethernet, "Packet Transmit: successful txFifo Available %d\n", 1024 txFifo.avail()); 1025 1026 interrupts = Regs::Intr_TxPacket; 1027 if (txFifo.size() < regs.TxFifoLow) 1028 interrupts |= Regs::Intr_TxLow; 1029 devIntrPost(interrupts); 1030} 1031 1032void 1033Device::txKick() 1034{ 1035 VirtualReg *vnic; 1036 DPRINTF(EthernetSM, "txKick: txState=%s (txFifo.size=%d)\n", 1037 TxStateStrings[txState], txFifo.size()); 1038 1039 if (txKickTick > curTick()) { 1040 DPRINTF(EthernetSM, "txKick: exiting, can't run till %d\n", 1041 txKickTick); 1042 return; 1043 } 1044 1045 next: 1046 if (txState == txIdle) 1047 goto exit; 1048 1049 assert(!txList.empty()); 1050 vnic = &virtualRegs[txList.front()]; 1051 1052 switch (txState) { 1053 case txFifoBlock: 1054 assert(Regs::get_TxDone_Busy(vnic->TxDone)); 1055 if (!txPacket) { 1056 // Grab a new packet from the fifo. 1057 txPacket = make_shared<EthPacketData>(16384); 1058 txPacketOffset = 0; 1059 } 1060 1061 if (txFifo.avail() - txPacket->length < 1062 Regs::get_TxData_Len(vnic->TxData)) { 1063 DPRINTF(EthernetSM, "transmit fifo full. Nothing to do.\n"); 1064 goto exit; 1065 } 1066 1067 txState = txBeginCopy; 1068 break; 1069 1070 case txBeginCopy: 1071 if (dmaPending() || drainState() != DrainState::Running) 1072 goto exit; 1073 1074 txDmaAddr = params()->platform->pciToDma( 1075 Regs::get_TxData_Addr(vnic->TxData)); 1076 txDmaLen = Regs::get_TxData_Len(vnic->TxData); 1077 txDmaData = txPacket->data + txPacketOffset; 1078 txState = txCopy; 1079 1080 dmaRead(txDmaAddr, txDmaLen, &txDmaEvent, txDmaData); 1081 break; 1082 1083 case txCopy: 1084 DPRINTF(EthernetSM, "transmit machine still copying\n"); 1085 goto exit; 1086 1087 case txCopyDone: 1088 vnic->TxDone = txDmaLen | Regs::TxDone_Complete; 1089 txPacket->length += txDmaLen; 1090 if ((vnic->TxData & Regs::TxData_More)) { 1091 txPacketOffset += txDmaLen; 1092 txState = txIdle; 1093 devIntrPost(Regs::Intr_TxDMA); 1094 break; 1095 } 1096 1097 assert(txPacket->length <= txFifo.avail()); 1098 if ((vnic->TxData & Regs::TxData_Checksum)) { 1099 IpPtr ip(txPacket); 1100 if (ip) { 1101 TcpPtr tcp(ip); 1102 if (tcp) { 1103 tcp->sum(0); 1104 tcp->sum(cksum(tcp)); 1105 txTcpChecksums++; 1106 } 1107 1108 UdpPtr udp(ip); 1109 if (udp) { 1110 udp->sum(0); 1111 udp->sum(cksum(udp)); 1112 txUdpChecksums++; 1113 } 1114 1115 ip->sum(0); 1116 ip->sum(cksum(ip)); 1117 txIpChecksums++; 1118 } 1119 } 1120 1121 txFifo.push(txPacket); 1122 if (txFifo.avail() < regs.TxMaxCopy) { 1123 devIntrPost(Regs::Intr_TxFull); 1124 txFull = true; 1125 } 1126 txPacket = 0; 1127 transmit(); 1128 txList.pop_front(); 1129 txState = txList.empty() ? txIdle : txFifoBlock; 1130 devIntrPost(Regs::Intr_TxDMA); 1131 break; 1132 1133 default: 1134 panic("Invalid txState!"); 1135 } 1136 1137 DPRINTF(EthernetSM, "entering next txState=%s\n", 1138 TxStateStrings[txState]); 1139 1140 goto next; 1141 1142 exit: 1143 /** 1144 * @todo do we want to schedule a future kick? 1145 */ 1146 DPRINTF(EthernetSM, "tx state machine exited txState=%s\n", 1147 TxStateStrings[txState]); 1148} 1149 1150void 1151Device::transferDone() 1152{ 1153 if (txFifo.empty()) { 1154 DPRINTF(Ethernet, "transfer complete: txFifo empty...nothing to do\n"); 1155 return; 1156 } 1157 1158 DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n"); 1159 1160 reschedule(txEvent, clockEdge(Cycles(1)), true); 1161} 1162 1163bool 1164Device::rxFilter(const EthPacketPtr &packet) 1165{ 1166 if (!Regs::get_Config_Filter(regs.Config)) 1167 return false; 1168 1169 panic("receive filter not implemented\n"); 1170 bool drop = true; 1171 1172#if 0 1173 string type; 1174 1175 EthHdr *eth = packet->eth(); 1176 if (eth->unicast()) { 1177 // If we're accepting all unicast addresses 1178 if (acceptUnicast) 1179 drop = false; 1180 1181 // If we make a perfect match 1182 if (acceptPerfect && params->eaddr == eth.dst()) 1183 drop = false; 1184 1185 if (acceptArp && eth->type() == ETH_TYPE_ARP) 1186 drop = false; 1187 1188 } else if (eth->broadcast()) { 1189 // if we're accepting broadcasts 1190 if (acceptBroadcast) 1191 drop = false; 1192 1193 } else if (eth->multicast()) { 1194 // if we're accepting all multicasts 1195 if (acceptMulticast) 1196 drop = false; 1197 1198 } 1199 1200 if (drop) { 1201 DPRINTF(Ethernet, "rxFilter drop\n"); 1202 DDUMP(EthernetData, packet->data, packet->length); 1203 } 1204#endif 1205 return drop; 1206} 1207 1208bool 1209Device::recvPacket(EthPacketPtr packet) 1210{ 1211 rxBytes += packet->length; 1212 rxPackets++; 1213 1214 DPRINTF(Ethernet, "Receiving packet from wire, rxFifo Available is %d\n", 1215 rxFifo.avail()); 1216 1217 if (!rxEnable) { 1218 DPRINTF(Ethernet, "receive disabled...packet dropped\n"); 1219 return true; 1220 } 1221 1222 if (rxFilter(packet)) { 1223 DPRINTF(Ethernet, "packet filtered...dropped\n"); 1224 return true; 1225 } 1226 1227 if (rxFifo.size() >= regs.RxFifoHigh) 1228 devIntrPost(Regs::Intr_RxHigh); 1229 1230 if (!rxFifo.push(packet)) { 1231 DPRINTF(Ethernet, 1232 "packet will not fit in receive buffer...packet dropped\n"); 1233 return false; 1234 } 1235 1236 // If we were at the last element, back up one ot go to the new 1237 // last element of the list. 1238 if (rxFifoPtr == rxFifo.end()) 1239 --rxFifoPtr; 1240 1241 devIntrPost(Regs::Intr_RxPacket); 1242 rxKick(); 1243 return true; 1244} 1245 1246void 1247Device::drainResume() 1248{ 1249 Drainable::drainResume(); 1250 1251 // During drain we could have left the state machines in a waiting state and 1252 // they wouldn't get out until some other event occured to kick them. 1253 // This way they'll get out immediately 1254 txKick(); 1255 rxKick(); 1256} 1257 1258//===================================================================== 1259// 1260// 1261void 1262Base::serialize(CheckpointOut &cp) const 1263{ 1264 // Serialize the PciDevice base class 1265 PciDevice::serialize(cp); 1266 1267 SERIALIZE_SCALAR(rxEnable); 1268 SERIALIZE_SCALAR(txEnable); 1269 SERIALIZE_SCALAR(cpuIntrEnable); 1270 1271 /* 1272 * Keep track of pending interrupt status. 1273 */ 1274 SERIALIZE_SCALAR(intrTick); 1275 SERIALIZE_SCALAR(cpuPendingIntr); 1276 Tick intrEventTick = 0; 1277 if (intrEvent) 1278 intrEventTick = intrEvent->when(); 1279 SERIALIZE_SCALAR(intrEventTick); 1280} 1281 1282void 1283Base::unserialize(CheckpointIn &cp) 1284{ 1285 // Unserialize the PciDevice base class 1286 PciDevice::unserialize(cp); 1287 1288 UNSERIALIZE_SCALAR(rxEnable); 1289 UNSERIALIZE_SCALAR(txEnable); 1290 UNSERIALIZE_SCALAR(cpuIntrEnable); 1291 1292 /* 1293 * Keep track of pending interrupt status. 1294 */ 1295 UNSERIALIZE_SCALAR(intrTick); 1296 UNSERIALIZE_SCALAR(cpuPendingIntr); 1297 Tick intrEventTick; 1298 UNSERIALIZE_SCALAR(intrEventTick); 1299 if (intrEventTick) { 1300 intrEvent = new IntrEvent(this, true); 1301 schedule(intrEvent, intrEventTick); 1302 } 1303} 1304 1305void 1306Device::serializeOld(CheckpointOut &cp) 1307{ 1308 int count; 1309 1310 // Serialize the PciDevice base class 1311 Base::serialize(cp); 1312 1313 if (rxState == rxCopy) 1314 panic("can't serialize with an in flight dma request rxState=%s", 1315 RxStateStrings[rxState]); 1316 1317 if (txState == txCopy) 1318 panic("can't serialize with an in flight dma request txState=%s", 1319 TxStateStrings[txState]); 1320 1321 /* 1322 * Serialize the device registers that could be modified by the OS. 1323 */ 1324 SERIALIZE_SCALAR(regs.Config); 1325 SERIALIZE_SCALAR(regs.IntrStatus); 1326 SERIALIZE_SCALAR(regs.IntrMask); 1327 SERIALIZE_SCALAR(regs.RxData); 1328 SERIALIZE_SCALAR(regs.TxData); 1329 1330 /* 1331 * Serialize the virtual nic state 1332 */ 1333 int virtualRegsSize = virtualRegs.size(); 1334 SERIALIZE_SCALAR(virtualRegsSize); 1335 for (int i = 0; i < virtualRegsSize; ++i) { 1336 const VirtualReg *vnic = &virtualRegs[i]; 1337 1338 std::string reg = csprintf("vnic%d", i); 1339 paramOut(cp, reg + ".RxData", vnic->RxData); 1340 paramOut(cp, reg + ".RxDone", vnic->RxDone); 1341 paramOut(cp, reg + ".TxData", vnic->TxData); 1342 paramOut(cp, reg + ".TxDone", vnic->TxDone); 1343 1344 bool rxPacketExists = vnic->rxIndex != rxFifo.end(); 1345 paramOut(cp, reg + ".rxPacketExists", rxPacketExists); 1346 if (rxPacketExists) { 1347 int rxPacket = 0; 1348 PacketFifo::iterator i = rxFifo.begin(); 1349 while (i != vnic->rxIndex) { 1350 assert(i != rxFifo.end()); 1351 ++i; 1352 ++rxPacket; 1353 } 1354 1355 paramOut(cp, reg + ".rxPacket", rxPacket); 1356 paramOut(cp, reg + ".rxPacketOffset", vnic->rxPacketOffset); 1357 paramOut(cp, reg + ".rxPacketBytes", vnic->rxPacketBytes); 1358 } 1359 paramOut(cp, reg + ".rxDoneData", vnic->rxDoneData); 1360 } 1361 1362 int rxFifoPtr = -1; 1363 if (this->rxFifoPtr != rxFifo.end()) 1364 rxFifoPtr = rxFifo.countPacketsBefore(this->rxFifoPtr); 1365 SERIALIZE_SCALAR(rxFifoPtr); 1366 1367 SERIALIZE_SCALAR(rxActive); 1368 SERIALIZE_SCALAR(rxBusyCount); 1369 SERIALIZE_SCALAR(rxDirtyCount); 1370 SERIALIZE_SCALAR(rxMappedCount); 1371 1372 VirtualList::iterator i, end; 1373 for (count = 0, i = rxList.begin(), end = rxList.end(); i != end; ++i) 1374 paramOut(cp, csprintf("rxList%d", count++), *i); 1375 int rxListSize = count; 1376 SERIALIZE_SCALAR(rxListSize); 1377 1378 for (count = 0, i = rxBusy.begin(), end = rxBusy.end(); i != end; ++i) 1379 paramOut(cp, csprintf("rxBusy%d", count++), *i); 1380 int rxBusySize = count; 1381 SERIALIZE_SCALAR(rxBusySize); 1382 1383 for (count = 0, i = txList.begin(), end = txList.end(); i != end; ++i) 1384 paramOut(cp, csprintf("txList%d", count++), *i); 1385 int txListSize = count; 1386 SERIALIZE_SCALAR(txListSize); 1387 1388 /* 1389 * Serialize rx state machine 1390 */ 1391 int rxState = this->rxState; 1392 SERIALIZE_SCALAR(rxState); 1393 SERIALIZE_SCALAR(rxEmpty); 1394 SERIALIZE_SCALAR(rxLow); 1395 rxFifo.serialize("rxFifo", cp); 1396 1397 /* 1398 * Serialize tx state machine 1399 */ 1400 int txState = this->txState; 1401 SERIALIZE_SCALAR(txState); 1402 SERIALIZE_SCALAR(txFull); 1403 txFifo.serialize("txFifo", cp); 1404 bool txPacketExists = txPacket != nullptr; 1405 SERIALIZE_SCALAR(txPacketExists); 1406 if (txPacketExists) { 1407 txPacket->serialize("txPacket", cp); 1408 SERIALIZE_SCALAR(txPacketOffset); 1409 SERIALIZE_SCALAR(txPacketBytes); 1410 } 1411 1412 /* 1413 * If there's a pending transmit, store the time so we can 1414 * reschedule it later 1415 */ 1416 Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick() : 0; 1417 SERIALIZE_SCALAR(transmitTick); 1418} 1419 1420void 1421Device::unserialize(CheckpointIn &cp) 1422{ 1423 // Unserialize the PciDevice base class 1424 Base::unserialize(cp); 1425 1426 /* 1427 * Unserialize the device registers that may have been written by the OS. 1428 */ 1429 UNSERIALIZE_SCALAR(regs.Config); 1430 UNSERIALIZE_SCALAR(regs.IntrStatus); 1431 UNSERIALIZE_SCALAR(regs.IntrMask); 1432 UNSERIALIZE_SCALAR(regs.RxData); 1433 UNSERIALIZE_SCALAR(regs.TxData); 1434 1435 UNSERIALIZE_SCALAR(rxActive); 1436 UNSERIALIZE_SCALAR(rxBusyCount); 1437 UNSERIALIZE_SCALAR(rxDirtyCount); 1438 UNSERIALIZE_SCALAR(rxMappedCount); 1439 1440 int rxListSize; 1441 UNSERIALIZE_SCALAR(rxListSize); 1442 rxList.clear(); 1443 for (int i = 0; i < rxListSize; ++i) { 1444 int value; 1445 paramIn(cp, csprintf("rxList%d", i), value); 1446 rxList.push_back(value); 1447 } 1448 1449 int rxBusySize; 1450 UNSERIALIZE_SCALAR(rxBusySize); 1451 rxBusy.clear(); 1452 for (int i = 0; i < rxBusySize; ++i) { 1453 int value; 1454 paramIn(cp, csprintf("rxBusy%d", i), value); 1455 rxBusy.push_back(value); 1456 } 1457 1458 int txListSize; 1459 UNSERIALIZE_SCALAR(txListSize); 1460 txList.clear(); 1461 for (int i = 0; i < txListSize; ++i) { 1462 int value; 1463 paramIn(cp, csprintf("txList%d", i), value); 1464 txList.push_back(value); 1465 } 1466 1467 /* 1468 * Unserialize rx state machine 1469 */ 1470 int rxState; 1471 UNSERIALIZE_SCALAR(rxState); 1472 UNSERIALIZE_SCALAR(rxEmpty); 1473 UNSERIALIZE_SCALAR(rxLow); 1474 this->rxState = (RxState) rxState; 1475 rxFifo.unserialize("rxFifo", cp); 1476 1477 int rxFifoPtr; 1478 UNSERIALIZE_SCALAR(rxFifoPtr); 1479 if (rxFifoPtr >= 0) { 1480 this->rxFifoPtr = rxFifo.begin(); 1481 for (int i = 0; i < rxFifoPtr; ++i) 1482 ++this->rxFifoPtr; 1483 } else { 1484 this->rxFifoPtr = rxFifo.end(); 1485 } 1486 1487 /* 1488 * Unserialize tx state machine 1489 */ 1490 int txState; 1491 UNSERIALIZE_SCALAR(txState); 1492 UNSERIALIZE_SCALAR(txFull); 1493 this->txState = (TxState) txState; 1494 txFifo.unserialize("txFifo", cp); 1495 bool txPacketExists; 1496 UNSERIALIZE_SCALAR(txPacketExists); 1497 txPacket = 0; 1498 if (txPacketExists) { 1499 txPacket = make_shared<EthPacketData>(16384); 1500 txPacket->unserialize("txPacket", cp); 1501 UNSERIALIZE_SCALAR(txPacketOffset); 1502 UNSERIALIZE_SCALAR(txPacketBytes); 1503 } 1504 1505 /* 1506 * unserialize the virtual nic registers/state 1507 * 1508 * this must be done after the unserialization of the rxFifo 1509 * because the packet iterators depend on the fifo being populated 1510 */ 1511 int virtualRegsSize; 1512 UNSERIALIZE_SCALAR(virtualRegsSize); 1513 virtualRegs.clear(); 1514 virtualRegs.resize(virtualRegsSize); 1515 for (int i = 0; i < virtualRegsSize; ++i) { 1516 VirtualReg *vnic = &virtualRegs[i]; 1517 std::string reg = csprintf("vnic%d", i); 1518 1519 paramIn(cp, reg + ".RxData", vnic->RxData); 1520 paramIn(cp, reg + ".RxDone", vnic->RxDone); 1521 paramIn(cp, reg + ".TxData", vnic->TxData); 1522 paramIn(cp, reg + ".TxDone", vnic->TxDone); 1523 1524 vnic->rxUnique = rxUnique++; 1525 vnic->txUnique = txUnique++; 1526 1527 bool rxPacketExists; 1528 paramIn(cp, reg + ".rxPacketExists", rxPacketExists); 1529 if (rxPacketExists) { 1530 int rxPacket; 1531 paramIn(cp, reg + ".rxPacket", rxPacket); 1532 vnic->rxIndex = rxFifo.begin(); 1533 while (rxPacket--) 1534 ++vnic->rxIndex; 1535 1536 paramIn(cp, reg + ".rxPacketOffset", 1537 vnic->rxPacketOffset); 1538 paramIn(cp, reg + ".rxPacketBytes", vnic->rxPacketBytes); 1539 } else { 1540 vnic->rxIndex = rxFifo.end(); 1541 } 1542 paramIn(cp, reg + ".rxDoneData", vnic->rxDoneData); 1543 } 1544 1545 /* 1546 * If there's a pending transmit, reschedule it now 1547 */ 1548 Tick transmitTick; 1549 UNSERIALIZE_SCALAR(transmitTick); 1550 if (transmitTick) 1551 schedule(txEvent, curTick() + transmitTick); 1552 1553 pioPort.sendRangeChange(); 1554 1555} 1556 1557} // namespace Sinic 1558 1559Sinic::Device * 1560SinicParams::create() 1561{ 1562 return new Sinic::Device(this); 1563} 1564