ns_gige_reg.h revision 2665
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Lisa Hsu 29 */ 30 31/** @file 32 * Ethernet device register definitions for the National 33 * Semiconductor DP83820 Ethernet controller 34 */ 35 36#ifndef __DEV_NS_GIGE_REG_H__ 37#define __DEV_NS_GIGE_REG_H__ 38 39/* Device Register Address Map */ 40#define CR 0x00 41#define CFGR 0x04 42#define MEAR 0x08 43#define PTSCR 0x0c 44#define ISR 0x10 45#define IMR 0x14 46#define IER 0x18 47#define IHR 0x1c 48#define TXDP 0x20 49#define TXDP_HI 0x24 50#define TX_CFG 0x28 51#define GPIOR 0x2c 52#define RXDP 0x30 53#define RXDP_HI 0x34 54#define RX_CFG 0x38 55#define PQCR 0x3c 56#define WCSR 0x40 57#define PCR 0x44 58#define RFCR 0x48 59#define RFDR 0x4c 60#define BRAR 0x50 61#define BRDR 0x54 62#define SRR 0x58 63#define MIBC 0x5c 64#define MIB_START 0x60 65#define MIB_END 0x88 66#define VRCR 0xbc 67#define VTCR 0xc0 68#define VDR 0xc4 69#define CCSR 0xcc 70#define TBICR 0xe0 71#define TBISR 0xe4 72#define TANAR 0xe8 73#define TANLPAR 0xec 74#define TANER 0xf0 75#define TESR 0xf4 76#define M5REG 0xf8 77#define LAST 0xf8 78#define RESERVED 0xfc 79 80/* Chip Command Register */ 81#define CR_TXE 0x00000001 82#define CR_TXD 0x00000002 83#define CR_RXE 0x00000004 84#define CR_RXD 0x00000008 85#define CR_TXR 0x00000010 86#define CR_RXR 0x00000020 87#define CR_SWI 0x00000080 88#define CR_RST 0x00000100 89 90/* configuration register */ 91#define CFGR_LNKSTS 0x80000000 92#define CFGR_SPDSTS 0x60000000 93#define CFGR_SPDSTS1 0x40000000 94#define CFGR_SPDSTS0 0x20000000 95#define CFGR_DUPSTS 0x10000000 96#define CFGR_TBI_EN 0x01000000 97#define CFGR_RESERVED 0x0e000000 98#define CFGR_MODE_1000 0x00400000 99#define CFGR_AUTO_1000 0x00200000 100#define CFGR_PINT_CTL 0x001c0000 101#define CFGR_PINT_DUPSTS 0x00100000 102#define CFGR_PINT_LNKSTS 0x00080000 103#define CFGR_PINT_SPDSTS 0x00040000 104#define CFGR_TMRTEST 0x00020000 105#define CFGR_MRM_DIS 0x00010000 106#define CFGR_MWI_DIS 0x00008000 107#define CFGR_T64ADDR 0x00004000 108#define CFGR_PCI64_DET 0x00002000 109#define CFGR_DATA64_EN 0x00001000 110#define CFGR_M64ADDR 0x00000800 111#define CFGR_PHY_RST 0x00000400 112#define CFGR_PHY_DIS 0x00000200 113#define CFGR_EXTSTS_EN 0x00000100 114#define CFGR_REQALG 0x00000080 115#define CFGR_SB 0x00000040 116#define CFGR_POW 0x00000020 117#define CFGR_EXD 0x00000010 118#define CFGR_PESEL 0x00000008 119#define CFGR_BROM_DIS 0x00000004 120#define CFGR_EXT_125 0x00000002 121#define CFGR_BEM 0x00000001 122 123/* EEPROM access register */ 124#define MEAR_EEDI 0x00000001 125#define MEAR_EEDO 0x00000002 126#define MEAR_EECLK 0x00000004 127#define MEAR_EESEL 0x00000008 128#define MEAR_MDIO 0x00000010 129#define MEAR_MDDIR 0x00000020 130#define MEAR_MDC 0x00000040 131 132/* PCI test control register */ 133#define PTSCR_EEBIST_FAIL 0x00000001 134#define PTSCR_EEBIST_EN 0x00000002 135#define PTSCR_EELOAD_EN 0x00000004 136#define PTSCR_RBIST_FAIL 0x000001b8 137#define PTSCR_RBIST_DONE 0x00000200 138#define PTSCR_RBIST_EN 0x00000400 139#define PTSCR_RBIST_RST 0x00002000 140#define PTSCR_RBIST_RDONLY 0x000003f9 141 142/* interrupt status register */ 143#define ISR_RESERVE 0x80000000 144#define ISR_TXDESC3 0x40000000 145#define ISR_TXDESC2 0x20000000 146#define ISR_TXDESC1 0x10000000 147#define ISR_TXDESC0 0x08000000 148#define ISR_RXDESC3 0x04000000 149#define ISR_RXDESC2 0x02000000 150#define ISR_RXDESC1 0x01000000 151#define ISR_RXDESC0 0x00800000 152#define ISR_TXRCMP 0x00400000 153#define ISR_RXRCMP 0x00200000 154#define ISR_DPERR 0x00100000 155#define ISR_SSERR 0x00080000 156#define ISR_RMABT 0x00040000 157#define ISR_RTABT 0x00020000 158#define ISR_RXSOVR 0x00010000 159#define ISR_HIBINT 0x00008000 160#define ISR_PHY 0x00004000 161#define ISR_PME 0x00002000 162#define ISR_SWI 0x00001000 163#define ISR_MIB 0x00000800 164#define ISR_TXURN 0x00000400 165#define ISR_TXIDLE 0x00000200 166#define ISR_TXERR 0x00000100 167#define ISR_TXDESC 0x00000080 168#define ISR_TXOK 0x00000040 169#define ISR_RXORN 0x00000020 170#define ISR_RXIDLE 0x00000010 171#define ISR_RXEARLY 0x00000008 172#define ISR_RXERR 0x00000004 173#define ISR_RXDESC 0x00000002 174#define ISR_RXOK 0x00000001 175#define ISR_ALL 0x7FFFFFFF 176#define ISR_DELAY (ISR_TXIDLE|ISR_TXDESC|ISR_TXOK| \ 177 ISR_RXIDLE|ISR_RXDESC|ISR_RXOK) 178#define ISR_NODELAY (ISR_ALL & ~ISR_DELAY) 179#define ISR_IMPL (ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN| \ 180 ISR_RXIDLE|ISR_RXDESC|ISR_RXOK) 181#define ISR_NOIMPL (ISR_ALL & ~ISR_IMPL) 182 183/* transmit configuration register */ 184#define TX_CFG_CSI 0x80000000 185#define TX_CFG_HBI 0x40000000 186#define TX_CFG_MLB 0x20000000 187#define TX_CFG_ATP 0x10000000 188#define TX_CFG_ECRETRY 0x00800000 189#define TX_CFG_BRST_DIS 0x00080000 190#define TX_CFG_MXDMA1024 0x00000000 191#define TX_CFG_MXDMA512 0x00700000 192#define TX_CFG_MXDMA256 0x00600000 193#define TX_CFG_MXDMA128 0x00500000 194#define TX_CFG_MXDMA64 0x00400000 195#define TX_CFG_MXDMA32 0x00300000 196#define TX_CFG_MXDMA16 0x00200000 197#define TX_CFG_MXDMA8 0x00100000 198#define TX_CFG_MXDMA 0x00700000 199 200#define TX_CFG_FLTH_MASK 0x0000ff00 201#define TX_CFG_DRTH_MASK 0x000000ff 202 203/*general purpose I/O control register */ 204#define GPIOR_UNUSED 0xffff8000 205#define GPIOR_GP5_IN 0x00004000 206#define GPIOR_GP4_IN 0x00002000 207#define GPIOR_GP3_IN 0x00001000 208#define GPIOR_GP2_IN 0x00000800 209#define GPIOR_GP1_IN 0x00000400 210#define GPIOR_GP5_OE 0x00000200 211#define GPIOR_GP4_OE 0x00000100 212#define GPIOR_GP3_OE 0x00000080 213#define GPIOR_GP2_OE 0x00000040 214#define GPIOR_GP1_OE 0x00000020 215#define GPIOR_GP5_OUT 0x00000010 216#define GPIOR_GP4_OUT 0x00000008 217#define GPIOR_GP3_OUT 0x00000004 218#define GPIOR_GP2_OUT 0x00000002 219#define GPIOR_GP1_OUT 0x00000001 220 221/* receive configuration register */ 222#define RX_CFG_AEP 0x80000000 223#define RX_CFG_ARP 0x40000000 224#define RX_CFG_STRIPCRC 0x20000000 225#define RX_CFG_RX_FD 0x10000000 226#define RX_CFG_ALP 0x08000000 227#define RX_CFG_AIRL 0x04000000 228#define RX_CFG_MXDMA512 0x00700000 229#define RX_CFG_MXDMA 0x00700000 230#define RX_CFG_DRTH 0x0000003e 231#define RX_CFG_DRTH0 0x00000002 232 233/* pause control status register */ 234#define PCR_PSEN (1 << 31) 235#define PCR_PS_MCAST (1 << 30) 236#define PCR_PS_DA (1 << 29) 237#define PCR_STHI_8 (3 << 23) 238#define PCR_STLO_4 (1 << 23) 239#define PCR_FFHI_8K (3 << 21) 240#define PCR_FFLO_4K (1 << 21) 241#define PCR_PAUSE_CNT 0xFFFE 242 243/*receive filter/match control register */ 244#define RFCR_RFEN 0x80000000 245#define RFCR_AAB 0x40000000 246#define RFCR_AAM 0x20000000 247#define RFCR_AAU 0x10000000 248#define RFCR_APM 0x08000000 249#define RFCR_APAT 0x07800000 250#define RFCR_APAT3 0x04000000 251#define RFCR_APAT2 0x02000000 252#define RFCR_APAT1 0x01000000 253#define RFCR_APAT0 0x00800000 254#define RFCR_AARP 0x00400000 255#define RFCR_MHEN 0x00200000 256#define RFCR_UHEN 0x00100000 257#define RFCR_ULM 0x00080000 258#define RFCR_RFADDR 0x000003ff 259 260/* receive filter/match data register */ 261#define RFDR_BMASK 0x00030000 262#define RFDR_RFDATA0 0x000000ff 263#define RFDR_RFDATA1 0x0000ff00 264 265/* management information base control register */ 266#define MIBC_MIBS 0x00000008 267#define MIBC_ACLR 0x00000004 268#define MIBC_FRZ 0x00000002 269#define MIBC_WRN 0x00000001 270 271/* VLAN/IP receive control register */ 272#define VRCR_RUDPE 0x00000080 273#define VRCR_RTCPE 0x00000040 274#define VRCR_RIPE 0x00000020 275#define VRCR_IPEN 0x00000010 276#define VRCR_DUTF 0x00000008 277#define VRCR_DVTF 0x00000004 278#define VRCR_VTREN 0x00000002 279#define VRCR_VTDEN 0x00000001 280 281/* VLAN/IP transmit control register */ 282#define VTCR_PPCHK 0x00000008 283#define VTCR_GCHK 0x00000004 284#define VTCR_VPPTI 0x00000002 285#define VTCR_VGTI 0x00000001 286 287/* Clockrun Control/Status Register */ 288#define CCSR_CLKRUN_EN 0x00000001 289 290/* TBI control register */ 291#define TBICR_MR_LOOPBACK 0x00004000 292#define TBICR_MR_AN_ENABLE 0x00001000 293#define TBICR_MR_RESTART_AN 0x00000200 294 295/* TBI status register */ 296#define TBISR_MR_LINK_STATUS 0x00000020 297#define TBISR_MR_AN_COMPLETE 0x00000004 298 299/* TBI auto-negotiation advertisement register */ 300#define TANAR_NP 0x00008000 301#define TANAR_RF2 0x00002000 302#define TANAR_RF1 0x00001000 303#define TANAR_PS2 0x00000100 304#define TANAR_PS1 0x00000080 305#define TANAR_HALF_DUP 0x00000040 306#define TANAR_FULL_DUP 0x00000020 307#define TANAR_UNUSED 0x00000E1F 308 309/* M5 control register */ 310#define M5REG_RESERVED 0xfffffffc 311#define M5REG_RSS 0x00000004 312#define M5REG_RX_THREAD 0x00000002 313#define M5REG_TX_THREAD 0x00000001 314 315struct ns_desc32 { 316 uint32_t link; /* link field to next descriptor in linked list */ 317 uint32_t bufptr; /* pointer to the first fragment or buffer */ 318 uint32_t cmdsts; /* command/status field */ 319 uint32_t extsts; /* extended status field for VLAN and IP info */ 320}; 321 322struct ns_desc64 { 323 uint64_t link; /* link field to next descriptor in linked list */ 324 uint64_t bufptr; /* pointer to the first fragment or buffer */ 325 uint32_t cmdsts; /* command/status field */ 326 uint32_t extsts; /* extended status field for VLAN and IP info */ 327}; 328 329/* cmdsts flags for descriptors */ 330#define CMDSTS_OWN 0x80000000 331#define CMDSTS_MORE 0x40000000 332#define CMDSTS_INTR 0x20000000 333#define CMDSTS_ERR 0x10000000 334#define CMDSTS_OK 0x08000000 335#define CMDSTS_LEN_MASK 0x0000ffff 336 337#define CMDSTS_DEST_MASK 0x01800000 338#define CMDSTS_DEST_SELF 0x00800000 339#define CMDSTS_DEST_MULTI 0x01000000 340 341/* extended flags for descriptors */ 342#define EXTSTS_UDPERR 0x00400000 343#define EXTSTS_UDPPKT 0x00200000 344#define EXTSTS_TCPERR 0x00100000 345#define EXTSTS_TCPPKT 0x00080000 346#define EXTSTS_IPERR 0x00040000 347#define EXTSTS_IPPKT 0x00020000 348 349 350/* speed status */ 351#define SPDSTS_POLARITY (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS | (lnksts ? CFGR_LNKSTS : 0)) 352 353#endif /* __DEV_NS_GIGE_REG_H__ */ 354