ns_gige_reg.h revision 1762
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Ethernet device register definitions for the National
31 * Semiconductor DP83820 Ethernet controller
32 */
33
34#ifndef __DEV_NS_GIGE_REG_H__
35#define __DEV_NS_GIGE_REG_H__
36
37/* Device Register Address Map */
38#define CR		0x00
39#define CFGR		0x04
40#define MEAR		0x08
41#define PTSCR		0x0c
42#define	ISR		0x10
43#define	IMR		0x14
44#define	IER		0x18
45#define	IHR		0x1c
46#define TXDP		0x20
47#define TXDP_HI		0x24
48#define TX_CFG		0x28
49#define GPIOR		0x2c
50#define RXDP		0x30
51#define RXDP_HI		0x34
52#define RX_CFG		0x38
53#define PQCR		0x3c
54#define WCSR		0x40
55#define PCR		0x44
56#define RFCR		0x48
57#define RFDR		0x4c
58#define BRAR            0x50
59#define BRDR            0x54
60#define SRR		0x58
61#define MIBC            0x5c
62#define MIB_START       0x60
63#define MIB_END         0x88
64#define VRCR		0xbc
65#define VTCR		0xc0
66#define VDR		0xc4
67#define CCSR		0xcc
68#define TBICR		0xe0
69#define TBISR		0xe4
70#define TANAR		0xe8
71#define TANLPAR		0xec
72#define TANER		0xf0
73#define TESR		0xf4
74#define M5REG		0xf8
75#define LAST            0xf8
76#define RESERVED        0xfc
77
78/* Chip Command Register */
79#define CR_TXE		0x00000001
80#define CR_TXD		0x00000002
81#define CR_RXE		0x00000004
82#define CR_RXD		0x00000008
83#define CR_TXR		0x00000010
84#define CR_RXR		0x00000020
85#define CR_SWI		0x00000080
86#define CR_RST		0x00000100
87
88/* configuration register */
89#define CFGR_LNKSTS	0x80000000
90#define CFGR_SPDSTS	0x60000000
91#define CFGR_SPDSTS1	0x40000000
92#define CFGR_SPDSTS0	0x20000000
93#define CFGR_DUPSTS	0x10000000
94#define CFGR_TBI_EN	0x01000000
95#define CFGR_RESERVED    0x0e000000
96#define CFGR_MODE_1000	0x00400000
97#define CFGR_AUTO_1000	0x00200000
98#define CFGR_PINT_CTL	0x001c0000
99#define CFGR_PINT_DUPSTS	0x00100000
100#define CFGR_PINT_LNKSTS	0x00080000
101#define CFGR_PINT_SPDSTS	0x00040000
102#define CFGR_TMRTEST	0x00020000
103#define CFGR_MRM_DIS	0x00010000
104#define CFGR_MWI_DIS	0x00008000
105#define CFGR_T64ADDR	0x00004000
106#define CFGR_PCI64_DET	0x00002000
107#define CFGR_DATA64_EN	0x00001000
108#define CFGR_M64ADDR	0x00000800
109#define CFGR_PHY_RST	0x00000400
110#define CFGR_PHY_DIS	0x00000200
111#define CFGR_EXTSTS_EN	0x00000100
112#define CFGR_REQALG	0x00000080
113#define CFGR_SB		0x00000040
114#define CFGR_POW		0x00000020
115#define CFGR_EXD		0x00000010
116#define CFGR_PESEL	0x00000008
117#define CFGR_BROM_DIS	0x00000004
118#define CFGR_EXT_125	0x00000002
119#define CFGR_BEM		0x00000001
120
121/* EEPROM access register */
122#define MEAR_EEDI             	0x00000001
123#define MEAR_EEDO		0x00000002
124#define MEAR_EECLK		0x00000004
125#define MEAR_EESEL		0x00000008
126#define MEAR_MDIO		0x00000010
127#define MEAR_MDDIR		0x00000020
128#define MEAR_MDC		0x00000040
129
130/* PCI test control register */
131#define PTSCR_EEBIST_FAIL       0x00000001
132#define PTSCR_EEBIST_EN         0x00000002
133#define PTSCR_EELOAD_EN         0x00000004
134#define PTSCR_RBIST_FAIL        0x000001b8
135#define PTSCR_RBIST_DONE        0x00000200
136#define PTSCR_RBIST_EN          0x00000400
137#define PTSCR_RBIST_RST         0x00002000
138#define PTSCR_RBIST_RDONLY      0x000003f9
139
140/* interrupt status register */
141#define ISR_RESERVE     0x80000000
142#define ISR_TXDESC3	0x40000000
143#define ISR_TXDESC2	0x20000000
144#define ISR_TXDESC1	0x10000000
145#define ISR_TXDESC0	0x08000000
146#define ISR_RXDESC3	0x04000000
147#define ISR_RXDESC2	0x02000000
148#define ISR_RXDESC1	0x01000000
149#define ISR_RXDESC0	0x00800000
150#define ISR_TXRCMP	0x00400000
151#define ISR_RXRCMP	0x00200000
152#define ISR_DPERR	0x00100000
153#define ISR_SSERR	0x00080000
154#define ISR_RMABT	0x00040000
155#define ISR_RTABT	0x00020000
156#define ISR_RXSOVR	0x00010000
157#define ISR_HIBINT	0x00008000
158#define ISR_PHY		0x00004000
159#define ISR_PME		0x00002000
160#define ISR_SWI		0x00001000
161#define ISR_MIB		0x00000800
162#define ISR_TXURN	0x00000400
163#define ISR_TXIDLE	0x00000200
164#define ISR_TXERR	0x00000100
165#define ISR_TXDESC	0x00000080
166#define ISR_TXOK	0x00000040
167#define ISR_RXORN	0x00000020
168#define ISR_RXIDLE	0x00000010
169#define ISR_RXEARLY	0x00000008
170#define ISR_RXERR	0x00000004
171#define ISR_RXDESC	0x00000002
172#define ISR_RXOK	0x00000001
173#define ISR_ALL         0x7FFFFFFF
174#define ISR_NODELAY	(ISR_ALL & ~(ISR_RXOK|ISR_RXDESC|ISR_TXOK|ISR_TXDESC))
175#define ISR_NOIMPL	(~(ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN| \
176                           ISR_RXIDLE|ISR_RXDESC|ISR_RXOK))
177
178/* transmit configuration register */
179#define TX_CFG_CSI	0x80000000
180#define TX_CFG_HBI	0x40000000
181#define TX_CFG_MLB	0x20000000
182#define TX_CFG_ATP	0x10000000
183#define TX_CFG_ECRETRY	0x00800000
184#define TX_CFG_BRST_DIS	0x00080000
185#define TX_CFG_MXDMA1024	0x00000000
186#define TX_CFG_MXDMA512	0x00700000
187#define TX_CFG_MXDMA256	0x00600000
188#define TX_CFG_MXDMA128	0x00500000
189#define TX_CFG_MXDMA64	0x00400000
190#define TX_CFG_MXDMA32	0x00300000
191#define TX_CFG_MXDMA16	0x00200000
192#define TX_CFG_MXDMA8	0x00100000
193#define TX_CFG_MXDMA     0x00700000
194
195#define TX_CFG_FLTH_MASK 0x0000ff00
196#define TX_CFG_DRTH_MASK 0x000000ff
197
198/*general purpose I/O control register */
199#define GPIOR_GP5_OE		0x00000200
200#define GPIOR_GP4_OE		0x00000100
201#define GPIOR_GP3_OE		0x00000080
202#define GPIOR_GP2_OE		0x00000040
203#define GPIOR_GP1_OE		0x00000020
204#define GPIOR_GP3_OUT		0x00000004
205#define GPIOR_GP1_OUT		0x00000001
206
207/* receive configuration register */
208#define RX_CFG_AEP	0x80000000
209#define RX_CFG_ARP	0x40000000
210#define RX_CFG_STRIPCRC	0x20000000
211#define RX_CFG_RX_FD	0x10000000
212#define RX_CFG_ALP	0x08000000
213#define RX_CFG_AIRL	0x04000000
214#define RX_CFG_MXDMA512	0x00700000
215#define RX_CFG_MXDMA     0x00700000
216#define RX_CFG_DRTH	0x0000003e
217#define RX_CFG_DRTH0	0x00000002
218
219/* pause control status register */
220#define PCR_PSEN	(1 << 31)
221#define PCR_PS_MCAST	(1 << 30)
222#define PCR_PS_DA	(1 << 29)
223#define PCR_STHI_8	(3 << 23)
224#define PCR_STLO_4	(1 << 23)
225#define PCR_FFHI_8K	(3 << 21)
226#define PCR_FFLO_4K	(1 << 21)
227#define PCR_PAUSE_CNT	0xFFFE
228
229/*receive filter/match control register */
230#define RFCR_RFEN	0x80000000
231#define RFCR_AAB	0x40000000
232#define RFCR_AAM	0x20000000
233#define RFCR_AAU	0x10000000
234#define RFCR_APM	0x08000000
235#define RFCR_APAT	0x07800000
236#define RFCR_APAT3	0x04000000
237#define RFCR_APAT2	0x02000000
238#define RFCR_APAT1	0x01000000
239#define RFCR_APAT0	0x00800000
240#define RFCR_AARP	0x00400000
241#define RFCR_MHEN	0x00200000
242#define RFCR_UHEN	0x00100000
243#define RFCR_ULM	0x00080000
244#define RFCR_RFADDR     0x000003ff
245
246/* receive filter/match data register */
247#define RFDR_BMASK      0x00030000
248#define RFDR_RFDATA0    0x000000ff
249#define RFDR_RFDATA1    0x0000ff00
250
251/* management information base control register */
252#define MIBC_MIBS	0x00000008
253#define MIBC_ACLR	0x00000004
254#define MIBC_FRZ	0x00000002
255#define MIBC_WRN	0x00000001
256
257/* VLAN/IP receive control register */
258#define VRCR_RUDPE	0x00000080
259#define VRCR_RTCPE	0x00000040
260#define VRCR_RIPE	0x00000020
261#define VRCR_IPEN	0x00000010
262#define VRCR_DUTF	0x00000008
263#define VRCR_DVTF	0x00000004
264#define VRCR_VTREN	0x00000002
265#define VRCR_VTDEN	0x00000001
266
267/* VLAN/IP transmit control register */
268#define VTCR_PPCHK	0x00000008
269#define VTCR_GCHK	0x00000004
270#define VTCR_VPPTI	0x00000002
271#define VTCR_VGTI	0x00000001
272
273/* Clockrun Control/Status Register */
274#define CCSR_CLKRUN_EN  0x00000001
275
276/* TBI control register */
277#define TBICR_MR_LOOPBACK       0x00004000
278#define TBICR_MR_AN_ENABLE	0x00001000
279#define TBICR_MR_RESTART_AN	0x00000200
280
281/* TBI status register */
282#define TBISR_MR_LINK_STATUS	0x00000020
283#define TBISR_MR_AN_COMPLETE	0x00000004
284
285/* TBI auto-negotiation advertisement register */
286#define TANAR_PS2 		0x00000100
287#define TANAR_PS1 		0x00000080
288#define TANAR_HALF_DUP 		0x00000040
289#define TANAR_FULL_DUP 		0x00000020
290
291/*
292 * descriptor format currently assuming link and bufptr
293 * are set for 32 bits,( may be wrong ) ASSUME32
294 */
295struct ns_desc {
296  uint32_t link;    /* link field to next descriptor in linked list */
297  uint32_t bufptr;  /* pointer to the first fragment or buffer */
298  uint32_t cmdsts;  /* command/status field */
299  uint32_t extsts;  /* extended status field for VLAN and IP info */
300};
301
302/* cmdsts flags for descriptors */
303#define CMDSTS_OWN	0x80000000
304#define CMDSTS_MORE	0x40000000
305#define CMDSTS_INTR	0x20000000
306#define CMDSTS_ERR	0x10000000
307#define CMDSTS_OK	0x08000000
308#define CMDSTS_LEN_MASK	0x0000ffff
309
310#define CMDSTS_DEST_MASK	0x01800000
311#define CMDSTS_DEST_SELF	0x00800000
312#define CMDSTS_DEST_MULTI	0x01000000
313
314/* extended flags for descriptors */
315#define EXTSTS_UDPERR   0x00400000
316#define EXTSTS_UDPPKT	0x00200000
317#define EXTSTS_TCPERR   0x00100000
318#define EXTSTS_TCPPKT	0x00080000
319#define EXTSTS_IPERR    0x00040000
320#define EXTSTS_IPPKT	0x00020000
321
322
323/* speed status */
324#define SPDSTS_POLARITY	(CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS | (lnksts ? CFGR_LNKSTS : 0))
325
326#endif /* __DEV_NS_GIGE_REG_H__ */
327