ns_gige.hh revision 1354
14120Sgblack@eecs.umich.edu/* 24120Sgblack@eecs.umich.edu * Copyright (c) 2004 The Regents of The University of Michigan 34120Sgblack@eecs.umich.edu * All rights reserved. 44120Sgblack@eecs.umich.edu * 54120Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64120Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 74120Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94120Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114120Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124120Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134120Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144120Sgblack@eecs.umich.edu * this software without specific prior written permission. 154120Sgblack@eecs.umich.edu * 164120Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174120Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184120Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194120Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274120Sgblack@eecs.umich.edu */ 284120Sgblack@eecs.umich.edu 294120Sgblack@eecs.umich.edu/* @file 304120Sgblack@eecs.umich.edu * Device module for modelling the National Semiconductor 314120Sgblack@eecs.umich.edu * DP83820 ethernet controller 324120Sgblack@eecs.umich.edu */ 334120Sgblack@eecs.umich.edu 344120Sgblack@eecs.umich.edu#ifndef __DEV_NS_GIGE_HH__ 354120Sgblack@eecs.umich.edu#define __DEV_NS_GIGE_HH__ 364120Sgblack@eecs.umich.edu 374120Sgblack@eecs.umich.edu#include "base/inet.hh" 384120Sgblack@eecs.umich.edu#include "base/statistics.hh" 394120Sgblack@eecs.umich.edu#include "dev/etherint.hh" 404120Sgblack@eecs.umich.edu#include "dev/etherpkt.hh" 414120Sgblack@eecs.umich.edu#include "dev/io_device.hh" 424120Sgblack@eecs.umich.edu#include "dev/ns_gige_reg.h" 434120Sgblack@eecs.umich.edu#include "dev/pcidev.hh" 444120Sgblack@eecs.umich.edu#include "dev/pktfifo.hh" 454120Sgblack@eecs.umich.edu#include "mem/bus/bus.hh" 464120Sgblack@eecs.umich.edu#include "sim/eventq.hh" 474120Sgblack@eecs.umich.edu 484120Sgblack@eecs.umich.edu/** 494120Sgblack@eecs.umich.edu * Ethernet device registers 504120Sgblack@eecs.umich.edu */ 514120Sgblack@eecs.umich.edustruct dp_regs { 524120Sgblack@eecs.umich.edu uint32_t command; 534120Sgblack@eecs.umich.edu uint32_t config; 544120Sgblack@eecs.umich.edu uint32_t mear; 554120Sgblack@eecs.umich.edu uint32_t ptscr; 564120Sgblack@eecs.umich.edu uint32_t isr; 574120Sgblack@eecs.umich.edu uint32_t imr; 584120Sgblack@eecs.umich.edu uint32_t ier; 594120Sgblack@eecs.umich.edu uint32_t ihr; 604120Sgblack@eecs.umich.edu uint32_t txdp; 615647Sgblack@eecs.umich.edu uint32_t txdp_hi; 625086Sgblack@eecs.umich.edu uint32_t txcfg; 635654Sgblack@eecs.umich.edu uint32_t gpior; 645086Sgblack@eecs.umich.edu uint32_t rxdp; 655648Sgblack@eecs.umich.edu uint32_t rxdp_hi; 665651Sgblack@eecs.umich.edu uint32_t rxcfg; 675647Sgblack@eecs.umich.edu uint32_t pqcr; 685647Sgblack@eecs.umich.edu uint32_t wcsr; 695647Sgblack@eecs.umich.edu uint32_t pcr; 705647Sgblack@eecs.umich.edu uint32_t rfcr; 714120Sgblack@eecs.umich.edu uint32_t rfdr; 724120Sgblack@eecs.umich.edu uint32_t srr; 734120Sgblack@eecs.umich.edu uint32_t mibc; 745086Sgblack@eecs.umich.edu uint32_t vrcr; 755651Sgblack@eecs.umich.edu uint32_t vtcr; 765086Sgblack@eecs.umich.edu uint32_t vdr; 775647Sgblack@eecs.umich.edu uint32_t ccsr; 785654Sgblack@eecs.umich.edu uint32_t tbicr; 795647Sgblack@eecs.umich.edu uint32_t tbisr; 805654Sgblack@eecs.umich.edu uint32_t tanar; 815654Sgblack@eecs.umich.edu uint32_t tanlpar; 825654Sgblack@eecs.umich.edu uint32_t taner; 835654Sgblack@eecs.umich.edu uint32_t tesr; 845648Sgblack@eecs.umich.edu}; 855648Sgblack@eecs.umich.edu 865647Sgblack@eecs.umich.edustruct dp_rom { 875647Sgblack@eecs.umich.edu /** 885647Sgblack@eecs.umich.edu * for perfect match memory. 895647Sgblack@eecs.umich.edu * the linux driver doesn't use any other ROM 905647Sgblack@eecs.umich.edu */ 915647Sgblack@eecs.umich.edu uint8_t perfectMatch[ETH_ADDR_LEN]; 925647Sgblack@eecs.umich.edu}; 935647Sgblack@eecs.umich.edu 945647Sgblack@eecs.umich.educlass IntrControl; 955647Sgblack@eecs.umich.educlass NSGigEInt; 965647Sgblack@eecs.umich.educlass PhysicalMemory; 975647Sgblack@eecs.umich.educlass BaseInterface; 985647Sgblack@eecs.umich.educlass HierParams; 995647Sgblack@eecs.umich.educlass Bus; 1005647Sgblack@eecs.umich.educlass PciConfigAll; 1015654Sgblack@eecs.umich.edu 1025654Sgblack@eecs.umich.edu/** 1035654Sgblack@eecs.umich.edu * NS DP82830 Ethernet device model 1045654Sgblack@eecs.umich.edu */ 1055654Sgblack@eecs.umich.educlass NSGigE : public PciDev 1065654Sgblack@eecs.umich.edu{ 1075654Sgblack@eecs.umich.edu public: 1085654Sgblack@eecs.umich.edu /** Transmit State Machine states */ 1095654Sgblack@eecs.umich.edu enum TxState 1105654Sgblack@eecs.umich.edu { 1115654Sgblack@eecs.umich.edu txIdle, 1125654Sgblack@eecs.umich.edu txDescRefr, 1135654Sgblack@eecs.umich.edu txDescRead, 1145654Sgblack@eecs.umich.edu txFifoBlock, 1155654Sgblack@eecs.umich.edu txFragRead, 1165654Sgblack@eecs.umich.edu txDescWrite, 1175654Sgblack@eecs.umich.edu txAdvance 1185654Sgblack@eecs.umich.edu }; 1195654Sgblack@eecs.umich.edu 1205654Sgblack@eecs.umich.edu /** Receive State Machine States */ 1215654Sgblack@eecs.umich.edu enum RxState 1225654Sgblack@eecs.umich.edu { 1235654Sgblack@eecs.umich.edu rxIdle, 1245654Sgblack@eecs.umich.edu rxDescRefr, 1255654Sgblack@eecs.umich.edu rxDescRead, 1265654Sgblack@eecs.umich.edu rxFifoBlock, 1275654Sgblack@eecs.umich.edu rxFragWrite, 1285654Sgblack@eecs.umich.edu rxDescWrite, 1295654Sgblack@eecs.umich.edu rxAdvance 1305654Sgblack@eecs.umich.edu }; 1315654Sgblack@eecs.umich.edu 1325654Sgblack@eecs.umich.edu enum DmaState 1335654Sgblack@eecs.umich.edu { 1345654Sgblack@eecs.umich.edu dmaIdle, 1355654Sgblack@eecs.umich.edu dmaReading, 1365654Sgblack@eecs.umich.edu dmaWriting, 1375654Sgblack@eecs.umich.edu dmaReadWaiting, 1385654Sgblack@eecs.umich.edu dmaWriteWaiting 1395654Sgblack@eecs.umich.edu }; 1405654Sgblack@eecs.umich.edu 1415654Sgblack@eecs.umich.edu private: 1425654Sgblack@eecs.umich.edu Addr addr; 1435654Sgblack@eecs.umich.edu static const Addr size = sizeof(dp_regs); 1445654Sgblack@eecs.umich.edu 1455654Sgblack@eecs.umich.edu protected: 1465654Sgblack@eecs.umich.edu typedef std::deque<PacketPtr> pktbuf_t; 1475654Sgblack@eecs.umich.edu typedef pktbuf_t::iterator pktiter_t; 1485654Sgblack@eecs.umich.edu 1495086Sgblack@eecs.umich.edu /** device register file */ 1505654Sgblack@eecs.umich.edu dp_regs regs; 1515654Sgblack@eecs.umich.edu dp_rom rom; 1525654Sgblack@eecs.umich.edu 1535647Sgblack@eecs.umich.edu /** pci settings */ 1545647Sgblack@eecs.umich.edu bool ioEnable; 1555648Sgblack@eecs.umich.edu#if 0 1565648Sgblack@eecs.umich.edu bool memEnable; 1575648Sgblack@eecs.umich.edu bool bmEnable; 1585648Sgblack@eecs.umich.edu#endif 1595648Sgblack@eecs.umich.edu 1605647Sgblack@eecs.umich.edu /*** BASIC STRUCTURES FOR TX/RX ***/ 1615647Sgblack@eecs.umich.edu /* Data FIFOs */ 1625086Sgblack@eecs.umich.edu PacketFifo txFifo; 1635647Sgblack@eecs.umich.edu PacketFifo rxFifo; 1645647Sgblack@eecs.umich.edu 1655647Sgblack@eecs.umich.edu /** various helper vars */ 1665654Sgblack@eecs.umich.edu PacketPtr txPacket; 1675654Sgblack@eecs.umich.edu PacketPtr rxPacket; 1685654Sgblack@eecs.umich.edu uint8_t *txPacketBufPtr; 1695648Sgblack@eecs.umich.edu uint8_t *rxPacketBufPtr; 1705648Sgblack@eecs.umich.edu uint32_t txXferLen; 1715651Sgblack@eecs.umich.edu uint32_t rxXferLen; 1725647Sgblack@eecs.umich.edu bool rxDmaFree; 1735648Sgblack@eecs.umich.edu bool txDmaFree; 1745648Sgblack@eecs.umich.edu 1755648Sgblack@eecs.umich.edu /** DescCaches */ 1765648Sgblack@eecs.umich.edu ns_desc txDescCache; 1775648Sgblack@eecs.umich.edu ns_desc rxDescCache; 1785648Sgblack@eecs.umich.edu 1795647Sgblack@eecs.umich.edu /* tx State Machine */ 1805651Sgblack@eecs.umich.edu TxState txState; 1815651Sgblack@eecs.umich.edu bool txEnable; 1825651Sgblack@eecs.umich.edu 1835651Sgblack@eecs.umich.edu /** Current Transmit Descriptor Done */ 1845651Sgblack@eecs.umich.edu bool CTDD; 1855651Sgblack@eecs.umich.edu /** halt the tx state machine after next packet */ 1865651Sgblack@eecs.umich.edu bool txHalt; 1875654Sgblack@eecs.umich.edu /** ptr to the next byte in the current fragment */ 1885654Sgblack@eecs.umich.edu Addr txFragPtr; 1895654Sgblack@eecs.umich.edu /** count of bytes remaining in the current descriptor */ 1905654Sgblack@eecs.umich.edu uint32_t txDescCnt; 1915654Sgblack@eecs.umich.edu DmaState txDmaState; 1925654Sgblack@eecs.umich.edu 1935654Sgblack@eecs.umich.edu /** rx State Machine */ 1945654Sgblack@eecs.umich.edu RxState rxState; 1955654Sgblack@eecs.umich.edu bool rxEnable; 1965654Sgblack@eecs.umich.edu 1975654Sgblack@eecs.umich.edu /** Current Receive Descriptor Done */ 1985648Sgblack@eecs.umich.edu bool CRDD; 1995648Sgblack@eecs.umich.edu /** num of bytes in the current packet being drained from rxDataFifo */ 2005648Sgblack@eecs.umich.edu uint32_t rxPktBytes; 2015647Sgblack@eecs.umich.edu /** halt the rx state machine after current packet */ 2025648Sgblack@eecs.umich.edu bool rxHalt; 2035648Sgblack@eecs.umich.edu /** ptr to the next byte in current fragment */ 2045648Sgblack@eecs.umich.edu Addr rxFragPtr; 2055654Sgblack@eecs.umich.edu /** count of bytes remaining in the current descriptor */ 2065654Sgblack@eecs.umich.edu uint32_t rxDescCnt; 2075654Sgblack@eecs.umich.edu DmaState rxDmaState; 2085654Sgblack@eecs.umich.edu 2095651Sgblack@eecs.umich.edu bool extstsEnable; 2105648Sgblack@eecs.umich.edu 2115648Sgblack@eecs.umich.edu protected: 2125648Sgblack@eecs.umich.edu Tick dmaReadDelay; 2135654Sgblack@eecs.umich.edu Tick dmaWriteDelay; 2145647Sgblack@eecs.umich.edu 2155647Sgblack@eecs.umich.edu Tick dmaReadFactor; 2165654Sgblack@eecs.umich.edu Tick dmaWriteFactor; 2175654Sgblack@eecs.umich.edu 2185086Sgblack@eecs.umich.edu void *rxDmaData; 2195086Sgblack@eecs.umich.edu Addr rxDmaAddr; 2205654Sgblack@eecs.umich.edu int rxDmaLen; 2215654Sgblack@eecs.umich.edu bool doRxDmaRead(); 2225654Sgblack@eecs.umich.edu bool doRxDmaWrite(); 2235651Sgblack@eecs.umich.edu void rxDmaReadCopy(); 2245654Sgblack@eecs.umich.edu void rxDmaWriteCopy(); 2255654Sgblack@eecs.umich.edu 2265654Sgblack@eecs.umich.edu void *txDmaData; 2275086Sgblack@eecs.umich.edu Addr txDmaAddr; 2285654Sgblack@eecs.umich.edu int txDmaLen; 2295654Sgblack@eecs.umich.edu bool doTxDmaRead(); 2305654Sgblack@eecs.umich.edu bool doTxDmaWrite(); 2315086Sgblack@eecs.umich.edu void txDmaReadCopy(); 2325086Sgblack@eecs.umich.edu void txDmaWriteCopy(); 2335086Sgblack@eecs.umich.edu 2345133Sgblack@eecs.umich.edu void rxDmaReadDone(); 2355086Sgblack@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>; 2365086Sgblack@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent; 2375086Sgblack@eecs.umich.edu 2385086Sgblack@eecs.umich.edu void rxDmaWriteDone(); 2395133Sgblack@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>; 2405086Sgblack@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent; 2415654Sgblack@eecs.umich.edu 2425654Sgblack@eecs.umich.edu void txDmaReadDone(); 2435654Sgblack@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>; 2445654Sgblack@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent; 2455654Sgblack@eecs.umich.edu 2465654Sgblack@eecs.umich.edu void txDmaWriteDone(); 2475654Sgblack@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>; 2485654Sgblack@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent; 2495654Sgblack@eecs.umich.edu 2505654Sgblack@eecs.umich.edu bool dmaDescFree; 2515654Sgblack@eecs.umich.edu bool dmaDataFree; 2525654Sgblack@eecs.umich.edu 2535654Sgblack@eecs.umich.edu 2545654Sgblack@eecs.umich.edu protected: 2555654Sgblack@eecs.umich.edu Tick txDelay; 2565654Sgblack@eecs.umich.edu Tick rxDelay; 2575654Sgblack@eecs.umich.edu 2585654Sgblack@eecs.umich.edu void txReset(); 2595654Sgblack@eecs.umich.edu void rxReset(); 2605086Sgblack@eecs.umich.edu void regsReset(); 2615086Sgblack@eecs.umich.edu 2624120Sgblack@eecs.umich.edu void rxKick(); 2634120Sgblack@eecs.umich.edu Tick rxKickTick; 2644120Sgblack@eecs.umich.edu typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent; 265 friend void RxKickEvent::process(); 266 267 void txKick(); 268 Tick txKickTick; 269 typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent; 270 friend void TxKickEvent::process(); 271 272 /** 273 * Retransmit event 274 */ 275 void transmit(); 276 void txEventTransmit() 277 { 278 transmit(); 279 if (txState == txFifoBlock) 280 txKick(); 281 } 282 typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent; 283 friend void TxEvent::process(); 284 TxEvent txEvent; 285 286 void txDump() const; 287 void rxDump() const; 288 289 /** 290 * receive address filter 291 */ 292 bool rxFilterEnable; 293 bool rxFilter(const PacketPtr &packet); 294 bool acceptBroadcast; 295 bool acceptMulticast; 296 bool acceptUnicast; 297 bool acceptPerfect; 298 bool acceptArp; 299 300 PhysicalMemory *physmem; 301 302 /** 303 * Interrupt management 304 */ 305 IntrControl *intctrl; 306 void devIntrPost(uint32_t interrupts); 307 void devIntrClear(uint32_t interrupts); 308 void devIntrChangeMask(); 309 310 Tick intrDelay; 311 Tick intrTick; 312 bool cpuPendingIntr; 313 void cpuIntrPost(Tick when); 314 void cpuInterrupt(); 315 void cpuIntrClear(); 316 317 typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent; 318 friend void IntrEvent::process(); 319 IntrEvent *intrEvent; 320 NSGigEInt *interface; 321 322 public: 323 struct Params : public PciDev::Params 324 { 325 PhysicalMemory *pmem; 326 HierParams *hier; 327 Bus *header_bus; 328 Bus *payload_bus; 329 Tick intr_delay; 330 Tick tx_delay; 331 Tick rx_delay; 332 Tick pio_latency; 333 bool dma_desc_free; 334 bool dma_data_free; 335 Tick dma_read_delay; 336 Tick dma_write_delay; 337 Tick dma_read_factor; 338 Tick dma_write_factor; 339 bool rx_filter; 340 Net::EthAddr eaddr; 341 uint32_t tx_fifo_size; 342 uint32_t rx_fifo_size; 343 }; 344 345 NSGigE(Params *params); 346 ~NSGigE(); 347 const Params *params() const { return (const Params *)_params; } 348 349 virtual void WriteConfig(int offset, int size, uint32_t data); 350 virtual void ReadConfig(int offset, int size, uint8_t *data); 351 352 virtual Fault read(MemReqPtr &req, uint8_t *data); 353 virtual Fault write(MemReqPtr &req, const uint8_t *data); 354 355 bool cpuIntrPending() const; 356 void cpuIntrAck() { cpuIntrClear(); } 357 358 bool recvPacket(PacketPtr packet); 359 void transferDone(); 360 361 void setInterface(NSGigEInt *i) { assert(!interface); interface = i; } 362 363 virtual void serialize(std::ostream &os); 364 virtual void unserialize(Checkpoint *cp, const std::string §ion); 365 366 public: 367 void regStats(); 368 369 private: 370 Stats::Scalar<> txBytes; 371 Stats::Scalar<> rxBytes; 372 Stats::Scalar<> txPackets; 373 Stats::Scalar<> rxPackets; 374 Stats::Scalar<> txIpChecksums; 375 Stats::Scalar<> rxIpChecksums; 376 Stats::Scalar<> txTcpChecksums; 377 Stats::Scalar<> rxTcpChecksums; 378 Stats::Scalar<> txUdpChecksums; 379 Stats::Scalar<> rxUdpChecksums; 380 Stats::Scalar<> descDmaReads; 381 Stats::Scalar<> descDmaWrites; 382 Stats::Scalar<> descDmaRdBytes; 383 Stats::Scalar<> descDmaWrBytes; 384 Stats::Formula txBandwidth; 385 Stats::Formula rxBandwidth; 386 Stats::Formula txPacketRate; 387 Stats::Formula rxPacketRate; 388 Stats::Scalar<> postedSwi; 389 Stats::Formula coalescedSwi; 390 Stats::Scalar<> totalSwi; 391 Stats::Scalar<> postedRxIdle; 392 Stats::Formula coalescedRxIdle; 393 Stats::Scalar<> totalRxIdle; 394 Stats::Scalar<> postedRxOk; 395 Stats::Formula coalescedRxOk; 396 Stats::Scalar<> totalRxOk; 397 Stats::Scalar<> postedRxDesc; 398 Stats::Formula coalescedRxDesc; 399 Stats::Scalar<> totalRxDesc; 400 Stats::Scalar<> postedTxOk; 401 Stats::Formula coalescedTxOk; 402 Stats::Scalar<> totalTxOk; 403 Stats::Scalar<> postedTxIdle; 404 Stats::Formula coalescedTxIdle; 405 Stats::Scalar<> totalTxIdle; 406 Stats::Scalar<> postedTxDesc; 407 Stats::Formula coalescedTxDesc; 408 Stats::Scalar<> totalTxDesc; 409 Stats::Scalar<> postedRxOrn; 410 Stats::Formula coalescedRxOrn; 411 Stats::Scalar<> totalRxOrn; 412 Stats::Formula coalescedTotal; 413 Stats::Scalar<> postedInterrupts; 414 Stats::Scalar<> droppedPackets; 415 416 public: 417 Tick cacheAccess(MemReqPtr &req); 418}; 419 420/* 421 * Ethernet Interface for an Ethernet Device 422 */ 423class NSGigEInt : public EtherInt 424{ 425 private: 426 NSGigE *dev; 427 428 public: 429 NSGigEInt(const std::string &name, NSGigE *d) 430 : EtherInt(name), dev(d) { dev->setInterface(this); } 431 432 virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); } 433 virtual void sendDone() { dev->transferDone(); } 434}; 435 436#endif // __DEV_NS_GIGE_HH__ 437