ns_gige.hh revision 9339
12SN/A/* 211147Smitch.hayenga@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 39920Syasuko.eckert@amd.com * All rights reserved. 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67338SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77338SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97338SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117338SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127338SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137338SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147338SAli.Saidi@ARM.com * this software without specific prior written permission. 151762SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A * 282SN/A * Authors: Nathan Binkert 292SN/A * Lisa Hsu 302SN/A */ 312SN/A 322SN/A/** @file 332SN/A * Device module for modelling the National Semiconductor 342SN/A * DP83820 ethernet controller 352SN/A */ 362SN/A 372SN/A#ifndef __DEV_NS_GIGE_HH__ 382SN/A#define __DEV_NS_GIGE_HH__ 392SN/A 402665Ssaidi@eecs.umich.edu#include "base/inet.hh" 412665Ssaidi@eecs.umich.edu#include "dev/etherdevice.hh" 422SN/A#include "dev/etherint.hh" 432SN/A#include "dev/etherpkt.hh" 448779Sgblack@eecs.umich.edu#include "dev/io_device.hh" 458779Sgblack@eecs.umich.edu#include "dev/ns_gige_reg.h" 468779Sgblack@eecs.umich.edu#include "dev/pktfifo.hh" 472439SN/A#include "params/NSGigE.hh" 488779Sgblack@eecs.umich.edu#include "sim/eventq.hh" 498229Snate@binkert.org 506216Snate@binkert.org// Hash filtering constants 51146SN/Aconst uint16_t FHASH_ADDR = 0x100; 52146SN/Aconst uint16_t FHASH_SIZE = 0x100; 53146SN/A 54146SN/A// EEPROM constants 55146SN/Aconst uint8_t EEPROM_READ = 0x2; 566216Snate@binkert.orgconst uint8_t EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM 576658Snate@binkert.orgconst uint8_t EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2 588229Snate@binkert.orgconst uint8_t EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1 591717SN/Aconst uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0 608887Sgeoffrey.blake@arm.com 618887Sgeoffrey.blake@arm.com/** 62146SN/A * Ethernet device registers 6310061Sandreas@sandberg.pp.se */ 641977SN/Astruct dp_regs { 6511147Smitch.hayenga@arm.com uint32_t command; 662683Sktlim@umich.edu uint32_t config; 671717SN/A uint32_t mear; 68146SN/A uint32_t ptscr; 692683Sktlim@umich.edu uint32_t isr; 708232Snate@binkert.org uint32_t imr; 718232Snate@binkert.org uint32_t ier; 728232Snate@binkert.org uint32_t ihr; 738779Sgblack@eecs.umich.edu uint32_t txdp; 743348Sbinkertn@umich.edu uint32_t txdp_hi; 756105Ssteve.reinhardt@amd.com uint32_t txcfg; 766216Snate@binkert.org uint32_t gpior; 772036SN/A uint32_t rxdp; 78146SN/A uint32_t rxdp_hi; 798817Sgblack@eecs.umich.edu uint32_t rxcfg; 808793Sgblack@eecs.umich.edu uint32_t pqcr; 8156SN/A uint32_t wcsr; 8256SN/A uint32_t pcr; 83695SN/A uint32_t rfcr; 842901Ssaidi@eecs.umich.edu uint32_t rfdr; 852SN/A uint32_t brar; 862SN/A uint32_t brdr; 872449SN/A uint32_t srr; 881355SN/A uint32_t mibc; 895529Snate@binkert.org uint32_t vrcr; 9010061Sandreas@sandberg.pp.se uint32_t vtcr; 9111147Smitch.hayenga@arm.com uint32_t vdr; 9210061Sandreas@sandberg.pp.se uint32_t ccsr; 9311147Smitch.hayenga@arm.com uint32_t tbicr; 9411147Smitch.hayenga@arm.com uint32_t tbisr; 9511147Smitch.hayenga@arm.com uint32_t tanar; 96224SN/A uint32_t tanlpar; 9711147Smitch.hayenga@arm.com uint32_t taner; 982SN/A uint32_t tesr; 9911147Smitch.hayenga@arm.com}; 10011147Smitch.hayenga@arm.com 10111147Smitch.hayenga@arm.comstruct dp_rom { 10211147Smitch.hayenga@arm.com /** 10311147Smitch.hayenga@arm.com * for perfect match memory. 10411147Smitch.hayenga@arm.com * the linux driver doesn't use any other ROM 10511147Smitch.hayenga@arm.com */ 10611147Smitch.hayenga@arm.com uint8_t perfectMatch[ETH_ADDR_LEN]; 10711147Smitch.hayenga@arm.com 10811147Smitch.hayenga@arm.com /** 10911147Smitch.hayenga@arm.com * for hash table memory. 11011147Smitch.hayenga@arm.com * used by the freebsd driver 1112SN/A */ 1128733Sgeoffrey.blake@arm.com uint8_t filterHash[FHASH_SIZE]; 11311147Smitch.hayenga@arm.com}; 11411147Smitch.hayenga@arm.com 11511147Smitch.hayenga@arm.comclass NSGigEInt; 1168733Sgeoffrey.blake@arm.comclass Packet; 1178733Sgeoffrey.blake@arm.com 1188733Sgeoffrey.blake@arm.com/** 1198733Sgeoffrey.blake@arm.com * NS DP83820 Ethernet device model 12011147Smitch.hayenga@arm.com */ 12111147Smitch.hayenga@arm.comclass NSGigE : public EtherDevBase 1228733Sgeoffrey.blake@arm.com{ 1238733Sgeoffrey.blake@arm.com public: 1248733Sgeoffrey.blake@arm.com /** Transmit State Machine states */ 12511147Smitch.hayenga@arm.com enum TxState 1268733Sgeoffrey.blake@arm.com { 12711147Smitch.hayenga@arm.com txIdle, 12811147Smitch.hayenga@arm.com txDescRefr, 12911147Smitch.hayenga@arm.com txDescRead, 13011147Smitch.hayenga@arm.com txFifoBlock, 1312SN/A txFragRead, 13211147Smitch.hayenga@arm.com txDescWrite, 13311147Smitch.hayenga@arm.com txAdvance 13411147Smitch.hayenga@arm.com }; 1354377Sgblack@eecs.umich.edu 13611147Smitch.hayenga@arm.com /** Receive State Machine States */ 13711147Smitch.hayenga@arm.com enum RxState 13811147Smitch.hayenga@arm.com { 13911147Smitch.hayenga@arm.com rxIdle, 14011147Smitch.hayenga@arm.com rxDescRefr, 14111147Smitch.hayenga@arm.com rxDescRead, 1425169Ssaidi@eecs.umich.edu rxFifoBlock, 14311147Smitch.hayenga@arm.com rxFragWrite, 14411147Smitch.hayenga@arm.com rxDescWrite, 14511147Smitch.hayenga@arm.com rxAdvance 14611147Smitch.hayenga@arm.com }; 14711147Smitch.hayenga@arm.com 14811147Smitch.hayenga@arm.com enum DmaState 14911147Smitch.hayenga@arm.com { 15011147Smitch.hayenga@arm.com dmaIdle, 15111147Smitch.hayenga@arm.com dmaReading, 15211147Smitch.hayenga@arm.com dmaWriting, 15311147Smitch.hayenga@arm.com dmaReadWaiting, 15411147Smitch.hayenga@arm.com dmaWriteWaiting 15511147Smitch.hayenga@arm.com }; 15611147Smitch.hayenga@arm.com 15711147Smitch.hayenga@arm.com /** EEPROM State Machine States */ 15811147Smitch.hayenga@arm.com enum EEPROMState 15911147Smitch.hayenga@arm.com { 16011147Smitch.hayenga@arm.com eepromStart, 16111147Smitch.hayenga@arm.com eepromGetOpcode, 16211147Smitch.hayenga@arm.com eepromGetAddress, 16311147Smitch.hayenga@arm.com eepromRead 16411147Smitch.hayenga@arm.com }; 16511147Smitch.hayenga@arm.com 16611147Smitch.hayenga@arm.com protected: 16711147Smitch.hayenga@arm.com /** device register file */ 16811147Smitch.hayenga@arm.com dp_regs regs; 16911147Smitch.hayenga@arm.com dp_rom rom; 17011147Smitch.hayenga@arm.com 17111147Smitch.hayenga@arm.com /** pci settings */ 17211147Smitch.hayenga@arm.com bool ioEnable; 17311147Smitch.hayenga@arm.com#if 0 17411147Smitch.hayenga@arm.com bool memEnable; 17511147Smitch.hayenga@arm.com bool bmEnable; 17611147Smitch.hayenga@arm.com#endif 17711147Smitch.hayenga@arm.com 17811147Smitch.hayenga@arm.com /*** BASIC STRUCTURES FOR TX/RX ***/ 17911147Smitch.hayenga@arm.com /* Data FIFOs */ 18011147Smitch.hayenga@arm.com PacketFifo txFifo; 18111147Smitch.hayenga@arm.com PacketFifo rxFifo; 18211147Smitch.hayenga@arm.com 18311147Smitch.hayenga@arm.com /** various helper vars */ 18411147Smitch.hayenga@arm.com EthPacketPtr txPacket; 18511147Smitch.hayenga@arm.com EthPacketPtr rxPacket; 18611147Smitch.hayenga@arm.com uint8_t *txPacketBufPtr; 18711147Smitch.hayenga@arm.com uint8_t *rxPacketBufPtr; 18811147Smitch.hayenga@arm.com uint32_t txXferLen; 18911147Smitch.hayenga@arm.com uint32_t rxXferLen; 19011147Smitch.hayenga@arm.com bool rxDmaFree; 19111147Smitch.hayenga@arm.com bool txDmaFree; 19211147Smitch.hayenga@arm.com 19311147Smitch.hayenga@arm.com /** DescCaches */ 19411147Smitch.hayenga@arm.com ns_desc32 txDesc32; 19511147Smitch.hayenga@arm.com ns_desc32 rxDesc32; 19611147Smitch.hayenga@arm.com ns_desc64 txDesc64; 19711147Smitch.hayenga@arm.com ns_desc64 rxDesc64; 19811147Smitch.hayenga@arm.com 19911147Smitch.hayenga@arm.com /* tx State Machine */ 20011147Smitch.hayenga@arm.com TxState txState; 20111147Smitch.hayenga@arm.com bool txEnable; 20211147Smitch.hayenga@arm.com 20311147Smitch.hayenga@arm.com /** Current Transmit Descriptor Done */ 20411147Smitch.hayenga@arm.com bool CTDD; 20511147Smitch.hayenga@arm.com /** halt the tx state machine after next packet */ 2062SN/A bool txHalt; 2072SN/A /** ptr to the next byte in the current fragment */ 2082623SN/A Addr txFragPtr; 2092SN/A /** count of bytes remaining in the current descriptor */ 2102SN/A uint32_t txDescCnt; 2112SN/A DmaState txDmaState; 212180SN/A 2138737Skoansin.tan@gmail.com /** rx State Machine */ 214393SN/A RxState rxState; 215393SN/A bool rxEnable; 216393SN/A 217393SN/A /** Current Receive Descriptor Done */ 218384SN/A bool CRDD; 219189SN/A /** num of bytes in the current packet being drained from rxDataFifo */ 220189SN/A uint32_t rxPktBytes; 2212623SN/A /** halt the rx state machine after current packet */ 2222SN/A bool rxHalt; 223729SN/A /** ptr to the next byte in current fragment */ 224334SN/A Addr rxFragPtr; 2252SN/A /** count of bytes remaining in the current descriptor */ 2262SN/A uint32_t rxDescCnt; 22711147Smitch.hayenga@arm.com DmaState rxDmaState; 22811147Smitch.hayenga@arm.com 2298834Satgutier@umich.edu bool extstsEnable; 23011147Smitch.hayenga@arm.com 23111147Smitch.hayenga@arm.com /** EEPROM State Machine */ 23211147Smitch.hayenga@arm.com EEPROMState eepromState; 2332SN/A bool eepromClk; 23411147Smitch.hayenga@arm.com uint8_t eepromBitsToRx; 23511147Smitch.hayenga@arm.com uint8_t eepromOpcode; 23611147Smitch.hayenga@arm.com uint8_t eepromAddress; 23711147Smitch.hayenga@arm.com uint16_t eepromData; 2387897Shestness@cs.utexas.edu 23911147Smitch.hayenga@arm.com protected: 24011147Smitch.hayenga@arm.com Tick dmaReadDelay; 24111147Smitch.hayenga@arm.com Tick dmaWriteDelay; 24211147Smitch.hayenga@arm.com 2437897Shestness@cs.utexas.edu Tick dmaReadFactor; 24411147Smitch.hayenga@arm.com Tick dmaWriteFactor; 24511147Smitch.hayenga@arm.com 24611147Smitch.hayenga@arm.com void *rxDmaData; 24711147Smitch.hayenga@arm.com Addr rxDmaAddr; 2487897Shestness@cs.utexas.edu int rxDmaLen; 24911147Smitch.hayenga@arm.com bool doRxDmaRead(); 25011147Smitch.hayenga@arm.com bool doRxDmaWrite(); 25111147Smitch.hayenga@arm.com 25211147Smitch.hayenga@arm.com void *txDmaData; 2537897Shestness@cs.utexas.edu Addr txDmaAddr; 25411147Smitch.hayenga@arm.com int txDmaLen; 25511147Smitch.hayenga@arm.com bool doTxDmaRead(); 25611147Smitch.hayenga@arm.com bool doTxDmaWrite(); 25711147Smitch.hayenga@arm.com 2587897Shestness@cs.utexas.edu void rxDmaReadDone(); 25911147Smitch.hayenga@arm.com friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>; 26011147Smitch.hayenga@arm.com EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent; 26111147Smitch.hayenga@arm.com 26211147Smitch.hayenga@arm.com void rxDmaWriteDone(); 2637897Shestness@cs.utexas.edu friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>; 26411147Smitch.hayenga@arm.com EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent; 26511147Smitch.hayenga@arm.com 26611147Smitch.hayenga@arm.com void txDmaReadDone(); 26711147Smitch.hayenga@arm.com friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>; 2687897Shestness@cs.utexas.edu EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent; 26911147Smitch.hayenga@arm.com 27011147Smitch.hayenga@arm.com void txDmaWriteDone(); 27111147Smitch.hayenga@arm.com friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>; 27211147Smitch.hayenga@arm.com EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent; 2737897Shestness@cs.utexas.edu 27411147Smitch.hayenga@arm.com bool dmaDescFree; 27511147Smitch.hayenga@arm.com bool dmaDataFree; 27611147Smitch.hayenga@arm.com 27711147Smitch.hayenga@arm.com protected: 2787897Shestness@cs.utexas.edu Tick txDelay; 27911147Smitch.hayenga@arm.com Tick rxDelay; 28011147Smitch.hayenga@arm.com 28111147Smitch.hayenga@arm.com void txReset(); 28211147Smitch.hayenga@arm.com void rxReset(); 2837897Shestness@cs.utexas.edu void regsReset(); 28411147Smitch.hayenga@arm.com 28511147Smitch.hayenga@arm.com void rxKick(); 28611147Smitch.hayenga@arm.com Tick rxKickTick; 28711147Smitch.hayenga@arm.com typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent; 2889920Syasuko.eckert@amd.com friend void RxKickEvent::process(); 28911147Smitch.hayenga@arm.com RxKickEvent rxKickEvent; 29011147Smitch.hayenga@arm.com 29111147Smitch.hayenga@arm.com void txKick(); 29211147Smitch.hayenga@arm.com Tick txKickTick; 2939920Syasuko.eckert@amd.com typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent; 29411147Smitch.hayenga@arm.com friend void TxKickEvent::process(); 29511147Smitch.hayenga@arm.com TxKickEvent txKickEvent; 29611147Smitch.hayenga@arm.com 29711147Smitch.hayenga@arm.com void eepromKick(); 29811147Smitch.hayenga@arm.com 2997897Shestness@cs.utexas.edu /** 30011147Smitch.hayenga@arm.com * Retransmit event 30111147Smitch.hayenga@arm.com */ 30211147Smitch.hayenga@arm.com void transmit(); 30311147Smitch.hayenga@arm.com void txEventTransmit() 30411147Smitch.hayenga@arm.com { 3057897Shestness@cs.utexas.edu transmit(); 30611147Smitch.hayenga@arm.com if (txState == txFifoBlock) 30711147Smitch.hayenga@arm.com txKick(); 30811147Smitch.hayenga@arm.com } 30911147Smitch.hayenga@arm.com typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent; 3102SN/A friend void TxEvent::process(); 31111147Smitch.hayenga@arm.com TxEvent txEvent; 31211147Smitch.hayenga@arm.com 31311147Smitch.hayenga@arm.com void txDump() const; 31411147Smitch.hayenga@arm.com void rxDump() const; 3151001SN/A 31611147Smitch.hayenga@arm.com /** 31711147Smitch.hayenga@arm.com * receive address filter 31811147Smitch.hayenga@arm.com */ 31911147Smitch.hayenga@arm.com bool rxFilterEnable; 3202SN/A bool rxFilter(const EthPacketPtr &packet); 32111147Smitch.hayenga@arm.com bool acceptBroadcast; 32211147Smitch.hayenga@arm.com bool acceptMulticast; 32311147Smitch.hayenga@arm.com bool acceptUnicast; 32411147Smitch.hayenga@arm.com bool acceptPerfect; 3257897Shestness@cs.utexas.edu bool acceptArp; 32611147Smitch.hayenga@arm.com bool multicastHashEnable; 32711147Smitch.hayenga@arm.com 32811147Smitch.hayenga@arm.com /** 32911147Smitch.hayenga@arm.com * Interrupt management 3307897Shestness@cs.utexas.edu */ 33111147Smitch.hayenga@arm.com void devIntrPost(uint32_t interrupts); 33211147Smitch.hayenga@arm.com void devIntrClear(uint32_t interrupts); 33311147Smitch.hayenga@arm.com void devIntrChangeMask(); 33411147Smitch.hayenga@arm.com 3352SN/A Tick intrDelay; 33611147Smitch.hayenga@arm.com Tick intrTick; 33711147Smitch.hayenga@arm.com bool cpuPendingIntr; 33811147Smitch.hayenga@arm.com void cpuIntrPost(Tick when); 33911147Smitch.hayenga@arm.com void cpuInterrupt(); 3402SN/A void cpuIntrClear(); 34111147Smitch.hayenga@arm.com 34211147Smitch.hayenga@arm.com typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent; 34311147Smitch.hayenga@arm.com friend void IntrEvent::process(); 34411147Smitch.hayenga@arm.com IntrEvent *intrEvent; 34511147Smitch.hayenga@arm.com NSGigEInt *interface; 34611147Smitch.hayenga@arm.com 34711147Smitch.hayenga@arm.com public: 34811147Smitch.hayenga@arm.com typedef NSGigEParams Params; 34911147Smitch.hayenga@arm.com const Params *params() const { 35011147Smitch.hayenga@arm.com return dynamic_cast<const Params *>(_params); 35111147Smitch.hayenga@arm.com } 35211147Smitch.hayenga@arm.com 35311147Smitch.hayenga@arm.com NSGigE(Params *params); 35411147Smitch.hayenga@arm.com ~NSGigE(); 35511147Smitch.hayenga@arm.com 35611147Smitch.hayenga@arm.com virtual EtherInt *getEthPort(const std::string &if_name, int idx); 35711147Smitch.hayenga@arm.com 35811147Smitch.hayenga@arm.com virtual Tick writeConfig(PacketPtr pkt); 35911147Smitch.hayenga@arm.com 36011147Smitch.hayenga@arm.com virtual Tick read(PacketPtr pkt); 36111147Smitch.hayenga@arm.com virtual Tick write(PacketPtr pkt); 36211147Smitch.hayenga@arm.com 36311147Smitch.hayenga@arm.com bool cpuIntrPending() const; 36411147Smitch.hayenga@arm.com void cpuIntrAck() { cpuIntrClear(); } 36511147Smitch.hayenga@arm.com 36611147Smitch.hayenga@arm.com bool recvPacket(EthPacketPtr packet); 36711147Smitch.hayenga@arm.com void transferDone(); 36811147Smitch.hayenga@arm.com 36911147Smitch.hayenga@arm.com virtual void serialize(std::ostream &os); 37011147Smitch.hayenga@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 37111147Smitch.hayenga@arm.com 37211147Smitch.hayenga@arm.com virtual void resume(); 37311147Smitch.hayenga@arm.com}; 37411147Smitch.hayenga@arm.com 37511147Smitch.hayenga@arm.com/* 37611147Smitch.hayenga@arm.com * Ethernet Interface for an Ethernet Device 37711147Smitch.hayenga@arm.com */ 37811147Smitch.hayenga@arm.comclass NSGigEInt : public EtherInt 37911147Smitch.hayenga@arm.com{ 38011147Smitch.hayenga@arm.com private: 38111147Smitch.hayenga@arm.com NSGigE *dev; 38210193SCurtis.Dunham@arm.com 3832SN/A public: 3842SN/A NSGigEInt(const std::string &name, NSGigE *d) 3852SN/A : EtherInt(name), dev(d) 3862623SN/A { } 387334SN/A 38811147Smitch.hayenga@arm.com virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); } 38911147Smitch.hayenga@arm.com virtual void sendDone() { dev->transferDone(); } 39011147Smitch.hayenga@arm.com}; 391334SN/A 392334SN/A#endif // __DEV_NS_GIGE_HH__ 393334SN/A