ns_gige.hh revision 879
14104Ssaidi@eecs.umich.edu/* 24104Ssaidi@eecs.umich.edu * Copyright (c) 2003 The Regents of The University of Michigan 34104Ssaidi@eecs.umich.edu * All rights reserved. 44104Ssaidi@eecs.umich.edu * 54104Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64104Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 74104Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84104Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94104Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104104Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114104Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124104Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134104Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144104Ssaidi@eecs.umich.edu * this software without specific prior written permission. 154104Ssaidi@eecs.umich.edu * 164104Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174104Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184104Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194104Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204104Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214104Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224104Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234104Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244104Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254104Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264104Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274104Ssaidi@eecs.umich.edu */ 284104Ssaidi@eecs.umich.edu 294104Ssaidi@eecs.umich.edu/* @file 304104Ssaidi@eecs.umich.edu * Device module for modelling the National Semiconductor 314104Ssaidi@eecs.umich.edu * DP83820 ethernet controller 324104Ssaidi@eecs.umich.edu */ 334104Ssaidi@eecs.umich.edu 344104Ssaidi@eecs.umich.edu#ifndef __NS_GIGE_HH__ 354104Ssaidi@eecs.umich.edu#define __NS_GIGE_HH__ 364104Ssaidi@eecs.umich.edu 374104Ssaidi@eecs.umich.edu//#include "base/range.hh" 384104Ssaidi@eecs.umich.edu#include "dev/etherint.hh" 394104Ssaidi@eecs.umich.edu#include "dev/etherpkt.hh" 408229Snate@binkert.org#include "sim/eventq.hh" 414104Ssaidi@eecs.umich.edu#include "dev/ns_gige_reg.h" 427723SAli.Saidi@ARM.com#include "base/statistics.hh" 434104Ssaidi@eecs.umich.edu#include "dev/pcidev.hh" 444104Ssaidi@eecs.umich.edu#include "dev/tsunami.hh" 458739Sgblack@eecs.umich.edu#include "dev/io_device.hh" 468232Snate@binkert.org#include "mem/bus/bus.hh" 474104Ssaidi@eecs.umich.edu 484104Ssaidi@eecs.umich.edu/** defined by the NS83820 data sheet */ 498229Snate@binkert.org#define MAX_TX_FIFO_SIZE 8192 504104Ssaidi@eecs.umich.edu#define MAX_RX_FIFO_SIZE 32768 514194Ssaidi@eecs.umich.edu 524104Ssaidi@eecs.umich.edu/** length of ethernet address in bytes */ 534104Ssaidi@eecs.umich.edu#define EADDR_LEN 6 544762Snate@binkert.org 554104Ssaidi@eecs.umich.edu/** 564104Ssaidi@eecs.umich.edu * Ethernet device registers 574104Ssaidi@eecs.umich.edu */ 584104Ssaidi@eecs.umich.edustruct dp_regs { 594104Ssaidi@eecs.umich.edu uint32_t command; 604104Ssaidi@eecs.umich.edu uint32_t config; 614104Ssaidi@eecs.umich.edu uint32_t mear; 625103Ssaidi@eecs.umich.edu uint32_t ptscr; 635103Ssaidi@eecs.umich.edu uint32_t isr; 645103Ssaidi@eecs.umich.edu uint32_t imr; 654104Ssaidi@eecs.umich.edu uint32_t ier; 664104Ssaidi@eecs.umich.edu uint32_t ihr; 674104Ssaidi@eecs.umich.edu uint32_t txdp; 684104Ssaidi@eecs.umich.edu uint32_t txdp_hi; 694104Ssaidi@eecs.umich.edu uint32_t txcfg; 704104Ssaidi@eecs.umich.edu uint32_t gpior; 714104Ssaidi@eecs.umich.edu uint32_t rxdp; 724104Ssaidi@eecs.umich.edu uint32_t rxdp_hi; 734104Ssaidi@eecs.umich.edu uint32_t rxcfg; 744104Ssaidi@eecs.umich.edu uint32_t pqcr; 754104Ssaidi@eecs.umich.edu uint32_t wcsr; 764104Ssaidi@eecs.umich.edu uint32_t pcr; 774104Ssaidi@eecs.umich.edu uint32_t rfcr; 784104Ssaidi@eecs.umich.edu uint32_t rfdr; 794104Ssaidi@eecs.umich.edu uint32_t srr; 804104Ssaidi@eecs.umich.edu uint32_t mibc; 814104Ssaidi@eecs.umich.edu uint32_t vrcr; 824104Ssaidi@eecs.umich.edu uint32_t vtcr; 834104Ssaidi@eecs.umich.edu uint32_t vdr; 844104Ssaidi@eecs.umich.edu uint32_t ccsr; 854870Sstever@eecs.umich.edu uint32_t tbicr; 864104Ssaidi@eecs.umich.edu uint32_t tbisr; 874104Ssaidi@eecs.umich.edu uint32_t tanar; 884104Ssaidi@eecs.umich.edu uint32_t tanlpar; 894104Ssaidi@eecs.umich.edu uint32_t taner; 904104Ssaidi@eecs.umich.edu uint32_t tesr; 914104Ssaidi@eecs.umich.edu}; 924104Ssaidi@eecs.umich.edu 934104Ssaidi@eecs.umich.edustruct dp_rom { 9411294Sandreas.hansson@arm.com /** for perfect match memory. the linux driver doesn't use any other ROM */ 9511294Sandreas.hansson@arm.com uint8_t perfectMatch[EADDR_LEN]; 966712Snate@binkert.org}; 976712Snate@binkert.org 984104Ssaidi@eecs.umich.educlass IntrControl; 994104Ssaidi@eecs.umich.educlass NSGigEInt; 1004104Ssaidi@eecs.umich.educlass PhysicalMemory; 1014104Ssaidi@eecs.umich.educlass BaseInterface; 1024104Ssaidi@eecs.umich.educlass HierParams; 1036712Snate@binkert.orgclass Bus; 1046712Snate@binkert.orgclass PciConfigAll; 1056712Snate@binkert.org 1064104Ssaidi@eecs.umich.edu/** 1074104Ssaidi@eecs.umich.edu * NS DP82830 Ethernet device model 1084104Ssaidi@eecs.umich.edu */ 1094104Ssaidi@eecs.umich.educlass NSGigE : public PciDev 1104104Ssaidi@eecs.umich.edu{ 1114104Ssaidi@eecs.umich.edu public: 1124104Ssaidi@eecs.umich.edu /** Transmit State Machine states */ 1134104Ssaidi@eecs.umich.edu enum TxState 1144104Ssaidi@eecs.umich.edu { 1154104Ssaidi@eecs.umich.edu txIdle, 1164104Ssaidi@eecs.umich.edu txDescRefr, 1174104Ssaidi@eecs.umich.edu txDescRead, 1184104Ssaidi@eecs.umich.edu txFifoBlock, 1194104Ssaidi@eecs.umich.edu txFragRead, 1204104Ssaidi@eecs.umich.edu txDescWrite, 1214104Ssaidi@eecs.umich.edu txAdvance 12211005Sandreas.sandberg@arm.com }; 1234104Ssaidi@eecs.umich.edu 1244104Ssaidi@eecs.umich.edu /** Receive State Machine States */ 1254104Ssaidi@eecs.umich.edu enum RxState 1264104Ssaidi@eecs.umich.edu { 1274104Ssaidi@eecs.umich.edu rxIdle, 1284104Ssaidi@eecs.umich.edu rxDescRefr, 1294104Ssaidi@eecs.umich.edu rxDescRead, 1304104Ssaidi@eecs.umich.edu rxFifoBlock, 1314104Ssaidi@eecs.umich.edu rxFragWrite, 1324104Ssaidi@eecs.umich.edu rxDescWrite, 1334104Ssaidi@eecs.umich.edu rxAdvance 1344104Ssaidi@eecs.umich.edu }; 1354104Ssaidi@eecs.umich.edu 1364104Ssaidi@eecs.umich.edu enum DmaState 1374104Ssaidi@eecs.umich.edu { 1384104Ssaidi@eecs.umich.edu dmaIdle, 1394104Ssaidi@eecs.umich.edu dmaReading, 1404104Ssaidi@eecs.umich.edu dmaWriting, 1414104Ssaidi@eecs.umich.edu dmaReadWaiting, 1424104Ssaidi@eecs.umich.edu dmaWriteWaiting 1434104Ssaidi@eecs.umich.edu }; 1444104Ssaidi@eecs.umich.edu 1454104Ssaidi@eecs.umich.edu private: 1464104Ssaidi@eecs.umich.edu /** pointer to the chipset */ 1474104Ssaidi@eecs.umich.edu Tsunami *tsunami; 1484104Ssaidi@eecs.umich.edu 1494104Ssaidi@eecs.umich.edu private: 1504104Ssaidi@eecs.umich.edu Addr addr; 1514104Ssaidi@eecs.umich.edu static const Addr size = sizeof(dp_regs); 1524104Ssaidi@eecs.umich.edu 1534104Ssaidi@eecs.umich.edu protected: 1544104Ssaidi@eecs.umich.edu typedef std::deque<PacketPtr> pktbuf_t; 1554104Ssaidi@eecs.umich.edu typedef pktbuf_t::iterator pktiter_t; 1564104Ssaidi@eecs.umich.edu 1574104Ssaidi@eecs.umich.edu /** device register file */ 1584104Ssaidi@eecs.umich.edu dp_regs regs; 1594104Ssaidi@eecs.umich.edu dp_rom rom; 1604104Ssaidi@eecs.umich.edu 1614104Ssaidi@eecs.umich.edu /*** BASIC STRUCTURES FOR TX/RX ***/ 1624104Ssaidi@eecs.umich.edu /* Data FIFOs */ 1634104Ssaidi@eecs.umich.edu pktbuf_t txFifo; 1644104Ssaidi@eecs.umich.edu pktbuf_t rxFifo; 1654104Ssaidi@eecs.umich.edu 1664104Ssaidi@eecs.umich.edu /** various helper vars */ 1674104Ssaidi@eecs.umich.edu uint8_t *txPacketBufPtr; 1684104Ssaidi@eecs.umich.edu uint8_t *rxPacketBufPtr; 1694104Ssaidi@eecs.umich.edu uint32_t txXferLen; 1704104Ssaidi@eecs.umich.edu uint32_t rxXferLen; 1714104Ssaidi@eecs.umich.edu uint32_t txPktXmitted; 1724104Ssaidi@eecs.umich.edu bool rxDmaFree; 1734104Ssaidi@eecs.umich.edu bool txDmaFree; 1744104Ssaidi@eecs.umich.edu PacketPtr txPacket; 1754104Ssaidi@eecs.umich.edu PacketPtr rxPacket; 1764104Ssaidi@eecs.umich.edu 1774104Ssaidi@eecs.umich.edu /** DescCaches */ 1784104Ssaidi@eecs.umich.edu ns_desc txDescCache; 1794870Sstever@eecs.umich.edu ns_desc rxDescCache; 1804104Ssaidi@eecs.umich.edu 1814104Ssaidi@eecs.umich.edu /* tx State Machine */ 1824104Ssaidi@eecs.umich.edu TxState txState; 1834104Ssaidi@eecs.umich.edu /** Current Transmit Descriptor Done */ 1844104Ssaidi@eecs.umich.edu bool CTDD; 1854104Ssaidi@eecs.umich.edu /** amt of data in the txDataFifo in bytes (logical) */ 1864104Ssaidi@eecs.umich.edu uint32_t txFifoCnt; 1874104Ssaidi@eecs.umich.edu /** current amt of free space in txDataFifo in bytes */ 1884104Ssaidi@eecs.umich.edu uint32_t txFifoAvail; 1894104Ssaidi@eecs.umich.edu /** halt the tx state machine after next packet */ 19011294Sandreas.hansson@arm.com bool txHalt; 19111294Sandreas.hansson@arm.com /** ptr to the next byte in the current fragment */ 1924104Ssaidi@eecs.umich.edu Addr txFragPtr; 1934104Ssaidi@eecs.umich.edu /** count of bytes remaining in the current descriptor */ 1944104Ssaidi@eecs.umich.edu uint32_t txDescCnt; 1954104Ssaidi@eecs.umich.edu DmaState txDmaState; 1964216Ssaidi@eecs.umich.edu 1974216Ssaidi@eecs.umich.edu /** rx State Machine */ 1984104Ssaidi@eecs.umich.edu RxState rxState; 1994104Ssaidi@eecs.umich.edu /** Current Receive Descriptor Done */ 2004104Ssaidi@eecs.umich.edu bool CRDD; 2014104Ssaidi@eecs.umich.edu /** num of bytes in the current packet being drained from rxDataFifo */ 2026712Snate@binkert.org uint32_t rxPktBytes; 2034104Ssaidi@eecs.umich.edu /** number of bytes in the rxFifo */ 2044104Ssaidi@eecs.umich.edu uint32_t rxFifoCnt; 2054104Ssaidi@eecs.umich.edu /** halt the rx state machine after current packet */ 2064104Ssaidi@eecs.umich.edu bool rxHalt; 2074216Ssaidi@eecs.umich.edu /** ptr to the next byte in current fragment */ 2084216Ssaidi@eecs.umich.edu Addr rxFragPtr; 2094104Ssaidi@eecs.umich.edu /** count of bytes remaining in the current descriptor */ 2104104Ssaidi@eecs.umich.edu uint32_t rxDescCnt; 2114104Ssaidi@eecs.umich.edu DmaState rxDmaState; 2124104Ssaidi@eecs.umich.edu 2134104Ssaidi@eecs.umich.edu bool extstsEnable; 2144216Ssaidi@eecs.umich.edu 2154104Ssaidi@eecs.umich.edu protected: 2164104Ssaidi@eecs.umich.edu Tick dmaReadDelay; 2174104Ssaidi@eecs.umich.edu Tick dmaWriteDelay; 2184104Ssaidi@eecs.umich.edu 2194104Ssaidi@eecs.umich.edu Tick dmaReadFactor; 2204104Ssaidi@eecs.umich.edu Tick dmaWriteFactor; 2214104Ssaidi@eecs.umich.edu 2224104Ssaidi@eecs.umich.edu void *rxDmaData; 2234104Ssaidi@eecs.umich.edu Addr rxDmaAddr; 2244104Ssaidi@eecs.umich.edu int rxDmaLen; 2254104Ssaidi@eecs.umich.edu bool doRxDmaRead(); 2264104Ssaidi@eecs.umich.edu bool doRxDmaWrite(); 2274104Ssaidi@eecs.umich.edu void rxDmaReadCopy(); 2284104Ssaidi@eecs.umich.edu void rxDmaWriteCopy(); 2294104Ssaidi@eecs.umich.edu 2304104Ssaidi@eecs.umich.edu void *txDmaData; 2314104Ssaidi@eecs.umich.edu Addr txDmaAddr; 2324104Ssaidi@eecs.umich.edu int txDmaLen; 2334104Ssaidi@eecs.umich.edu bool doTxDmaRead(); 2344104Ssaidi@eecs.umich.edu bool doTxDmaWrite(); 2354104Ssaidi@eecs.umich.edu void txDmaReadCopy(); 2364104Ssaidi@eecs.umich.edu void txDmaWriteCopy(); 2374104Ssaidi@eecs.umich.edu 23811005Sandreas.sandberg@arm.com void rxDmaReadDone(); 2394104Ssaidi@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>; 2404104Ssaidi@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent; 2414104Ssaidi@eecs.umich.edu 2424104Ssaidi@eecs.umich.edu void rxDmaWriteDone(); 2434104Ssaidi@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>; 2444104Ssaidi@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent; 2454104Ssaidi@eecs.umich.edu 2464216Ssaidi@eecs.umich.edu void txDmaReadDone(); 2474216Ssaidi@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>; 2484104Ssaidi@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent; 2494104Ssaidi@eecs.umich.edu 2504104Ssaidi@eecs.umich.edu void txDmaWriteDone(); 2514104Ssaidi@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>; 2524104Ssaidi@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent; 2534216Ssaidi@eecs.umich.edu 2544216Ssaidi@eecs.umich.edu bool dmaDescFree; 2554104Ssaidi@eecs.umich.edu bool dmaDataFree; 2564104Ssaidi@eecs.umich.edu 2574104Ssaidi@eecs.umich.edu 2584104Ssaidi@eecs.umich.edu protected: 2594104Ssaidi@eecs.umich.edu Tick txDelay; 2604104Ssaidi@eecs.umich.edu Tick rxDelay; 2614104Ssaidi@eecs.umich.edu 2624104Ssaidi@eecs.umich.edu void txReset(); 2634104Ssaidi@eecs.umich.edu void rxReset(); 2644104Ssaidi@eecs.umich.edu void regsReset() { 2654104Ssaidi@eecs.umich.edu memset(®s, 0, sizeof(regs)); 2664104Ssaidi@eecs.umich.edu regs.config = 0x80000000; 2674104Ssaidi@eecs.umich.edu regs.mear = 0x12; 2684104Ssaidi@eecs.umich.edu regs.isr = 0x00608000; 2694216Ssaidi@eecs.umich.edu regs.txcfg = 0x120; 2704216Ssaidi@eecs.umich.edu regs.rxcfg = 0x4; 2714104Ssaidi@eecs.umich.edu regs.srr = 0x0103; 2724104Ssaidi@eecs.umich.edu regs.mibc = 0x2; 2734104Ssaidi@eecs.umich.edu regs.vdr = 0x81; 2744104Ssaidi@eecs.umich.edu regs.tesr = 0xc000; 2754104Ssaidi@eecs.umich.edu } 2764104Ssaidi@eecs.umich.edu 2774104Ssaidi@eecs.umich.edu void rxKick(); 2784194Ssaidi@eecs.umich.edu Tick rxKickTick; 2795719Shsul@eecs.umich.edu typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent; 2804104Ssaidi@eecs.umich.edu friend class RxKickEvent; 2814130Ssaidi@eecs.umich.edu 2824194Ssaidi@eecs.umich.edu void txKick(); 2834194Ssaidi@eecs.umich.edu Tick txKickTick; 2844216Ssaidi@eecs.umich.edu typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent; 2854216Ssaidi@eecs.umich.edu friend class TxKickEvent; 2864194Ssaidi@eecs.umich.edu 2874194Ssaidi@eecs.umich.edu /** 2884194Ssaidi@eecs.umich.edu * Retransmit event 2894194Ssaidi@eecs.umich.edu */ 2904194Ssaidi@eecs.umich.edu void transmit(); 2914194Ssaidi@eecs.umich.edu typedef EventWrapper<NSGigE, &NSGigE::transmit> TxEvent; 2924194Ssaidi@eecs.umich.edu friend class TxEvent; 2934194Ssaidi@eecs.umich.edu TxEvent txEvent; 2944194Ssaidi@eecs.umich.edu 2954194Ssaidi@eecs.umich.edu void txDump() const; 2964216Ssaidi@eecs.umich.edu void rxDump() const; 2974194Ssaidi@eecs.umich.edu 2984194Ssaidi@eecs.umich.edu /** 2994194Ssaidi@eecs.umich.edu * receive address filter 3004216Ssaidi@eecs.umich.edu */ 3014194Ssaidi@eecs.umich.edu bool rxFilterEnable; 3024194Ssaidi@eecs.umich.edu bool rxFilter(PacketPtr packet); 3034194Ssaidi@eecs.umich.edu bool acceptBroadcast; 3044194Ssaidi@eecs.umich.edu bool acceptMulticast; 3054194Ssaidi@eecs.umich.edu bool acceptUnicast; 3064104Ssaidi@eecs.umich.edu bool acceptPerfect; 3074104Ssaidi@eecs.umich.edu bool acceptArp; 3084104Ssaidi@eecs.umich.edu 3094104Ssaidi@eecs.umich.edu PhysicalMemory *physmem; 3104104Ssaidi@eecs.umich.edu 3114104Ssaidi@eecs.umich.edu /** 3124104Ssaidi@eecs.umich.edu * Interrupt management 3134104Ssaidi@eecs.umich.edu */ 3144104Ssaidi@eecs.umich.edu IntrControl *intctrl; 3154104Ssaidi@eecs.umich.edu void devIntrPost(uint32_t interrupts); 3164216Ssaidi@eecs.umich.edu void devIntrClear(uint32_t interrupts); 3174216Ssaidi@eecs.umich.edu void devIntrChangeMask(); 3184216Ssaidi@eecs.umich.edu 3194104Ssaidi@eecs.umich.edu Tick intrDelay; 3204104Ssaidi@eecs.umich.edu Tick intrTick; 3214104Ssaidi@eecs.umich.edu bool cpuPendingIntr; 3224104Ssaidi@eecs.umich.edu void cpuIntrPost(Tick when); 3234104Ssaidi@eecs.umich.edu void cpuInterrupt(); 3244104Ssaidi@eecs.umich.edu void cpuIntrClear(); 3254104Ssaidi@eecs.umich.edu 3264104Ssaidi@eecs.umich.edu typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent; 3274104Ssaidi@eecs.umich.edu friend class IntrEvent; 3288711Sandreas.hansson@arm.com IntrEvent *intrEvent; 3299090Sandreas.hansson@arm.com 3304104Ssaidi@eecs.umich.edu /** 3318711Sandreas.hansson@arm.com * Hardware checksum support 3328711Sandreas.hansson@arm.com */ 3338711Sandreas.hansson@arm.com bool udpChecksum(PacketPtr packet, bool gen); 3348711Sandreas.hansson@arm.com bool tcpChecksum(PacketPtr packet, bool gen); 3354104Ssaidi@eecs.umich.edu bool ipChecksum(PacketPtr packet, bool gen); 3364104Ssaidi@eecs.umich.edu uint16_t checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len); 3374104Ssaidi@eecs.umich.edu 3384104Ssaidi@eecs.umich.edu NSGigEInt *interface; 33910905Sandreas.sandberg@arm.com 3404104Ssaidi@eecs.umich.edu public: 3414104Ssaidi@eecs.umich.edu NSGigE(const std::string &name, IntrControl *i, Tick intr_delay, 3424104Ssaidi@eecs.umich.edu PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay, 3434104Ssaidi@eecs.umich.edu MemoryController *mmu, HierParams *hier, Bus *header_bus, 3444104Ssaidi@eecs.umich.edu Bus *payload_bus, Tick pio_latency, bool dma_desc_free, 3454104Ssaidi@eecs.umich.edu bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay, 34610905Sandreas.sandberg@arm.com Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf, 34710905Sandreas.sandberg@arm.com PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev, 34810905Sandreas.sandberg@arm.com uint32_t func, bool rx_filter, const int eaddr[6], Addr addr); 34910905Sandreas.sandberg@arm.com ~NSGigE(); 35010905Sandreas.sandberg@arm.com 3514104Ssaidi@eecs.umich.edu virtual void WriteConfig(int offset, int size, uint32_t data); 3524104Ssaidi@eecs.umich.edu virtual void ReadConfig(int offset, int size, uint8_t *data); 35310905Sandreas.sandberg@arm.com 35410905Sandreas.sandberg@arm.com virtual Fault read(MemReqPtr &req, uint8_t *data); 35510905Sandreas.sandberg@arm.com virtual Fault write(MemReqPtr &req, const uint8_t *data); 3564104Ssaidi@eecs.umich.edu 3574104Ssaidi@eecs.umich.edu bool cpuIntrPending() const; 3584104Ssaidi@eecs.umich.edu void cpuIntrAck() { cpuIntrClear(); } 3594104Ssaidi@eecs.umich.edu 36010905Sandreas.sandberg@arm.com bool recvPacket(PacketPtr packet); 3614104Ssaidi@eecs.umich.edu void transferDone(); 3624104Ssaidi@eecs.umich.edu 3634104Ssaidi@eecs.umich.edu void setInterface(NSGigEInt *i) { assert(!interface); interface = i; } 3644104Ssaidi@eecs.umich.edu 3654104Ssaidi@eecs.umich.edu virtual void serialize(std::ostream &os); 36610905Sandreas.sandberg@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 36710905Sandreas.sandberg@arm.com 36810905Sandreas.sandberg@arm.com public: 36910905Sandreas.sandberg@arm.com void regStats(); 37010905Sandreas.sandberg@arm.com 3714104Ssaidi@eecs.umich.edu private: 3724104Ssaidi@eecs.umich.edu Stats::Scalar<> txBytes; 37310905Sandreas.sandberg@arm.com Stats::Scalar<> rxBytes; 37410905Sandreas.sandberg@arm.com Stats::Scalar<> txPackets; 37510905Sandreas.sandberg@arm.com Stats::Scalar<> rxPackets; 3764104Ssaidi@eecs.umich.edu Stats::Formula txBandwidth; 3774104Ssaidi@eecs.umich.edu Stats::Formula rxBandwidth; 3784104Ssaidi@eecs.umich.edu Stats::Formula txPacketRate; 3794762Snate@binkert.org Stats::Formula rxPacketRate; 3804762Snate@binkert.org 3814104Ssaidi@eecs.umich.edu private: 3824762Snate@binkert.org Tick pioLatency; 3834104Ssaidi@eecs.umich.edu 384 public: 385 Tick cacheAccess(MemReqPtr &req); 386}; 387 388/* 389 * Ethernet Interface for an Ethernet Device 390 */ 391class NSGigEInt : public EtherInt 392{ 393 private: 394 NSGigE *dev; 395 396 public: 397 NSGigEInt(const std::string &name, NSGigE *d) 398 : EtherInt(name), dev(d) { dev->setInterface(this); } 399 400 virtual bool recvPacket(PacketPtr &pkt) { return dev->recvPacket(pkt); } 401 virtual void sendDone() { dev->transferDone(); } 402}; 403 404#endif // __NS_GIGE_HH__ 405