ns_gige.hh revision 4762
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 293569Sgblack@eecs.umich.edu * Lisa Hsu 303569Sgblack@eecs.umich.edu */ 313804Ssaidi@eecs.umich.edu 323811Ssaidi@eecs.umich.edu/** @file 333569Sgblack@eecs.umich.edu * Device module for modelling the National Semiconductor 343824Ssaidi@eecs.umich.edu * DP83820 ethernet controller 353811Ssaidi@eecs.umich.edu */ 363811Ssaidi@eecs.umich.edu 373823Ssaidi@eecs.umich.edu#ifndef __DEV_NS_GIGE_HH__ 383823Ssaidi@eecs.umich.edu#define __DEV_NS_GIGE_HH__ 393823Ssaidi@eecs.umich.edu 403569Sgblack@eecs.umich.edu#include "base/inet.hh" 413569Sgblack@eecs.umich.edu#include "base/statistics.hh" 423804Ssaidi@eecs.umich.edu#include "dev/etherint.hh" 433804Ssaidi@eecs.umich.edu#include "dev/etherpkt.hh" 443569Sgblack@eecs.umich.edu#include "dev/io_device.hh" 453569Sgblack@eecs.umich.edu#include "dev/ns_gige_reg.h" 463569Sgblack@eecs.umich.edu#include "dev/pcidev.hh" 473804Ssaidi@eecs.umich.edu#include "dev/pktfifo.hh" 483804Ssaidi@eecs.umich.edu#include "params/NSGigE.hh" 493804Ssaidi@eecs.umich.edu#include "sim/eventq.hh" 503804Ssaidi@eecs.umich.edu 513804Ssaidi@eecs.umich.edu// Hash filtering constants 523804Ssaidi@eecs.umich.educonst uint16_t FHASH_ADDR = 0x100; 533569Sgblack@eecs.umich.educonst uint16_t FHASH_SIZE = 0x100; 543804Ssaidi@eecs.umich.edu 553804Ssaidi@eecs.umich.edu// EEPROM constants 563804Ssaidi@eecs.umich.educonst uint8_t EEPROM_READ = 0x2; 573569Sgblack@eecs.umich.educonst uint8_t EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM 583804Ssaidi@eecs.umich.educonst uint8_t EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2 593804Ssaidi@eecs.umich.educonst uint8_t EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1 603804Ssaidi@eecs.umich.educonst uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0 613804Ssaidi@eecs.umich.edu 623804Ssaidi@eecs.umich.edu/** 633804Ssaidi@eecs.umich.edu * Ethernet device registers 643804Ssaidi@eecs.umich.edu */ 653804Ssaidi@eecs.umich.edustruct dp_regs { 663804Ssaidi@eecs.umich.edu uint32_t command; 673804Ssaidi@eecs.umich.edu uint32_t config; 683804Ssaidi@eecs.umich.edu uint32_t mear; 693804Ssaidi@eecs.umich.edu uint32_t ptscr; 703569Sgblack@eecs.umich.edu uint32_t isr; 713569Sgblack@eecs.umich.edu uint32_t imr; 723804Ssaidi@eecs.umich.edu uint32_t ier; 733804Ssaidi@eecs.umich.edu uint32_t ihr; 743826Ssaidi@eecs.umich.edu uint32_t txdp; 753804Ssaidi@eecs.umich.edu uint32_t txdp_hi; 763569Sgblack@eecs.umich.edu uint32_t txcfg; 773569Sgblack@eecs.umich.edu uint32_t gpior; 783804Ssaidi@eecs.umich.edu uint32_t rxdp; 793826Ssaidi@eecs.umich.edu uint32_t rxdp_hi; 803826Ssaidi@eecs.umich.edu uint32_t rxcfg; 813811Ssaidi@eecs.umich.edu uint32_t pqcr; 823826Ssaidi@eecs.umich.edu uint32_t wcsr; 833826Ssaidi@eecs.umich.edu uint32_t pcr; 843811Ssaidi@eecs.umich.edu uint32_t rfcr; 853826Ssaidi@eecs.umich.edu uint32_t rfdr; 863826Ssaidi@eecs.umich.edu uint32_t brar; 873826Ssaidi@eecs.umich.edu uint32_t brdr; 883826Ssaidi@eecs.umich.edu uint32_t srr; 893826Ssaidi@eecs.umich.edu uint32_t mibc; 903826Ssaidi@eecs.umich.edu uint32_t vrcr; 913826Ssaidi@eecs.umich.edu uint32_t vtcr; 923826Ssaidi@eecs.umich.edu uint32_t vdr; 933826Ssaidi@eecs.umich.edu uint32_t ccsr; 943804Ssaidi@eecs.umich.edu uint32_t tbicr; 953569Sgblack@eecs.umich.edu uint32_t tbisr; 963569Sgblack@eecs.umich.edu uint32_t tanar; 973804Ssaidi@eecs.umich.edu uint32_t tanlpar; 983826Ssaidi@eecs.umich.edu uint32_t taner; 993826Ssaidi@eecs.umich.edu uint32_t tesr; 1003569Sgblack@eecs.umich.edu}; 1013804Ssaidi@eecs.umich.edu 1023804Ssaidi@eecs.umich.edustruct dp_rom { 1033804Ssaidi@eecs.umich.edu /** 1043804Ssaidi@eecs.umich.edu * for perfect match memory. 1053804Ssaidi@eecs.umich.edu * the linux driver doesn't use any other ROM 1063804Ssaidi@eecs.umich.edu */ 1073804Ssaidi@eecs.umich.edu uint8_t perfectMatch[ETH_ADDR_LEN]; 1083804Ssaidi@eecs.umich.edu 1093804Ssaidi@eecs.umich.edu /** 1103804Ssaidi@eecs.umich.edu * for hash table memory. 1113569Sgblack@eecs.umich.edu * used by the freebsd driver 1123569Sgblack@eecs.umich.edu */ 1133804Ssaidi@eecs.umich.edu uint8_t filterHash[FHASH_SIZE]; 1143804Ssaidi@eecs.umich.edu}; 1153804Ssaidi@eecs.umich.edu 1163804Ssaidi@eecs.umich.educlass NSGigEInt; 1173804Ssaidi@eecs.umich.educlass Packet; 1183804Ssaidi@eecs.umich.edu 1193804Ssaidi@eecs.umich.edu/** 1203804Ssaidi@eecs.umich.edu * NS DP83820 Ethernet device model 1213811Ssaidi@eecs.umich.edu */ 1223804Ssaidi@eecs.umich.educlass NSGigE : public PciDev 1233569Sgblack@eecs.umich.edu{ 1243569Sgblack@eecs.umich.edu public: 1253804Ssaidi@eecs.umich.edu /** Transmit State Machine states */ 1263804Ssaidi@eecs.umich.edu enum TxState 1273804Ssaidi@eecs.umich.edu { 1283804Ssaidi@eecs.umich.edu txIdle, 1293804Ssaidi@eecs.umich.edu txDescRefr, 1303804Ssaidi@eecs.umich.edu txDescRead, 1313804Ssaidi@eecs.umich.edu txFifoBlock, 1323804Ssaidi@eecs.umich.edu txFragRead, 1333804Ssaidi@eecs.umich.edu txDescWrite, 1343804Ssaidi@eecs.umich.edu txAdvance 1353569Sgblack@eecs.umich.edu }; 1363804Ssaidi@eecs.umich.edu 1373804Ssaidi@eecs.umich.edu /** Receive State Machine States */ 1383804Ssaidi@eecs.umich.edu enum RxState 1393804Ssaidi@eecs.umich.edu { 1403804Ssaidi@eecs.umich.edu rxIdle, 1413804Ssaidi@eecs.umich.edu rxDescRefr, 1423804Ssaidi@eecs.umich.edu rxDescRead, 1433804Ssaidi@eecs.umich.edu rxFifoBlock, 1443804Ssaidi@eecs.umich.edu rxFragWrite, 1453811Ssaidi@eecs.umich.edu rxDescWrite, 1463811Ssaidi@eecs.umich.edu rxAdvance 1473804Ssaidi@eecs.umich.edu }; 1483804Ssaidi@eecs.umich.edu 1493804Ssaidi@eecs.umich.edu enum DmaState 1503804Ssaidi@eecs.umich.edu { 1513804Ssaidi@eecs.umich.edu dmaIdle, 1523804Ssaidi@eecs.umich.edu dmaReading, 1533804Ssaidi@eecs.umich.edu dmaWriting, 1543804Ssaidi@eecs.umich.edu dmaReadWaiting, 1553804Ssaidi@eecs.umich.edu dmaWriteWaiting 1563804Ssaidi@eecs.umich.edu }; 1573811Ssaidi@eecs.umich.edu 1583804Ssaidi@eecs.umich.edu /** EEPROM State Machine States */ 1593804Ssaidi@eecs.umich.edu enum EEPROMState 1603804Ssaidi@eecs.umich.edu { 1613804Ssaidi@eecs.umich.edu eepromStart, 1623804Ssaidi@eecs.umich.edu eepromGetOpcode, 1633826Ssaidi@eecs.umich.edu eepromGetAddress, 1643826Ssaidi@eecs.umich.edu eepromRead 1653804Ssaidi@eecs.umich.edu }; 1663804Ssaidi@eecs.umich.edu 1673804Ssaidi@eecs.umich.edu protected: 1683804Ssaidi@eecs.umich.edu /** device register file */ 1693804Ssaidi@eecs.umich.edu dp_regs regs; 1703804Ssaidi@eecs.umich.edu dp_rom rom; 1713804Ssaidi@eecs.umich.edu 1723804Ssaidi@eecs.umich.edu /** pci settings */ 1733804Ssaidi@eecs.umich.edu bool ioEnable; 1743804Ssaidi@eecs.umich.edu#if 0 1753804Ssaidi@eecs.umich.edu bool memEnable; 1763804Ssaidi@eecs.umich.edu bool bmEnable; 1773804Ssaidi@eecs.umich.edu#endif 1783826Ssaidi@eecs.umich.edu 1793826Ssaidi@eecs.umich.edu /*** BASIC STRUCTURES FOR TX/RX ***/ 1803826Ssaidi@eecs.umich.edu /* Data FIFOs */ 1813826Ssaidi@eecs.umich.edu PacketFifo txFifo; 1823826Ssaidi@eecs.umich.edu PacketFifo rxFifo; 1833826Ssaidi@eecs.umich.edu 1843826Ssaidi@eecs.umich.edu /** various helper vars */ 1853826Ssaidi@eecs.umich.edu EthPacketPtr txPacket; 1863826Ssaidi@eecs.umich.edu EthPacketPtr rxPacket; 1873826Ssaidi@eecs.umich.edu uint8_t *txPacketBufPtr; 1883826Ssaidi@eecs.umich.edu uint8_t *rxPacketBufPtr; 1893826Ssaidi@eecs.umich.edu uint32_t txXferLen; 1903804Ssaidi@eecs.umich.edu uint32_t rxXferLen; 1913804Ssaidi@eecs.umich.edu bool rxDmaFree; 1923804Ssaidi@eecs.umich.edu bool txDmaFree; 1933804Ssaidi@eecs.umich.edu 1943804Ssaidi@eecs.umich.edu /** DescCaches */ 1953804Ssaidi@eecs.umich.edu ns_desc32 txDesc32; 1963804Ssaidi@eecs.umich.edu ns_desc32 rxDesc32; 1973804Ssaidi@eecs.umich.edu ns_desc64 txDesc64; 1983804Ssaidi@eecs.umich.edu ns_desc64 rxDesc64; 1993804Ssaidi@eecs.umich.edu 2003804Ssaidi@eecs.umich.edu /* state machine cycle time */ 2013804Ssaidi@eecs.umich.edu Tick clock; 2023804Ssaidi@eecs.umich.edu inline Tick cycles(int numCycles) const { return numCycles * clock; } 2033804Ssaidi@eecs.umich.edu 2043804Ssaidi@eecs.umich.edu /* tx State Machine */ 2053804Ssaidi@eecs.umich.edu TxState txState; 2063804Ssaidi@eecs.umich.edu bool txEnable; 2073804Ssaidi@eecs.umich.edu 2083804Ssaidi@eecs.umich.edu /** Current Transmit Descriptor Done */ 2093804Ssaidi@eecs.umich.edu bool CTDD; 2103804Ssaidi@eecs.umich.edu /** halt the tx state machine after next packet */ 2113804Ssaidi@eecs.umich.edu bool txHalt; 2123804Ssaidi@eecs.umich.edu /** ptr to the next byte in the current fragment */ 2133804Ssaidi@eecs.umich.edu Addr txFragPtr; 2143804Ssaidi@eecs.umich.edu /** count of bytes remaining in the current descriptor */ 2153804Ssaidi@eecs.umich.edu uint32_t txDescCnt; 2163804Ssaidi@eecs.umich.edu DmaState txDmaState; 2173804Ssaidi@eecs.umich.edu 2183804Ssaidi@eecs.umich.edu /** rx State Machine */ 2193804Ssaidi@eecs.umich.edu RxState rxState; 2203804Ssaidi@eecs.umich.edu bool rxEnable; 2213804Ssaidi@eecs.umich.edu 2223804Ssaidi@eecs.umich.edu /** Current Receive Descriptor Done */ 2233804Ssaidi@eecs.umich.edu bool CRDD; 2243804Ssaidi@eecs.umich.edu /** num of bytes in the current packet being drained from rxDataFifo */ 2253804Ssaidi@eecs.umich.edu uint32_t rxPktBytes; 2263804Ssaidi@eecs.umich.edu /** halt the rx state machine after current packet */ 2273804Ssaidi@eecs.umich.edu bool rxHalt; 2283804Ssaidi@eecs.umich.edu /** ptr to the next byte in current fragment */ 2293804Ssaidi@eecs.umich.edu Addr rxFragPtr; 2303804Ssaidi@eecs.umich.edu /** count of bytes remaining in the current descriptor */ 2313804Ssaidi@eecs.umich.edu uint32_t rxDescCnt; 2323804Ssaidi@eecs.umich.edu DmaState rxDmaState; 2333804Ssaidi@eecs.umich.edu 2343804Ssaidi@eecs.umich.edu bool extstsEnable; 2353804Ssaidi@eecs.umich.edu 2363804Ssaidi@eecs.umich.edu /** EEPROM State Machine */ 2373804Ssaidi@eecs.umich.edu EEPROMState eepromState; 2383804Ssaidi@eecs.umich.edu bool eepromClk; 2393804Ssaidi@eecs.umich.edu uint8_t eepromBitsToRx; 2403804Ssaidi@eecs.umich.edu uint8_t eepromOpcode; 2413804Ssaidi@eecs.umich.edu uint8_t eepromAddress; 2423804Ssaidi@eecs.umich.edu uint16_t eepromData; 2433804Ssaidi@eecs.umich.edu 2443804Ssaidi@eecs.umich.edu protected: 2453804Ssaidi@eecs.umich.edu Tick dmaReadDelay; 2463804Ssaidi@eecs.umich.edu Tick dmaWriteDelay; 2473804Ssaidi@eecs.umich.edu 2483804Ssaidi@eecs.umich.edu Tick dmaReadFactor; 2493804Ssaidi@eecs.umich.edu Tick dmaWriteFactor; 2503804Ssaidi@eecs.umich.edu 2513804Ssaidi@eecs.umich.edu void *rxDmaData; 2523804Ssaidi@eecs.umich.edu Addr rxDmaAddr; 2533804Ssaidi@eecs.umich.edu int rxDmaLen; 2543804Ssaidi@eecs.umich.edu bool doRxDmaRead(); 2553804Ssaidi@eecs.umich.edu bool doRxDmaWrite(); 2563804Ssaidi@eecs.umich.edu 2573804Ssaidi@eecs.umich.edu void *txDmaData; 2583804Ssaidi@eecs.umich.edu Addr txDmaAddr; 2593804Ssaidi@eecs.umich.edu int txDmaLen; 2603804Ssaidi@eecs.umich.edu bool doTxDmaRead(); 2613804Ssaidi@eecs.umich.edu bool doTxDmaWrite(); 2623804Ssaidi@eecs.umich.edu 2633804Ssaidi@eecs.umich.edu void rxDmaReadDone(); 2643804Ssaidi@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>; 2653804Ssaidi@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent; 2663804Ssaidi@eecs.umich.edu 2673804Ssaidi@eecs.umich.edu void rxDmaWriteDone(); 2683804Ssaidi@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>; 2693804Ssaidi@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent; 2703804Ssaidi@eecs.umich.edu 2713804Ssaidi@eecs.umich.edu void txDmaReadDone(); 2723804Ssaidi@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>; 2733804Ssaidi@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent; 2743804Ssaidi@eecs.umich.edu 2753804Ssaidi@eecs.umich.edu void txDmaWriteDone(); 2763804Ssaidi@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>; 2773804Ssaidi@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent; 2783804Ssaidi@eecs.umich.edu 2793804Ssaidi@eecs.umich.edu bool dmaDescFree; 2803804Ssaidi@eecs.umich.edu bool dmaDataFree; 2813804Ssaidi@eecs.umich.edu 2823804Ssaidi@eecs.umich.edu protected: 2833804Ssaidi@eecs.umich.edu Tick txDelay; 2843804Ssaidi@eecs.umich.edu Tick rxDelay; 2853804Ssaidi@eecs.umich.edu 2863804Ssaidi@eecs.umich.edu void txReset(); 2873804Ssaidi@eecs.umich.edu void rxReset(); 2883804Ssaidi@eecs.umich.edu void regsReset(); 2893804Ssaidi@eecs.umich.edu 2903804Ssaidi@eecs.umich.edu void rxKick(); 2913804Ssaidi@eecs.umich.edu Tick rxKickTick; 2923804Ssaidi@eecs.umich.edu typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent; 2933804Ssaidi@eecs.umich.edu friend void RxKickEvent::process(); 2943804Ssaidi@eecs.umich.edu RxKickEvent rxKickEvent; 2953804Ssaidi@eecs.umich.edu 2963804Ssaidi@eecs.umich.edu void txKick(); 2973804Ssaidi@eecs.umich.edu Tick txKickTick; 2983804Ssaidi@eecs.umich.edu typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent; 2993804Ssaidi@eecs.umich.edu friend void TxKickEvent::process(); 3003804Ssaidi@eecs.umich.edu TxKickEvent txKickEvent; 3013804Ssaidi@eecs.umich.edu 3023804Ssaidi@eecs.umich.edu void eepromKick(); 3033804Ssaidi@eecs.umich.edu 3043804Ssaidi@eecs.umich.edu /** 3053804Ssaidi@eecs.umich.edu * Retransmit event 3063826Ssaidi@eecs.umich.edu */ 3073804Ssaidi@eecs.umich.edu void transmit(); 3083804Ssaidi@eecs.umich.edu void txEventTransmit() 3093826Ssaidi@eecs.umich.edu { 3103826Ssaidi@eecs.umich.edu transmit(); 3113826Ssaidi@eecs.umich.edu if (txState == txFifoBlock) 3123826Ssaidi@eecs.umich.edu txKick(); 3133826Ssaidi@eecs.umich.edu } 3143804Ssaidi@eecs.umich.edu typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent; 3153804Ssaidi@eecs.umich.edu friend void TxEvent::process(); 3163804Ssaidi@eecs.umich.edu TxEvent txEvent; 3173804Ssaidi@eecs.umich.edu 3183804Ssaidi@eecs.umich.edu void txDump() const; 3193811Ssaidi@eecs.umich.edu void rxDump() const; 3203811Ssaidi@eecs.umich.edu 3213804Ssaidi@eecs.umich.edu /** 3223804Ssaidi@eecs.umich.edu * receive address filter 3233804Ssaidi@eecs.umich.edu */ 3243804Ssaidi@eecs.umich.edu bool rxFilterEnable; 3253826Ssaidi@eecs.umich.edu bool rxFilter(const EthPacketPtr &packet); 3263826Ssaidi@eecs.umich.edu bool acceptBroadcast; 3273826Ssaidi@eecs.umich.edu bool acceptMulticast; 3283826Ssaidi@eecs.umich.edu bool acceptUnicast; 3293826Ssaidi@eecs.umich.edu bool acceptPerfect; 3303826Ssaidi@eecs.umich.edu bool acceptArp; 3313804Ssaidi@eecs.umich.edu bool multicastHashEnable; 3323804Ssaidi@eecs.umich.edu 3333804Ssaidi@eecs.umich.edu /** 3343811Ssaidi@eecs.umich.edu * Interrupt management 3353811Ssaidi@eecs.umich.edu */ 3363804Ssaidi@eecs.umich.edu void devIntrPost(uint32_t interrupts); 3373826Ssaidi@eecs.umich.edu void devIntrClear(uint32_t interrupts); 3383804Ssaidi@eecs.umich.edu void devIntrChangeMask(); 3393804Ssaidi@eecs.umich.edu 3403826Ssaidi@eecs.umich.edu Tick intrDelay; 3413826Ssaidi@eecs.umich.edu Tick intrTick; 3423826Ssaidi@eecs.umich.edu bool cpuPendingIntr; 3433826Ssaidi@eecs.umich.edu void cpuIntrPost(Tick when); 3443826Ssaidi@eecs.umich.edu void cpuInterrupt(); 3453826Ssaidi@eecs.umich.edu void cpuIntrClear(); 3463826Ssaidi@eecs.umich.edu 3473804Ssaidi@eecs.umich.edu typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent; 3483804Ssaidi@eecs.umich.edu friend void IntrEvent::process(); 3493804Ssaidi@eecs.umich.edu IntrEvent *intrEvent; 3503804Ssaidi@eecs.umich.edu NSGigEInt *interface; 3513833Ssaidi@eecs.umich.edu 3523833Ssaidi@eecs.umich.edu public: 3533833Ssaidi@eecs.umich.edu typedef NSGigEParams Params; 3543833Ssaidi@eecs.umich.edu const Params *params() const { return (const Params *)_params; } 3553833Ssaidi@eecs.umich.edu NSGigE(Params *params); 3563833Ssaidi@eecs.umich.edu ~NSGigE(); 3573833Ssaidi@eecs.umich.edu 3583833Ssaidi@eecs.umich.edu virtual Tick writeConfig(PacketPtr pkt); 3593833Ssaidi@eecs.umich.edu 3603833Ssaidi@eecs.umich.edu virtual Tick read(PacketPtr pkt); 3613833Ssaidi@eecs.umich.edu virtual Tick write(PacketPtr pkt); 3623833Ssaidi@eecs.umich.edu 3633804Ssaidi@eecs.umich.edu bool cpuIntrPending() const; 3643804Ssaidi@eecs.umich.edu void cpuIntrAck() { cpuIntrClear(); } 3653804Ssaidi@eecs.umich.edu 3663804Ssaidi@eecs.umich.edu bool recvPacket(EthPacketPtr packet); 3673804Ssaidi@eecs.umich.edu void transferDone(); 3683804Ssaidi@eecs.umich.edu 3693804Ssaidi@eecs.umich.edu void setInterface(NSGigEInt *i) { assert(!interface); interface = i; } 3703811Ssaidi@eecs.umich.edu 3713811Ssaidi@eecs.umich.edu virtual void serialize(std::ostream &os); 3723833Ssaidi@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3733833Ssaidi@eecs.umich.edu 3743811Ssaidi@eecs.umich.edu virtual void resume(); 3753804Ssaidi@eecs.umich.edu 3763804Ssaidi@eecs.umich.edu public: 3773804Ssaidi@eecs.umich.edu void regStats(); 3783804Ssaidi@eecs.umich.edu 3793804Ssaidi@eecs.umich.edu private: 3803804Ssaidi@eecs.umich.edu Stats::Scalar<> txBytes; 3813804Ssaidi@eecs.umich.edu Stats::Scalar<> rxBytes; 3823804Ssaidi@eecs.umich.edu Stats::Scalar<> txPackets; 3833804Ssaidi@eecs.umich.edu Stats::Scalar<> rxPackets; 3843833Ssaidi@eecs.umich.edu Stats::Scalar<> txIpChecksums; 3853804Ssaidi@eecs.umich.edu Stats::Scalar<> rxIpChecksums; 3863804Ssaidi@eecs.umich.edu Stats::Scalar<> txTcpChecksums; 3873833Ssaidi@eecs.umich.edu Stats::Scalar<> rxTcpChecksums; 3883804Ssaidi@eecs.umich.edu Stats::Scalar<> txUdpChecksums; 3893804Ssaidi@eecs.umich.edu Stats::Scalar<> rxUdpChecksums; 3903804Ssaidi@eecs.umich.edu Stats::Scalar<> descDmaReads; 3913804Ssaidi@eecs.umich.edu Stats::Scalar<> descDmaWrites; 3923804Ssaidi@eecs.umich.edu Stats::Scalar<> descDmaRdBytes; 3933826Ssaidi@eecs.umich.edu Stats::Scalar<> descDmaWrBytes; 3943804Ssaidi@eecs.umich.edu Stats::Formula totBandwidth; 3953804Ssaidi@eecs.umich.edu Stats::Formula totPackets; 3963804Ssaidi@eecs.umich.edu Stats::Formula totBytes; 3973804Ssaidi@eecs.umich.edu Stats::Formula totPacketRate; 3983804Ssaidi@eecs.umich.edu Stats::Formula txBandwidth; 3993804Ssaidi@eecs.umich.edu Stats::Formula rxBandwidth; 4003804Ssaidi@eecs.umich.edu Stats::Formula txPacketRate; 4013804Ssaidi@eecs.umich.edu Stats::Formula rxPacketRate; 4023804Ssaidi@eecs.umich.edu Stats::Scalar<> postedSwi; 4033804Ssaidi@eecs.umich.edu Stats::Formula coalescedSwi; 4043804Ssaidi@eecs.umich.edu Stats::Scalar<> totalSwi; 4053804Ssaidi@eecs.umich.edu Stats::Scalar<> postedRxIdle; 4063833Ssaidi@eecs.umich.edu Stats::Formula coalescedRxIdle; 4073804Ssaidi@eecs.umich.edu Stats::Scalar<> totalRxIdle; 4083804Ssaidi@eecs.umich.edu Stats::Scalar<> postedRxOk; 4093804Ssaidi@eecs.umich.edu Stats::Formula coalescedRxOk; 4103804Ssaidi@eecs.umich.edu Stats::Scalar<> totalRxOk; 4113804Ssaidi@eecs.umich.edu Stats::Scalar<> postedRxDesc; 4123804Ssaidi@eecs.umich.edu Stats::Formula coalescedRxDesc; 4133804Ssaidi@eecs.umich.edu Stats::Scalar<> totalRxDesc; 4143804Ssaidi@eecs.umich.edu Stats::Scalar<> postedTxOk; 4153804Ssaidi@eecs.umich.edu Stats::Formula coalescedTxOk; 4163804Ssaidi@eecs.umich.edu Stats::Scalar<> totalTxOk; 4173804Ssaidi@eecs.umich.edu Stats::Scalar<> postedTxIdle; 4183804Ssaidi@eecs.umich.edu Stats::Formula coalescedTxIdle; 4193804Ssaidi@eecs.umich.edu Stats::Scalar<> totalTxIdle; 4203804Ssaidi@eecs.umich.edu Stats::Scalar<> postedTxDesc; 4213804Ssaidi@eecs.umich.edu Stats::Formula coalescedTxDesc; 4223804Ssaidi@eecs.umich.edu Stats::Scalar<> totalTxDesc; 4233804Ssaidi@eecs.umich.edu Stats::Scalar<> postedRxOrn; 4243804Ssaidi@eecs.umich.edu Stats::Formula coalescedRxOrn; 4253804Ssaidi@eecs.umich.edu Stats::Scalar<> totalRxOrn; 4263804Ssaidi@eecs.umich.edu Stats::Formula coalescedTotal; 4273804Ssaidi@eecs.umich.edu Stats::Scalar<> postedInterrupts; 4283804Ssaidi@eecs.umich.edu Stats::Scalar<> droppedPackets; 4293826Ssaidi@eecs.umich.edu}; 4303826Ssaidi@eecs.umich.edu 4313826Ssaidi@eecs.umich.edu/* 4323804Ssaidi@eecs.umich.edu * Ethernet Interface for an Ethernet Device 4333804Ssaidi@eecs.umich.edu */ 4343804Ssaidi@eecs.umich.educlass NSGigEInt : public EtherInt 4353804Ssaidi@eecs.umich.edu{ 4363804Ssaidi@eecs.umich.edu private: 4373804Ssaidi@eecs.umich.edu NSGigE *dev; 4383804Ssaidi@eecs.umich.edu 4393804Ssaidi@eecs.umich.edu public: 4403804Ssaidi@eecs.umich.edu NSGigEInt(const std::string &name, NSGigE *d) 4413833Ssaidi@eecs.umich.edu : EtherInt(name), dev(d) { dev->setInterface(this); } 4423833Ssaidi@eecs.umich.edu 4433833Ssaidi@eecs.umich.edu virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); } 4443833Ssaidi@eecs.umich.edu virtual void sendDone() { dev->transferDone(); } 4453833Ssaidi@eecs.umich.edu}; 4463833Ssaidi@eecs.umich.edu 4473833Ssaidi@eecs.umich.edu#endif // __DEV_NS_GIGE_HH__ 4483833Ssaidi@eecs.umich.edu