ns_gige.hh revision 1817
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu */ 283804Ssaidi@eecs.umich.edu 293569Sgblack@eecs.umich.edu/** @file 303569Sgblack@eecs.umich.edu * Device module for modelling the National Semiconductor 313918Ssaidi@eecs.umich.edu * DP83820 ethernet controller 323918Ssaidi@eecs.umich.edu */ 333804Ssaidi@eecs.umich.edu 347678Sgblack@eecs.umich.edu#ifndef __DEV_NS_GIGE_HH__ 356335Sgblack@eecs.umich.edu#define __DEV_NS_GIGE_HH__ 363569Sgblack@eecs.umich.edu 373824Ssaidi@eecs.umich.edu#include "base/inet.hh" 383811Ssaidi@eecs.umich.edu#include "base/statistics.hh" 398229Snate@binkert.org#include "dev/etherint.hh" 403811Ssaidi@eecs.umich.edu#include "dev/etherpkt.hh" 418232Snate@binkert.org#include "dev/io_device.hh" 428232Snate@binkert.org#include "dev/ns_gige_reg.h" 433823Ssaidi@eecs.umich.edu#include "dev/pcidev.hh" 443823Ssaidi@eecs.umich.edu#include "dev/pktfifo.hh" 458751Sgblack@eecs.umich.edu#include "mem/bus/bus.hh" 464103Ssaidi@eecs.umich.edu#include "sim/eventq.hh" 473569Sgblack@eecs.umich.edu 483804Ssaidi@eecs.umich.edu/** 493804Ssaidi@eecs.umich.edu * Ethernet device registers 504088Sbinkertn@umich.edu */ 513569Sgblack@eecs.umich.edustruct dp_regs { 525034Smilesck@eecs.umich.edu uint32_t command; 535358Sgblack@eecs.umich.edu uint32_t config; 548374Sksewell@umich.edu uint32_t mear; 553804Ssaidi@eecs.umich.edu uint32_t ptscr; 563804Ssaidi@eecs.umich.edu uint32_t isr; 573804Ssaidi@eecs.umich.edu uint32_t imr; 585555Snate@binkert.org uint32_t ier; 593569Sgblack@eecs.umich.edu uint32_t ihr; 603804Ssaidi@eecs.umich.edu uint32_t txdp; 613918Ssaidi@eecs.umich.edu uint32_t txdp_hi; 623881Ssaidi@eecs.umich.edu uint32_t txcfg; 633881Ssaidi@eecs.umich.edu uint32_t gpior; 643881Ssaidi@eecs.umich.edu uint32_t rxdp; 654990Sgblack@eecs.umich.edu uint32_t rxdp_hi; 664990Sgblack@eecs.umich.edu uint32_t rxcfg; 674990Sgblack@eecs.umich.edu uint32_t pqcr; 684990Sgblack@eecs.umich.edu uint32_t wcsr; 694990Sgblack@eecs.umich.edu uint32_t pcr; 704990Sgblack@eecs.umich.edu uint32_t rfcr; 714990Sgblack@eecs.umich.edu uint32_t rfdr; 724990Sgblack@eecs.umich.edu uint32_t srr; 734990Sgblack@eecs.umich.edu uint32_t mibc; 746022Sgblack@eecs.umich.edu uint32_t vrcr; 756022Sgblack@eecs.umich.edu uint32_t vtcr; 766022Sgblack@eecs.umich.edu uint32_t vdr; 773804Ssaidi@eecs.umich.edu uint32_t ccsr; 783569Sgblack@eecs.umich.edu uint32_t tbicr; 793804Ssaidi@eecs.umich.edu uint32_t tbisr; 803804Ssaidi@eecs.umich.edu uint32_t tanar; 813804Ssaidi@eecs.umich.edu uint32_t tanlpar; 823804Ssaidi@eecs.umich.edu uint32_t taner; 833881Ssaidi@eecs.umich.edu uint32_t tesr; 843804Ssaidi@eecs.umich.edu}; 853804Ssaidi@eecs.umich.edu 863804Ssaidi@eecs.umich.edustruct dp_rom { 873804Ssaidi@eecs.umich.edu /** 883804Ssaidi@eecs.umich.edu * for perfect match memory. 893804Ssaidi@eecs.umich.edu * the linux driver doesn't use any other ROM 903804Ssaidi@eecs.umich.edu */ 913569Sgblack@eecs.umich.edu uint8_t perfectMatch[ETH_ADDR_LEN]; 923569Sgblack@eecs.umich.edu}; 933804Ssaidi@eecs.umich.edu 943804Ssaidi@eecs.umich.educlass NSGigEInt; 953826Ssaidi@eecs.umich.educlass PhysicalMemory; 963804Ssaidi@eecs.umich.educlass BaseInterface; 973804Ssaidi@eecs.umich.educlass HierParams; 983826Ssaidi@eecs.umich.educlass Bus; 993907Ssaidi@eecs.umich.educlass PciConfigAll; 1003826Ssaidi@eecs.umich.edu 1013811Ssaidi@eecs.umich.edu/** 1023836Ssaidi@eecs.umich.edu * NS DP83820 Ethernet device model 1033915Ssaidi@eecs.umich.edu */ 1043907Ssaidi@eecs.umich.educlass NSGigE : public PciDev 1053881Ssaidi@eecs.umich.edu{ 1063881Ssaidi@eecs.umich.edu public: 1073881Ssaidi@eecs.umich.edu /** Transmit State Machine states */ 1083881Ssaidi@eecs.umich.edu enum TxState 1093907Ssaidi@eecs.umich.edu { 1103881Ssaidi@eecs.umich.edu txIdle, 1115555Snate@binkert.org txDescRefr, 1125555Snate@binkert.org txDescRead, 1135555Snate@binkert.org txFifoBlock, 1143881Ssaidi@eecs.umich.edu txFragRead, 1153881Ssaidi@eecs.umich.edu txDescWrite, 1163907Ssaidi@eecs.umich.edu txAdvance 1173907Ssaidi@eecs.umich.edu }; 1183907Ssaidi@eecs.umich.edu 1193907Ssaidi@eecs.umich.edu /** Receive State Machine States */ 1203907Ssaidi@eecs.umich.edu enum RxState 1213907Ssaidi@eecs.umich.edu { 1223907Ssaidi@eecs.umich.edu rxIdle, 1233907Ssaidi@eecs.umich.edu rxDescRefr, 1243907Ssaidi@eecs.umich.edu rxDescRead, 1253907Ssaidi@eecs.umich.edu rxFifoBlock, 1263907Ssaidi@eecs.umich.edu rxFragWrite, 1273907Ssaidi@eecs.umich.edu rxDescWrite, 1283907Ssaidi@eecs.umich.edu rxAdvance 1293907Ssaidi@eecs.umich.edu }; 1303907Ssaidi@eecs.umich.edu 1313907Ssaidi@eecs.umich.edu enum DmaState 1323907Ssaidi@eecs.umich.edu { 1333907Ssaidi@eecs.umich.edu dmaIdle, 1343907Ssaidi@eecs.umich.edu dmaReading, 1353907Ssaidi@eecs.umich.edu dmaWriting, 1363907Ssaidi@eecs.umich.edu dmaReadWaiting, 1373826Ssaidi@eecs.umich.edu dmaWriteWaiting 1383826Ssaidi@eecs.umich.edu }; 1393826Ssaidi@eecs.umich.edu 1403826Ssaidi@eecs.umich.edu private: 1413881Ssaidi@eecs.umich.edu Addr addr; 1423881Ssaidi@eecs.umich.edu static const Addr size = sizeof(dp_regs); 1433881Ssaidi@eecs.umich.edu 1443881Ssaidi@eecs.umich.edu protected: 1453881Ssaidi@eecs.umich.edu typedef std::deque<PacketPtr> pktbuf_t; 1463881Ssaidi@eecs.umich.edu typedef pktbuf_t::iterator pktiter_t; 1473881Ssaidi@eecs.umich.edu 1483881Ssaidi@eecs.umich.edu /** device register file */ 1493881Ssaidi@eecs.umich.edu dp_regs regs; 1503881Ssaidi@eecs.umich.edu dp_rom rom; 1513881Ssaidi@eecs.umich.edu 1523881Ssaidi@eecs.umich.edu /** pci settings */ 1533881Ssaidi@eecs.umich.edu bool ioEnable; 1543881Ssaidi@eecs.umich.edu#if 0 1553569Sgblack@eecs.umich.edu bool memEnable; 1563569Sgblack@eecs.umich.edu bool bmEnable; 1573881Ssaidi@eecs.umich.edu#endif 1583804Ssaidi@eecs.umich.edu 1593881Ssaidi@eecs.umich.edu /*** BASIC STRUCTURES FOR TX/RX ***/ 1603826Ssaidi@eecs.umich.edu /* Data FIFOs */ 1613881Ssaidi@eecs.umich.edu PacketFifo txFifo; 1623881Ssaidi@eecs.umich.edu PacketFifo rxFifo; 1633881Ssaidi@eecs.umich.edu 1643907Ssaidi@eecs.umich.edu /** various helper vars */ 1653907Ssaidi@eecs.umich.edu PacketPtr txPacket; 1663929Ssaidi@eecs.umich.edu PacketPtr rxPacket; 1673929Ssaidi@eecs.umich.edu uint8_t *txPacketBufPtr; 1683907Ssaidi@eecs.umich.edu uint8_t *rxPacketBufPtr; 1693907Ssaidi@eecs.umich.edu uint32_t txXferLen; 1703804Ssaidi@eecs.umich.edu uint32_t rxXferLen; 1713804Ssaidi@eecs.umich.edu bool rxDmaFree; 1723881Ssaidi@eecs.umich.edu bool txDmaFree; 1733804Ssaidi@eecs.umich.edu 1743804Ssaidi@eecs.umich.edu /** DescCaches */ 1753804Ssaidi@eecs.umich.edu ns_desc txDescCache; 1763804Ssaidi@eecs.umich.edu ns_desc rxDescCache; 1773804Ssaidi@eecs.umich.edu 1783804Ssaidi@eecs.umich.edu /* state machine cycle time */ 1793804Ssaidi@eecs.umich.edu Tick clock; 1803569Sgblack@eecs.umich.edu inline Tick cycles(int numCycles) const { return numCycles * clock; } 1813863Ssaidi@eecs.umich.edu 1823863Ssaidi@eecs.umich.edu /* tx State Machine */ 1833804Ssaidi@eecs.umich.edu TxState txState; 1845555Snate@binkert.org bool txEnable; 1855555Snate@binkert.org 1863804Ssaidi@eecs.umich.edu /** Current Transmit Descriptor Done */ 1873804Ssaidi@eecs.umich.edu bool CTDD; 1883804Ssaidi@eecs.umich.edu /** halt the tx state machine after next packet */ 1893804Ssaidi@eecs.umich.edu bool txHalt; 1903804Ssaidi@eecs.umich.edu /** ptr to the next byte in the current fragment */ 1913569Sgblack@eecs.umich.edu Addr txFragPtr; 1923804Ssaidi@eecs.umich.edu /** count of bytes remaining in the current descriptor */ 1933804Ssaidi@eecs.umich.edu uint32_t txDescCnt; 1943804Ssaidi@eecs.umich.edu DmaState txDmaState; 1955555Snate@binkert.org 1965555Snate@binkert.org /** rx State Machine */ 1973804Ssaidi@eecs.umich.edu RxState rxState; 1983804Ssaidi@eecs.umich.edu bool rxEnable; 1993804Ssaidi@eecs.umich.edu 2003804Ssaidi@eecs.umich.edu /** Current Receive Descriptor Done */ 2013804Ssaidi@eecs.umich.edu bool CRDD; 2023811Ssaidi@eecs.umich.edu /** num of bytes in the current packet being drained from rxDataFifo */ 2033811Ssaidi@eecs.umich.edu uint32_t rxPktBytes; 2043804Ssaidi@eecs.umich.edu /** halt the rx state machine after current packet */ 2053804Ssaidi@eecs.umich.edu bool rxHalt; 2065312Sgblack@eecs.umich.edu /** ptr to the next byte in current fragment */ 2073804Ssaidi@eecs.umich.edu Addr rxFragPtr; 2083804Ssaidi@eecs.umich.edu /** count of bytes remaining in the current descriptor */ 2093804Ssaidi@eecs.umich.edu uint32_t rxDescCnt; 2103804Ssaidi@eecs.umich.edu DmaState rxDmaState; 2113804Ssaidi@eecs.umich.edu 2123804Ssaidi@eecs.umich.edu bool extstsEnable; 2133804Ssaidi@eecs.umich.edu 2143811Ssaidi@eecs.umich.edu protected: 2153804Ssaidi@eecs.umich.edu Tick dmaReadDelay; 2163804Ssaidi@eecs.umich.edu Tick dmaWriteDelay; 2173804Ssaidi@eecs.umich.edu 2183804Ssaidi@eecs.umich.edu Tick dmaReadFactor; 2193804Ssaidi@eecs.umich.edu Tick dmaWriteFactor; 2203826Ssaidi@eecs.umich.edu 2213826Ssaidi@eecs.umich.edu void *rxDmaData; 2224070Ssaidi@eecs.umich.edu Addr rxDmaAddr; 2235555Snate@binkert.org int rxDmaLen; 2245555Snate@binkert.org bool doRxDmaRead(); 2254070Ssaidi@eecs.umich.edu bool doRxDmaWrite(); 2263804Ssaidi@eecs.umich.edu void rxDmaReadCopy(); 2273804Ssaidi@eecs.umich.edu void rxDmaWriteCopy(); 2283804Ssaidi@eecs.umich.edu 2293804Ssaidi@eecs.umich.edu void *txDmaData; 2303804Ssaidi@eecs.umich.edu Addr txDmaAddr; 2313804Ssaidi@eecs.umich.edu int txDmaLen; 2323804Ssaidi@eecs.umich.edu bool doTxDmaRead(); 2333804Ssaidi@eecs.umich.edu bool doTxDmaWrite(); 2343804Ssaidi@eecs.umich.edu void txDmaReadCopy(); 2353804Ssaidi@eecs.umich.edu void txDmaWriteCopy(); 2363804Ssaidi@eecs.umich.edu 2373804Ssaidi@eecs.umich.edu void rxDmaReadDone(); 2383826Ssaidi@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>; 2393826Ssaidi@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent; 2403826Ssaidi@eecs.umich.edu 2413863Ssaidi@eecs.umich.edu void rxDmaWriteDone(); 2423826Ssaidi@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>; 2433826Ssaidi@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent; 2443826Ssaidi@eecs.umich.edu 2453826Ssaidi@eecs.umich.edu void txDmaReadDone(); 2463826Ssaidi@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>; 2473826Ssaidi@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent; 2483826Ssaidi@eecs.umich.edu 2493826Ssaidi@eecs.umich.edu void txDmaWriteDone(); 2503826Ssaidi@eecs.umich.edu friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>; 2513804Ssaidi@eecs.umich.edu EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent; 2523804Ssaidi@eecs.umich.edu 2533804Ssaidi@eecs.umich.edu bool dmaDescFree; 2543804Ssaidi@eecs.umich.edu bool dmaDataFree; 2553804Ssaidi@eecs.umich.edu 2563804Ssaidi@eecs.umich.edu 2573804Ssaidi@eecs.umich.edu protected: 2583863Ssaidi@eecs.umich.edu Tick txDelay; 2593863Ssaidi@eecs.umich.edu Tick rxDelay; 2603863Ssaidi@eecs.umich.edu 2613836Ssaidi@eecs.umich.edu void txReset(); 2623836Ssaidi@eecs.umich.edu void rxReset(); 2633804Ssaidi@eecs.umich.edu void regsReset(); 2643804Ssaidi@eecs.umich.edu 2655312Sgblack@eecs.umich.edu void rxKick(); 2663804Ssaidi@eecs.umich.edu Tick rxKickTick; 2673804Ssaidi@eecs.umich.edu typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent; 2683804Ssaidi@eecs.umich.edu friend void RxKickEvent::process(); 2693804Ssaidi@eecs.umich.edu RxKickEvent rxKickEvent; 2703804Ssaidi@eecs.umich.edu 2713804Ssaidi@eecs.umich.edu void txKick(); 2723804Ssaidi@eecs.umich.edu Tick txKickTick; 2733863Ssaidi@eecs.umich.edu typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent; 2743804Ssaidi@eecs.umich.edu friend void TxKickEvent::process(); 2753804Ssaidi@eecs.umich.edu TxKickEvent txKickEvent; 2763804Ssaidi@eecs.umich.edu 2773804Ssaidi@eecs.umich.edu /** 2783804Ssaidi@eecs.umich.edu * Retransmit event 2793881Ssaidi@eecs.umich.edu */ 2803804Ssaidi@eecs.umich.edu void transmit(); 2813804Ssaidi@eecs.umich.edu void txEventTransmit() 2823804Ssaidi@eecs.umich.edu { 2833804Ssaidi@eecs.umich.edu transmit(); 2843804Ssaidi@eecs.umich.edu if (txState == txFifoBlock) 2853804Ssaidi@eecs.umich.edu txKick(); 2863804Ssaidi@eecs.umich.edu } 2873863Ssaidi@eecs.umich.edu typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent; 2883863Ssaidi@eecs.umich.edu friend void TxEvent::process(); 2893836Ssaidi@eecs.umich.edu TxEvent txEvent; 2905555Snate@binkert.org 2913804Ssaidi@eecs.umich.edu void txDump() const; 2923804Ssaidi@eecs.umich.edu void rxDump() const; 2933881Ssaidi@eecs.umich.edu 2943881Ssaidi@eecs.umich.edu /** 2953881Ssaidi@eecs.umich.edu * receive address filter 2963804Ssaidi@eecs.umich.edu */ 2973804Ssaidi@eecs.umich.edu bool rxFilterEnable; 2983804Ssaidi@eecs.umich.edu bool rxFilter(const PacketPtr &packet); 2993804Ssaidi@eecs.umich.edu bool acceptBroadcast; 3003804Ssaidi@eecs.umich.edu bool acceptMulticast; 3013804Ssaidi@eecs.umich.edu bool acceptUnicast; 3023804Ssaidi@eecs.umich.edu bool acceptPerfect; 3033804Ssaidi@eecs.umich.edu bool acceptArp; 3043804Ssaidi@eecs.umich.edu 3053804Ssaidi@eecs.umich.edu PhysicalMemory *physmem; 3063804Ssaidi@eecs.umich.edu 3073804Ssaidi@eecs.umich.edu /** 3083804Ssaidi@eecs.umich.edu * Interrupt management 3093863Ssaidi@eecs.umich.edu */ 3103836Ssaidi@eecs.umich.edu void devIntrPost(uint32_t interrupts); 3115555Snate@binkert.org void devIntrClear(uint32_t interrupts); 3125288Sgblack@eecs.umich.edu void devIntrChangeMask(); 3135288Sgblack@eecs.umich.edu 3145288Sgblack@eecs.umich.edu Tick intrDelay; 3153804Ssaidi@eecs.umich.edu Tick intrTick; 3163804Ssaidi@eecs.umich.edu bool cpuPendingIntr; 3173804Ssaidi@eecs.umich.edu void cpuIntrPost(Tick when); 3183804Ssaidi@eecs.umich.edu void cpuInterrupt(); 3193804Ssaidi@eecs.umich.edu void cpuIntrClear(); 3203804Ssaidi@eecs.umich.edu 3213804Ssaidi@eecs.umich.edu typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent; 3223804Ssaidi@eecs.umich.edu friend void IntrEvent::process(); 3233804Ssaidi@eecs.umich.edu IntrEvent *intrEvent; 3243804Ssaidi@eecs.umich.edu NSGigEInt *interface; 3253804Ssaidi@eecs.umich.edu 3269423SAndreas.Sandberg@arm.com public: 3273804Ssaidi@eecs.umich.edu struct Params : public PciDev::Params 3283836Ssaidi@eecs.umich.edu { 3295555Snate@binkert.org PhysicalMemory *pmem; 3303836Ssaidi@eecs.umich.edu HierParams *hier; 3315555Snate@binkert.org Bus *header_bus; 3323881Ssaidi@eecs.umich.edu Bus *payload_bus; 3333881Ssaidi@eecs.umich.edu Tick clock; 3343804Ssaidi@eecs.umich.edu Tick intr_delay; 3353907Ssaidi@eecs.umich.edu Tick tx_delay; 3363804Ssaidi@eecs.umich.edu Tick rx_delay; 3373804Ssaidi@eecs.umich.edu Tick pio_latency; 3383804Ssaidi@eecs.umich.edu bool dma_desc_free; 3393804Ssaidi@eecs.umich.edu bool dma_data_free; 3403804Ssaidi@eecs.umich.edu Tick dma_read_delay; 3415555Snate@binkert.org Tick dma_write_delay; 3425555Snate@binkert.org Tick dma_read_factor; 3433881Ssaidi@eecs.umich.edu Tick dma_write_factor; 3443881Ssaidi@eecs.umich.edu bool rx_filter; 3453881Ssaidi@eecs.umich.edu Net::EthAddr eaddr; 3463804Ssaidi@eecs.umich.edu uint32_t tx_fifo_size; 3473881Ssaidi@eecs.umich.edu uint32_t rx_fifo_size; 3483881Ssaidi@eecs.umich.edu uint32_t m5reg; 3493881Ssaidi@eecs.umich.edu bool dma_no_allocate; 3503881Ssaidi@eecs.umich.edu }; 3513804Ssaidi@eecs.umich.edu 3523804Ssaidi@eecs.umich.edu NSGigE(Params *params); 3533804Ssaidi@eecs.umich.edu ~NSGigE(); 3545555Snate@binkert.org const Params *params() const { return (const Params *)_params; } 3555555Snate@binkert.org 3563804Ssaidi@eecs.umich.edu virtual void writeConfig(int offset, int size, const uint8_t *data); 3573804Ssaidi@eecs.umich.edu virtual void readConfig(int offset, int size, uint8_t *data); 3583881Ssaidi@eecs.umich.edu 3593881Ssaidi@eecs.umich.edu virtual Fault read(MemReqPtr &req, uint8_t *data); 3603804Ssaidi@eecs.umich.edu virtual Fault write(MemReqPtr &req, const uint8_t *data); 3613881Ssaidi@eecs.umich.edu 3623881Ssaidi@eecs.umich.edu bool cpuIntrPending() const; 3633881Ssaidi@eecs.umich.edu void cpuIntrAck() { cpuIntrClear(); } 3643804Ssaidi@eecs.umich.edu 3653804Ssaidi@eecs.umich.edu bool recvPacket(PacketPtr packet); 3663804Ssaidi@eecs.umich.edu void transferDone(); 3673804Ssaidi@eecs.umich.edu 3683804Ssaidi@eecs.umich.edu void setInterface(NSGigEInt *i) { assert(!interface); interface = i; } 3693804Ssaidi@eecs.umich.edu 3703804Ssaidi@eecs.umich.edu virtual void serialize(std::ostream &os); 3713804Ssaidi@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3723804Ssaidi@eecs.umich.edu 3733804Ssaidi@eecs.umich.edu public: 3743804Ssaidi@eecs.umich.edu void regStats(); 3753804Ssaidi@eecs.umich.edu 3763804Ssaidi@eecs.umich.edu private: 3773804Ssaidi@eecs.umich.edu Stats::Scalar<> txBytes; 3783804Ssaidi@eecs.umich.edu Stats::Scalar<> rxBytes; 3793804Ssaidi@eecs.umich.edu Stats::Scalar<> txPackets; 3804990Sgblack@eecs.umich.edu Stats::Scalar<> rxPackets; 3813804Ssaidi@eecs.umich.edu Stats::Scalar<> txIpChecksums; 3823804Ssaidi@eecs.umich.edu Stats::Scalar<> rxIpChecksums; 3833804Ssaidi@eecs.umich.edu Stats::Scalar<> txTcpChecksums; 3843804Ssaidi@eecs.umich.edu Stats::Scalar<> rxTcpChecksums; 3853804Ssaidi@eecs.umich.edu Stats::Scalar<> txUdpChecksums; 3863804Ssaidi@eecs.umich.edu Stats::Scalar<> rxUdpChecksums; 3873804Ssaidi@eecs.umich.edu Stats::Scalar<> descDmaReads; 3883804Ssaidi@eecs.umich.edu Stats::Scalar<> descDmaWrites; 3893804Ssaidi@eecs.umich.edu Stats::Scalar<> descDmaRdBytes; 3903804Ssaidi@eecs.umich.edu Stats::Scalar<> descDmaWrBytes; 3913804Ssaidi@eecs.umich.edu Stats::Formula totBandwidth; 3923804Ssaidi@eecs.umich.edu Stats::Formula totPackets; 3933804Ssaidi@eecs.umich.edu Stats::Formula totBytes; 3943804Ssaidi@eecs.umich.edu Stats::Formula totPacketRate; 3953804Ssaidi@eecs.umich.edu Stats::Formula txBandwidth; 3963826Ssaidi@eecs.umich.edu Stats::Formula rxBandwidth; 3974990Sgblack@eecs.umich.edu Stats::Formula txPacketRate; 3983826Ssaidi@eecs.umich.edu Stats::Formula rxPacketRate; 3993916Ssaidi@eecs.umich.edu Stats::Scalar<> postedSwi; 4003916Ssaidi@eecs.umich.edu Stats::Formula coalescedSwi; 4013916Ssaidi@eecs.umich.edu Stats::Scalar<> totalSwi; 4024990Sgblack@eecs.umich.edu Stats::Scalar<> postedRxIdle; 4033826Ssaidi@eecs.umich.edu Stats::Formula coalescedRxIdle; 4043804Ssaidi@eecs.umich.edu Stats::Scalar<> totalRxIdle; 4053804Ssaidi@eecs.umich.edu Stats::Scalar<> postedRxOk; 4066022Sgblack@eecs.umich.edu Stats::Formula coalescedRxOk; 4073804Ssaidi@eecs.umich.edu Stats::Scalar<> totalRxOk; 4083804Ssaidi@eecs.umich.edu Stats::Scalar<> postedRxDesc; 4096022Sgblack@eecs.umich.edu Stats::Formula coalescedRxDesc; 4103811Ssaidi@eecs.umich.edu Stats::Scalar<> totalRxDesc; 4114990Sgblack@eecs.umich.edu Stats::Scalar<> postedTxOk; 4124990Sgblack@eecs.umich.edu Stats::Formula coalescedTxOk; 4133804Ssaidi@eecs.umich.edu Stats::Scalar<> totalTxOk; 4143804Ssaidi@eecs.umich.edu Stats::Scalar<> postedTxIdle; 4153804Ssaidi@eecs.umich.edu Stats::Formula coalescedTxIdle; 4166022Sgblack@eecs.umich.edu Stats::Scalar<> totalTxIdle; 4173804Ssaidi@eecs.umich.edu Stats::Scalar<> postedTxDesc; 4184172Ssaidi@eecs.umich.edu Stats::Formula coalescedTxDesc; 4193833Ssaidi@eecs.umich.edu Stats::Scalar<> totalTxDesc; 4203836Ssaidi@eecs.umich.edu Stats::Scalar<> postedRxOrn; 4213836Ssaidi@eecs.umich.edu Stats::Formula coalescedRxOrn; 4223836Ssaidi@eecs.umich.edu Stats::Scalar<> totalRxOrn; 4233836Ssaidi@eecs.umich.edu Stats::Formula coalescedTotal; 4243836Ssaidi@eecs.umich.edu Stats::Scalar<> postedInterrupts; 4253836Ssaidi@eecs.umich.edu Stats::Scalar<> droppedPackets; 4263836Ssaidi@eecs.umich.edu 4273836Ssaidi@eecs.umich.edu public: 4283836Ssaidi@eecs.umich.edu Tick cacheAccess(MemReqPtr &req); 4293836Ssaidi@eecs.umich.edu}; 4306022Sgblack@eecs.umich.edu 4316022Sgblack@eecs.umich.edu/* 4326022Sgblack@eecs.umich.edu * Ethernet Interface for an Ethernet Device 4336022Sgblack@eecs.umich.edu */ 4345555Snate@binkert.orgclass NSGigEInt : public EtherInt 4353836Ssaidi@eecs.umich.edu{ 4363836Ssaidi@eecs.umich.edu private: 4373836Ssaidi@eecs.umich.edu NSGigE *dev; 4383836Ssaidi@eecs.umich.edu 4393836Ssaidi@eecs.umich.edu public: 4403836Ssaidi@eecs.umich.edu NSGigEInt(const std::string &name, NSGigE *d) 4413836Ssaidi@eecs.umich.edu : EtherInt(name), dev(d) { dev->setInterface(this); } 4423833Ssaidi@eecs.umich.edu 4433833Ssaidi@eecs.umich.edu virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); } 4443833Ssaidi@eecs.umich.edu virtual void sendDone() { dev->transferDone(); } 4453833Ssaidi@eecs.umich.edu}; 4463833Ssaidi@eecs.umich.edu 4473833Ssaidi@eecs.umich.edu#endif // __DEV_NS_GIGE_HH__ 4483833Ssaidi@eecs.umich.edu