ns_gige.hh revision 1762
12SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292SN/A/** @file 302SN/A * Device module for modelling the National Semiconductor 312439SN/A * DP83820 ethernet controller 322984Sgblack@eecs.umich.edu */ 33146SN/A 34146SN/A#ifndef __DEV_NS_GIGE_HH__ 35146SN/A#define __DEV_NS_GIGE_HH__ 36146SN/A 37146SN/A#include "base/inet.hh" 38146SN/A#include "base/statistics.hh" 391717SN/A#include "dev/etherint.hh" 40146SN/A#include "dev/etherpkt.hh" 411717SN/A#include "dev/io_device.hh" 42146SN/A#include "dev/ns_gige_reg.h" 431977SN/A#include "dev/pcidev.hh" 442623SN/A#include "dev/pktfifo.hh" 452683Sktlim@umich.edu#include "mem/bus/bus.hh" 461717SN/A#include "sim/eventq.hh" 47146SN/A 482683Sktlim@umich.edu/** 493348Sbinkertn@umich.edu * Ethernet device registers 502036SN/A */ 51146SN/Astruct dp_regs { 5256SN/A uint32_t command; 5356SN/A uint32_t config; 5456SN/A uint32_t mear; 55695SN/A uint32_t ptscr; 562901Ssaidi@eecs.umich.edu uint32_t isr; 572SN/A uint32_t imr; 581858SN/A uint32_t ier; 593565Sgblack@eecs.umich.edu uint32_t ihr; 603565Sgblack@eecs.umich.edu uint32_t txdp; 612171SN/A uint32_t txdp_hi; 622170SN/A uint32_t txcfg; 633562Sgblack@eecs.umich.edu uint32_t gpior; 64146SN/A uint32_t rxdp; 652462SN/A uint32_t rxdp_hi; 66146SN/A uint32_t rxcfg; 672SN/A uint32_t pqcr; 685529Snate@binkert.org uint32_t wcsr; 695529Snate@binkert.org uint32_t pcr; 702SN/A uint32_t rfcr; 712449SN/A uint32_t rfdr; 721355SN/A uint32_t srr; 735529Snate@binkert.org uint32_t mibc; 744495Sacolyte@umich.edu uint32_t vrcr; 75224SN/A uint32_t vtcr; 761858SN/A uint32_t vdr; 772683Sktlim@umich.edu uint32_t ccsr; 782420SN/A uint32_t tbicr; 795529Snate@binkert.org uint32_t tbisr; 804997Sgblack@eecs.umich.edu uint32_t tanar; 812420SN/A uint32_t tanlpar; 822SN/A uint32_t taner; 834400Srdreslin@umich.edu uint32_t tesr; 842672Sktlim@umich.edu}; 852683Sktlim@umich.edu 862SN/Astruct dp_rom { 872SN/A /** 88334SN/A * for perfect match memory. 89140SN/A * the linux driver doesn't use any other ROM 90334SN/A */ 912SN/A uint8_t perfectMatch[ETH_ADDR_LEN]; 922SN/A}; 932SN/A 942680Sktlim@umich.educlass NSGigEInt; 954377Sgblack@eecs.umich.educlass PhysicalMemory; 965169Ssaidi@eecs.umich.educlass BaseInterface; 974377Sgblack@eecs.umich.educlass HierParams; 984377Sgblack@eecs.umich.educlass Bus; 992SN/Aclass PciConfigAll; 1002SN/A 1012623SN/A/** 1022SN/A * NS DP82830 Ethernet device model 1032SN/A */ 1042SN/Aclass NSGigE : public PciDev 105180SN/A{ 1062623SN/A public: 107393SN/A /** Transmit State Machine states */ 108393SN/A enum TxState 109393SN/A { 110393SN/A txIdle, 111384SN/A txDescRefr, 112384SN/A txDescRead, 113393SN/A txFifoBlock, 1142623SN/A txFragRead, 115393SN/A txDescWrite, 116393SN/A txAdvance 117393SN/A }; 118393SN/A 119384SN/A /** Receive State Machine States */ 120189SN/A enum RxState 121189SN/A { 1222623SN/A rxIdle, 1232SN/A rxDescRefr, 124729SN/A rxDescRead, 125334SN/A rxFifoBlock, 1262SN/A rxFragWrite, 1272SN/A rxDescWrite, 1282SN/A rxAdvance 1292SN/A }; 1302SN/A 1312SN/A enum DmaState 1322SN/A { 1332SN/A dmaIdle, 1342SN/A dmaReading, 1352SN/A dmaWriting, 1362SN/A dmaReadWaiting, 1372SN/A dmaWriteWaiting 1381001SN/A }; 1391001SN/A 1401001SN/A private: 1411001SN/A Addr addr; 1421001SN/A static const Addr size = sizeof(dp_regs); 1432SN/A 1442SN/A protected: 1452SN/A typedef std::deque<PacketPtr> pktbuf_t; 1462SN/A typedef pktbuf_t::iterator pktiter_t; 1472SN/A 1482SN/A /** device register file */ 1492SN/A dp_regs regs; 1502SN/A dp_rom rom; 1512SN/A 1522SN/A /** pci settings */ 1532SN/A bool ioEnable; 1542SN/A#if 0 1552SN/A bool memEnable; 1562SN/A bool bmEnable; 1572SN/A#endif 1582SN/A 1592SN/A /*** BASIC STRUCTURES FOR TX/RX ***/ 1602390SN/A /* Data FIFOs */ 1612390SN/A PacketFifo txFifo; 1622390SN/A PacketFifo rxFifo; 1632390SN/A 1642390SN/A /** various helper vars */ 1652390SN/A PacketPtr txPacket; 1662390SN/A PacketPtr rxPacket; 1672390SN/A uint8_t *txPacketBufPtr; 1682390SN/A uint8_t *rxPacketBufPtr; 1692390SN/A uint32_t txXferLen; 1702390SN/A uint32_t rxXferLen; 1712390SN/A bool rxDmaFree; 172385SN/A bool txDmaFree; 1732SN/A 1742SN/A /** DescCaches */ 1752SN/A ns_desc txDescCache; 1762623SN/A ns_desc rxDescCache; 177334SN/A 1782361SN/A /* state machine cycle time */ 1795496Ssaidi@eecs.umich.edu Tick clock; 180334SN/A inline Tick cycles(int numCycles) const { return numCycles * clock; } 181334SN/A 182334SN/A /* tx State Machine */ 1832623SN/A TxState txState; 1842SN/A bool txEnable; 1855496Ssaidi@eecs.umich.edu 186921SN/A /** Current Transmit Descriptor Done */ 1872915Sktlim@umich.edu bool CTDD; 1882915Sktlim@umich.edu /** halt the tx state machine after next packet */ 1892683Sktlim@umich.edu bool txHalt; 1902SN/A /** ptr to the next byte in the current fragment */ 1912SN/A Addr txFragPtr; 1922SN/A /** count of bytes remaining in the current descriptor */ 1932623SN/A uint32_t txDescCnt; 1942SN/A DmaState txDmaState; 1955496Ssaidi@eecs.umich.edu 196921SN/A /** rx State Machine */ 1972915Sktlim@umich.edu RxState rxState; 1982915Sktlim@umich.edu bool rxEnable; 1992SN/A 2002SN/A /** Current Receive Descriptor Done */ 2012SN/A bool CRDD; 2022SN/A /** num of bytes in the current packet being drained from rxDataFifo */ 2032SN/A uint32_t rxPktBytes; 2042SN/A /** halt the rx state machine after current packet */ 2052SN/A bool rxHalt; 206595SN/A /** ptr to the next byte in current fragment */ 2072623SN/A Addr rxFragPtr; 208595SN/A /** count of bytes remaining in the current descriptor */ 2092390SN/A uint32_t rxDescCnt; 2101080SN/A DmaState rxDmaState; 2111080SN/A 2121080SN/A bool extstsEnable; 2131080SN/A 2141080SN/A protected: 2151080SN/A Tick dmaReadDelay; 2161080SN/A Tick dmaWriteDelay; 2171121SN/A 2182107SN/A Tick dmaReadFactor; 2191089SN/A Tick dmaWriteFactor; 2201089SN/A 2211080SN/A void *rxDmaData; 2221080SN/A Addr rxDmaAddr; 2231080SN/A int rxDmaLen; 2241080SN/A bool doRxDmaRead(); 225595SN/A bool doRxDmaWrite(); 2262623SN/A void rxDmaReadCopy(); 2272683Sktlim@umich.edu void rxDmaWriteCopy(); 228595SN/A 2292090SN/A void *txDmaData; 2302683Sktlim@umich.edu Addr txDmaAddr; 2312683Sktlim@umich.edu int txDmaLen; 232595SN/A bool doTxDmaRead(); 2332205SN/A bool doTxDmaWrite(); 2342205SN/A void txDmaReadCopy(); 2352683Sktlim@umich.edu void txDmaWriteCopy(); 2362683Sktlim@umich.edu 237595SN/A void rxDmaReadDone(); 238595SN/A friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>; 2392390SN/A EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent; 2402423SN/A 2412390SN/A void rxDmaWriteDone(); 242595SN/A friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>; 243595SN/A EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent; 244595SN/A 2452623SN/A void txDmaReadDone(); 246595SN/A friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>; 2472390SN/A EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent; 2481080SN/A 249595SN/A void txDmaWriteDone(); 2501080SN/A friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>; 2511080SN/A EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent; 252595SN/A 2532683Sktlim@umich.edu bool dmaDescFree; 2541080SN/A bool dmaDataFree; 2551080SN/A 2561080SN/A 2571121SN/A protected: 2582107SN/A Tick txDelay; 2591089SN/A Tick rxDelay; 2601080SN/A 2611089SN/A void txReset(); 2621080SN/A void rxReset(); 2631080SN/A void regsReset(); 2641080SN/A 265595SN/A void rxKick(); 2662683Sktlim@umich.edu Tick rxKickTick; 2671080SN/A typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent; 2682090SN/A friend void RxKickEvent::process(); 2691080SN/A 270595SN/A void txKick(); 2712683Sktlim@umich.edu Tick txKickTick; 2722683Sktlim@umich.edu typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent; 273595SN/A friend void TxKickEvent::process(); 2742683Sktlim@umich.edu 2751098SN/A /** 2761098SN/A * Retransmit event 2771098SN/A */ 2782683Sktlim@umich.edu void transmit(); 2791098SN/A void txEventTransmit() 2801098SN/A { 2811098SN/A transmit(); 2822012SN/A if (txState == txFifoBlock) 2831098SN/A txKick(); 2841098SN/A } 285595SN/A typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent; 2862205SN/A friend void TxEvent::process(); 2872205SN/A TxEvent txEvent; 2882205SN/A 289595SN/A void txDump() const; 2902390SN/A void rxDump() const; 2912420SN/A 2922423SN/A /** 2932390SN/A * receive address filter 294595SN/A */ 295595SN/A bool rxFilterEnable; 2961858SN/A bool rxFilter(const PacketPtr &packet); 2972SN/A bool acceptBroadcast; 2982623SN/A bool acceptMulticast; 2992SN/A bool acceptUnicast; 3002680Sktlim@umich.edu bool acceptPerfect; 3012SN/A bool acceptArp; 3022SN/A 3032SN/A PhysicalMemory *physmem; 3041858SN/A 3052SN/A /** 3065807Snate@binkert.org * Interrupt management 3072SN/A */ 3085807Snate@binkert.org void devIntrPost(uint32_t interrupts); 3095807Snate@binkert.org void devIntrClear(uint32_t interrupts); 3102SN/A void devIntrChangeMask(); 3115807Snate@binkert.org 3125807Snate@binkert.org Tick intrDelay; 3132SN/A Tick intrTick; 3142SN/A bool cpuPendingIntr; 3152SN/A void cpuIntrPost(Tick when); 3162SN/A void cpuInterrupt(); 3172623SN/A void cpuIntrClear(); 3182SN/A 3191858SN/A typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent; 3205704Snate@binkert.org friend void IntrEvent::process(); 3215647Sgblack@eecs.umich.edu IntrEvent *intrEvent; 3222SN/A NSGigEInt *interface; 3233520Sgblack@eecs.umich.edu 3245835Sgblack@eecs.umich.edu public: 3255647Sgblack@eecs.umich.edu struct Params : public PciDev::Params 3263520Sgblack@eecs.umich.edu { 3272SN/A PhysicalMemory *pmem; 3282SN/A HierParams *hier; 3292SN/A Bus *header_bus; 3302623SN/A Bus *payload_bus; 3312SN/A Tick clock; 3322623SN/A Tick intr_delay; 3335894Sgblack@eecs.umich.edu Tick tx_delay; 3342662Sstever@eecs.umich.edu Tick rx_delay; 3352623SN/A Tick pio_latency; 3364514Ssaidi@eecs.umich.edu bool dma_desc_free; 3374495Sacolyte@umich.edu bool dma_data_free; 3382623SN/A Tick dma_read_delay; 3393093Sksewell@umich.edu Tick dma_write_delay; 3404495Sacolyte@umich.edu Tick dma_read_factor; 3413093Sksewell@umich.edu Tick dma_write_factor; 3423093Sksewell@umich.edu bool rx_filter; 3434564Sgblack@eecs.umich.edu Net::EthAddr eaddr; 3442741Sksewell@umich.edu uint32_t tx_fifo_size; 3452741Sksewell@umich.edu uint32_t rx_fifo_size; 3462623SN/A uint32_t m5reg; 3474564Sgblack@eecs.umich.edu bool dma_no_allocate; 3484564Sgblack@eecs.umich.edu }; 3492623SN/A 3502623SN/A NSGigE(Params *params); 3512623SN/A ~NSGigE(); 3522623SN/A const Params *params() const { return (const Params *)_params; } 3532623SN/A 3542623SN/A virtual void WriteConfig(int offset, int size, uint32_t data); 3552SN/A virtual void ReadConfig(int offset, int size, uint8_t *data); 3562683Sktlim@umich.edu 3572427SN/A virtual Fault read(MemReqPtr &req, uint8_t *data); 3582683Sktlim@umich.edu virtual Fault write(MemReqPtr &req, const uint8_t *data); 3592427SN/A 3602SN/A bool cpuIntrPending() const; 3612623SN/A void cpuIntrAck() { cpuIntrClear(); } 3622623SN/A 3632SN/A bool recvPacket(PacketPtr packet); 3642623SN/A void transferDone(); 3652623SN/A 3664377Sgblack@eecs.umich.edu void setInterface(NSGigEInt *i) { assert(!interface); interface = i; } 3675665Sgblack@eecs.umich.edu 3684377Sgblack@eecs.umich.edu virtual void serialize(std::ostream &os); 3695665Sgblack@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3705665Sgblack@eecs.umich.edu 3715665Sgblack@eecs.umich.edu public: 3725665Sgblack@eecs.umich.edu void regStats(); 3735665Sgblack@eecs.umich.edu 3744181Sgblack@eecs.umich.edu private: 3754181Sgblack@eecs.umich.edu Stats::Scalar<> txBytes; 3764181Sgblack@eecs.umich.edu Stats::Scalar<> rxBytes; 3774182Sgblack@eecs.umich.edu Stats::Scalar<> txPackets; 3784182Sgblack@eecs.umich.edu Stats::Scalar<> rxPackets; 3794182Sgblack@eecs.umich.edu Stats::Scalar<> txIpChecksums; 3804593Sgblack@eecs.umich.edu Stats::Scalar<> rxIpChecksums; 3814593Sgblack@eecs.umich.edu Stats::Scalar<> txTcpChecksums; 3824593Sgblack@eecs.umich.edu Stats::Scalar<> rxTcpChecksums; 3834593Sgblack@eecs.umich.edu Stats::Scalar<> txUdpChecksums; 3844593Sgblack@eecs.umich.edu Stats::Scalar<> rxUdpChecksums; 3854377Sgblack@eecs.umich.edu Stats::Scalar<> descDmaReads; 3864377Sgblack@eecs.umich.edu Stats::Scalar<> descDmaWrites; 3874377Sgblack@eecs.umich.edu Stats::Scalar<> descDmaRdBytes; 3884377Sgblack@eecs.umich.edu Stats::Scalar<> descDmaWrBytes; 3894377Sgblack@eecs.umich.edu Stats::Formula totBandwidth; 3904377Sgblack@eecs.umich.edu Stats::Formula totPackets; 3914377Sgblack@eecs.umich.edu Stats::Formula totBytes; 3924377Sgblack@eecs.umich.edu Stats::Formula totPacketRate; 3934572Sacolyte@umich.edu Stats::Formula txBandwidth; 3944572Sacolyte@umich.edu Stats::Formula rxBandwidth; 3954377Sgblack@eecs.umich.edu Stats::Formula txPacketRate; 3964377Sgblack@eecs.umich.edu Stats::Formula rxPacketRate; 3974377Sgblack@eecs.umich.edu Stats::Scalar<> postedSwi; 3984377Sgblack@eecs.umich.edu Stats::Formula coalescedSwi; 3994181Sgblack@eecs.umich.edu Stats::Scalar<> totalSwi; 4004181Sgblack@eecs.umich.edu Stats::Scalar<> postedRxIdle; 4014181Sgblack@eecs.umich.edu Stats::Formula coalescedRxIdle; 4024539Sgblack@eecs.umich.edu Stats::Scalar<> totalRxIdle; 4033276Sgblack@eecs.umich.edu Stats::Scalar<> postedRxOk; 4045665Sgblack@eecs.umich.edu Stats::Formula coalescedRxOk; 4053280Sgblack@eecs.umich.edu Stats::Scalar<> totalRxOk; 4063280Sgblack@eecs.umich.edu Stats::Scalar<> postedRxDesc; 4073276Sgblack@eecs.umich.edu Stats::Formula coalescedRxDesc; 4083276Sgblack@eecs.umich.edu Stats::Scalar<> totalRxDesc; 4093276Sgblack@eecs.umich.edu Stats::Scalar<> postedTxOk; 4105665Sgblack@eecs.umich.edu Stats::Formula coalescedTxOk; 4113276Sgblack@eecs.umich.edu Stats::Scalar<> totalTxOk; 4123276Sgblack@eecs.umich.edu Stats::Scalar<> postedTxIdle; 4134181Sgblack@eecs.umich.edu Stats::Formula coalescedTxIdle; 4144181Sgblack@eecs.umich.edu Stats::Scalar<> totalTxIdle; 4154181Sgblack@eecs.umich.edu Stats::Scalar<> postedTxDesc; 4164522Ssaidi@eecs.umich.edu Stats::Formula coalescedTxDesc; 4175784Sgblack@eecs.umich.edu Stats::Scalar<> totalTxDesc; 4185784Sgblack@eecs.umich.edu Stats::Scalar<> postedRxOrn; 4195784Sgblack@eecs.umich.edu Stats::Formula coalescedRxOrn; 4202470SN/A Stats::Scalar<> totalRxOrn; 4214181Sgblack@eecs.umich.edu Stats::Formula coalescedTotal; 4224181Sgblack@eecs.umich.edu Stats::Scalar<> postedInterrupts; 4234522Ssaidi@eecs.umich.edu Stats::Scalar<> droppedPackets; 4242623SN/A 4252623SN/A public: 4264181Sgblack@eecs.umich.edu Tick cacheAccess(MemReqPtr &req); 4272623SN/A}; 4284181Sgblack@eecs.umich.edu 4292623SN/A/* 4302623SN/A * Ethernet Interface for an Ethernet Device 4312623SN/A */ 4322623SN/Aclass NSGigEInt : public EtherInt 4332623SN/A{ 4342623SN/A private: 4355086Sgblack@eecs.umich.edu NSGigE *dev; 4363577Sgblack@eecs.umich.edu 4372683Sktlim@umich.edu public: 4385086Sgblack@eecs.umich.edu NSGigEInt(const std::string &name, NSGigE *d) 4392623SN/A : EtherInt(name), dev(d) { dev->setInterface(this); } 4402683Sktlim@umich.edu 4412623SN/A virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); } 4422420SN/A virtual void sendDone() { dev->transferDone(); } 4432SN/A}; 4442623SN/A 4452623SN/A#endif // __DEV_NS_GIGE_HH__ 4462SN/A