ns_gige.hh revision 11168
15651Sgblack@eecs.umich.edu/* 25651Sgblack@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 35651Sgblack@eecs.umich.edu * All rights reserved. 45651Sgblack@eecs.umich.edu * 55651Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65651Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75651Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85651Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95651Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105651Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115651Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125651Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135651Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145651Sgblack@eecs.umich.edu * this software without specific prior written permission. 155651Sgblack@eecs.umich.edu * 165651Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175651Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185651Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195651Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205651Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215651Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225651Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235651Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245651Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255651Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265651Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275651Sgblack@eecs.umich.edu * 285651Sgblack@eecs.umich.edu * Authors: Nathan Binkert 295651Sgblack@eecs.umich.edu * Lisa Hsu 305651Sgblack@eecs.umich.edu */ 315651Sgblack@eecs.umich.edu 325651Sgblack@eecs.umich.edu/** @file 335651Sgblack@eecs.umich.edu * Device module for modelling the National Semiconductor 345651Sgblack@eecs.umich.edu * DP83820 ethernet controller 355651Sgblack@eecs.umich.edu */ 365651Sgblack@eecs.umich.edu 376046Sgblack@eecs.umich.edu#ifndef __DEV_NS_GIGE_HH__ 385651Sgblack@eecs.umich.edu#define __DEV_NS_GIGE_HH__ 395651Sgblack@eecs.umich.edu 405651Sgblack@eecs.umich.edu#include "base/inet.hh" 415651Sgblack@eecs.umich.edu#include "dev/etherdevice.hh" 425651Sgblack@eecs.umich.edu#include "dev/etherint.hh" 435651Sgblack@eecs.umich.edu#include "dev/etherpkt.hh" 445651Sgblack@eecs.umich.edu#include "dev/io_device.hh" 455651Sgblack@eecs.umich.edu#include "dev/ns_gige_reg.h" 465651Sgblack@eecs.umich.edu#include "dev/pktfifo.hh" 475651Sgblack@eecs.umich.edu#include "params/NSGigE.hh" 485654Sgblack@eecs.umich.edu#include "sim/eventq.hh" 495654Sgblack@eecs.umich.edu 505651Sgblack@eecs.umich.edu// Hash filtering constants 515651Sgblack@eecs.umich.educonst uint16_t FHASH_ADDR = 0x100; 525654Sgblack@eecs.umich.educonst uint16_t FHASH_SIZE = 0x100; 535654Sgblack@eecs.umich.edu 545654Sgblack@eecs.umich.edu// EEPROM constants 555654Sgblack@eecs.umich.educonst uint8_t EEPROM_READ = 0x2; 565654Sgblack@eecs.umich.educonst uint8_t EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM 575654Sgblack@eecs.umich.educonst uint8_t EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2 585654Sgblack@eecs.umich.educonst uint8_t EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1 595654Sgblack@eecs.umich.educonst uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0 606050Sgblack@eecs.umich.edu 615654Sgblack@eecs.umich.edu/** 625654Sgblack@eecs.umich.edu * Ethernet device registers 635654Sgblack@eecs.umich.edu */ 645654Sgblack@eecs.umich.edustruct dp_regs { 655654Sgblack@eecs.umich.edu uint32_t command; 665654Sgblack@eecs.umich.edu uint32_t config; 676050Sgblack@eecs.umich.edu uint32_t mear; 685654Sgblack@eecs.umich.edu uint32_t ptscr; 695654Sgblack@eecs.umich.edu uint32_t isr; 705654Sgblack@eecs.umich.edu uint32_t imr; 715654Sgblack@eecs.umich.edu uint32_t ier; 725654Sgblack@eecs.umich.edu uint32_t ihr; 736050Sgblack@eecs.umich.edu uint32_t txdp; 745654Sgblack@eecs.umich.edu uint32_t txdp_hi; 755654Sgblack@eecs.umich.edu uint32_t txcfg; 765654Sgblack@eecs.umich.edu uint32_t gpior; 775651Sgblack@eecs.umich.edu uint32_t rxdp; 785651Sgblack@eecs.umich.edu uint32_t rxdp_hi; 795651Sgblack@eecs.umich.edu uint32_t rxcfg; 805651Sgblack@eecs.umich.edu uint32_t pqcr; 815651Sgblack@eecs.umich.edu uint32_t wcsr; 825651Sgblack@eecs.umich.edu uint32_t pcr; 835736Snate@binkert.org uint32_t rfcr; 845651Sgblack@eecs.umich.edu uint32_t rfdr; 855651Sgblack@eecs.umich.edu uint32_t brar; 865651Sgblack@eecs.umich.edu uint32_t brdr; 875651Sgblack@eecs.umich.edu uint32_t srr; 885651Sgblack@eecs.umich.edu uint32_t mibc; 895651Sgblack@eecs.umich.edu uint32_t vrcr; 905651Sgblack@eecs.umich.edu uint32_t vtcr; 915651Sgblack@eecs.umich.edu uint32_t vdr; 925651Sgblack@eecs.umich.edu uint32_t ccsr; 935651Sgblack@eecs.umich.edu uint32_t tbicr; 945651Sgblack@eecs.umich.edu uint32_t tbisr; 955651Sgblack@eecs.umich.edu uint32_t tanar; 965651Sgblack@eecs.umich.edu uint32_t tanlpar; 975651Sgblack@eecs.umich.edu uint32_t taner; 985651Sgblack@eecs.umich.edu uint32_t tesr; 995651Sgblack@eecs.umich.edu}; 1005651Sgblack@eecs.umich.edu 1015651Sgblack@eecs.umich.edustruct dp_rom { 1025651Sgblack@eecs.umich.edu /** 1035651Sgblack@eecs.umich.edu * for perfect match memory. 1045651Sgblack@eecs.umich.edu * the linux driver doesn't use any other ROM 1055651Sgblack@eecs.umich.edu */ 1065651Sgblack@eecs.umich.edu uint8_t perfectMatch[ETH_ADDR_LEN]; 1075651Sgblack@eecs.umich.edu 1085651Sgblack@eecs.umich.edu /** 1095651Sgblack@eecs.umich.edu * for hash table memory. 1105651Sgblack@eecs.umich.edu * used by the freebsd driver 1115651Sgblack@eecs.umich.edu */ 1125651Sgblack@eecs.umich.edu uint8_t filterHash[FHASH_SIZE]; 113}; 114 115class NSGigEInt; 116class Packet; 117 118/** 119 * NS DP83820 Ethernet device model 120 */ 121class NSGigE : public EtherDevBase 122{ 123 public: 124 /** Transmit State Machine states */ 125 enum TxState 126 { 127 txIdle, 128 txDescRefr, 129 txDescRead, 130 txFifoBlock, 131 txFragRead, 132 txDescWrite, 133 txAdvance 134 }; 135 136 /** Receive State Machine States */ 137 enum RxState 138 { 139 rxIdle, 140 rxDescRefr, 141 rxDescRead, 142 rxFifoBlock, 143 rxFragWrite, 144 rxDescWrite, 145 rxAdvance 146 }; 147 148 enum DmaState 149 { 150 dmaIdle, 151 dmaReading, 152 dmaWriting, 153 dmaReadWaiting, 154 dmaWriteWaiting 155 }; 156 157 /** EEPROM State Machine States */ 158 enum EEPROMState 159 { 160 eepromStart, 161 eepromGetOpcode, 162 eepromGetAddress, 163 eepromRead 164 }; 165 166 protected: 167 /** device register file */ 168 dp_regs regs; 169 dp_rom rom; 170 171 /** pci settings */ 172 bool ioEnable; 173#if 0 174 bool memEnable; 175 bool bmEnable; 176#endif 177 178 /*** BASIC STRUCTURES FOR TX/RX ***/ 179 /* Data FIFOs */ 180 PacketFifo txFifo; 181 PacketFifo rxFifo; 182 183 /** various helper vars */ 184 EthPacketPtr txPacket; 185 EthPacketPtr rxPacket; 186 uint8_t *txPacketBufPtr; 187 uint8_t *rxPacketBufPtr; 188 uint32_t txXferLen; 189 uint32_t rxXferLen; 190 bool rxDmaFree; 191 bool txDmaFree; 192 193 /** DescCaches */ 194 ns_desc32 txDesc32; 195 ns_desc32 rxDesc32; 196 ns_desc64 txDesc64; 197 ns_desc64 rxDesc64; 198 199 /* tx State Machine */ 200 TxState txState; 201 bool txEnable; 202 203 /** Current Transmit Descriptor Done */ 204 bool CTDD; 205 /** halt the tx state machine after next packet */ 206 bool txHalt; 207 /** ptr to the next byte in the current fragment */ 208 Addr txFragPtr; 209 /** count of bytes remaining in the current descriptor */ 210 uint32_t txDescCnt; 211 DmaState txDmaState; 212 213 /** rx State Machine */ 214 RxState rxState; 215 bool rxEnable; 216 217 /** Current Receive Descriptor Done */ 218 bool CRDD; 219 /** num of bytes in the current packet being drained from rxDataFifo */ 220 uint32_t rxPktBytes; 221 /** halt the rx state machine after current packet */ 222 bool rxHalt; 223 /** ptr to the next byte in current fragment */ 224 Addr rxFragPtr; 225 /** count of bytes remaining in the current descriptor */ 226 uint32_t rxDescCnt; 227 DmaState rxDmaState; 228 229 bool extstsEnable; 230 231 /** EEPROM State Machine */ 232 EEPROMState eepromState; 233 bool eepromClk; 234 uint8_t eepromBitsToRx; 235 uint8_t eepromOpcode; 236 uint8_t eepromAddress; 237 uint16_t eepromData; 238 239 protected: 240 Tick dmaReadDelay; 241 Tick dmaWriteDelay; 242 243 Tick dmaReadFactor; 244 Tick dmaWriteFactor; 245 246 void *rxDmaData; 247 Addr rxDmaAddr; 248 int rxDmaLen; 249 bool doRxDmaRead(); 250 bool doRxDmaWrite(); 251 252 void *txDmaData; 253 Addr txDmaAddr; 254 int txDmaLen; 255 bool doTxDmaRead(); 256 bool doTxDmaWrite(); 257 258 void rxDmaReadDone(); 259 friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>; 260 EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent; 261 262 void rxDmaWriteDone(); 263 friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>; 264 EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent; 265 266 void txDmaReadDone(); 267 friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>; 268 EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent; 269 270 void txDmaWriteDone(); 271 friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>; 272 EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent; 273 274 bool dmaDescFree; 275 bool dmaDataFree; 276 277 protected: 278 Tick txDelay; 279 Tick rxDelay; 280 281 void txReset(); 282 void rxReset(); 283 void regsReset(); 284 285 void rxKick(); 286 Tick rxKickTick; 287 typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent; 288 friend void RxKickEvent::process(); 289 RxKickEvent rxKickEvent; 290 291 void txKick(); 292 Tick txKickTick; 293 typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent; 294 friend void TxKickEvent::process(); 295 TxKickEvent txKickEvent; 296 297 void eepromKick(); 298 299 /** 300 * Retransmit event 301 */ 302 void transmit(); 303 void txEventTransmit() 304 { 305 transmit(); 306 if (txState == txFifoBlock) 307 txKick(); 308 } 309 typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent; 310 friend void TxEvent::process(); 311 TxEvent txEvent; 312 313 void txDump() const; 314 void rxDump() const; 315 316 /** 317 * receive address filter 318 */ 319 bool rxFilterEnable; 320 bool rxFilter(const EthPacketPtr &packet); 321 bool acceptBroadcast; 322 bool acceptMulticast; 323 bool acceptUnicast; 324 bool acceptPerfect; 325 bool acceptArp; 326 bool multicastHashEnable; 327 328 /** 329 * Interrupt management 330 */ 331 void devIntrPost(uint32_t interrupts); 332 void devIntrClear(uint32_t interrupts); 333 void devIntrChangeMask(); 334 335 Tick intrDelay; 336 Tick intrTick; 337 bool cpuPendingIntr; 338 void cpuIntrPost(Tick when); 339 void cpuInterrupt(); 340 void cpuIntrClear(); 341 342 typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent; 343 friend void IntrEvent::process(); 344 IntrEvent *intrEvent; 345 NSGigEInt *interface; 346 347 public: 348 typedef NSGigEParams Params; 349 const Params *params() const { 350 return dynamic_cast<const Params *>(_params); 351 } 352 353 NSGigE(Params *params); 354 ~NSGigE(); 355 356 virtual EtherInt *getEthPort(const std::string &if_name, int idx); 357 358 virtual Tick writeConfig(PacketPtr pkt); 359 360 virtual Tick read(PacketPtr pkt); 361 virtual Tick write(PacketPtr pkt); 362 363 bool cpuIntrPending() const; 364 void cpuIntrAck() { cpuIntrClear(); } 365 366 bool recvPacket(EthPacketPtr packet); 367 void transferDone(); 368 369 void serialize(CheckpointOut &cp) const override; 370 void unserialize(CheckpointIn &cp) override; 371 372 void drainResume() override; 373}; 374 375/* 376 * Ethernet Interface for an Ethernet Device 377 */ 378class NSGigEInt : public EtherInt 379{ 380 private: 381 NSGigE *dev; 382 383 public: 384 NSGigEInt(const std::string &name, NSGigE *d) 385 : EtherInt(name), dev(d) 386 { } 387 388 virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); } 389 virtual void sendDone() { dev->transferDone(); } 390}; 391 392#endif // __DEV_NS_GIGE_HH__ 393