i8254xGBe_defs.hh revision 3116 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/* @file
32 * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers.
33 */
34
35namespace iGbReg {
36
37const uint32_t CTRL     = 0x00000;
38const uint32_t STATUS   = 0x00008;
39const uint32_t EECD     = 0x00010;
40const uint32_t CTRL_EXT = 0x00018;
41const uint32_t PBA      = 0x01000;
42const uint32_t ICR      = 0x000C0;
43const uint32_t ITR      = 0x000C4;
44const uint32_t ICS      = 0x000C8;
45const uint32_t IMS      = 0x000D0;
46const uint32_t IMC      = 0x000D8;
47const uint32_t RCTL     = 0x00100;
48const uint32_t RDBAL    = 0x02800;
49const uint32_t RDBAH    = 0x02804;
50const uint32_t RDLEN    = 0x02808;
51const uint32_t RDH      = 0x02810;
52const uint32_t RDT      = 0x02818;
53const uint32_t RDTR     = 0x02820;
54const uint32_t RADV     = 0x0282C;
55const uint32_t RSRPD    = 0x02C00;
56const uint32_t TCTL     = 0x00400;
57const uint32_t TDBAL    = 0x03800;
58const uint32_t TDBAH    = 0x03804;
59const uint32_t TDLEN    = 0x03808;
60const uint32_t TDH      = 0x03810;
61const uint32_t THT      = 0x03818;
62const uint32_t TIDV     = 0x03820;
63const uint32_t TXDMAC   = 0x03000;
64const uint32_t TXDCTL   = 0x03828;
65const uint32_t TADV     = 0x0282C;
66const uint32_t TSPMT    = 0x03830;
67const uint32_t RXDCTL   = 0x02828;
68const uint32_t RXCSUM   = 0x05000;
69
70struct RxDesc {
71    Addr buf;
72    uint16_t len;
73    uint16_t csum;
74    union {
75        uint8_t status;
76        struct { // these may be in the worng order
77            uint8_t dd:1;    // descriptor done (hw is done when 1)
78            uint8_t eop:1;   // end of packet
79            uint8_t xism:1;  // ignore checksum
80            uint8_t vp:1;    // packet is vlan packet
81            uint8_t rsv:1;   // reserved
82            uint8_t tcpcs:1; // TCP checksum done
83            uint8_t ipcs:1;  // IP checksum done
84            uint8_t pif:1;   // passed in-exact filter
85        } st;
86    };
87    union {
88        uint8_t errors;
89        struct {
90            uint8_t ce:1;   // crc error or alignment error
91            uint8_t se:1;   // symbol error
92            uint8_t seq:1;  // sequence error
93            uint8_t rsv:1;  // reserved
94            uint8_t cxe:1;  // carrier extension error
95            uint8_t tcpe:1; // tcp checksum error
96            uint8_t ipe:1;  // ip checksum error
97            uint8_t rxe:1;  // PX data error
98        } er;
99    };
100    union {
101        uint16_t special;
102        struct {
103            uint16_t vlan:12; //vlan id
104            uint16_t cfi:1;   // canocial form id
105            uint16_t pri:3;   // user priority
106        } sp;
107    };
108};
109
110union TxDesc {
111    uint8_t data[16];
112    struct {
113        Addr buf;
114        uint16_t len;
115        uint8_t  cso;
116        union {
117            uint8_t command;
118            struct {
119                uint8_t eop:1;  // end of packet
120                uint8_t ifcs:1; // insert crc
121                uint8_t ic:1;   // insert checksum
122                uint8_t rs:1;   // report status
123                uint8_t rps:1;  // report packet sent
124                uint8_t dext:1; // extension
125                uint8_t vle:1;  // vlan enable
126                uint8_t ide:1;  // interrupt delay enable
127            } cmd;
128        };
129        union {
130            uint8_t status:4;
131            struct {
132                uint8_t dd:1; // descriptor done
133                uint8_t ec:1; // excess collisions
134                uint8_t lc:1; // late collision
135                uint8_t tu:1; // transmit underrun
136            } st;
137        };
138        uint8_t reserved:4;
139        uint8_t css;
140        union {
141            uint16_t special;
142            struct {
143                uint16_t vlan:12; //vlan id
144                uint16_t cfi:1;   // canocial form id
145                uint16_t pri:3;   // user priority
146            } sp;
147        };
148    } legacy;
149
150    // Type 0000 descriptor
151    struct {
152        uint8_t ipcss;
153        uint8_t ipcso;
154        uint16_t ipcse;
155        uint8_t tucss;
156        uint8_t tucso;
157        uint16_t tucse;
158        uint32_t paylen:20;
159        uint8_t dtype:4;
160        union {
161            uint8_t tucommand;
162            struct {
163                uint8_t tcp:1;  // tcp/udp
164                uint8_t ip:1;   // ip ipv4/ipv6
165                uint8_t tse:1;  // tcp segment enbale
166                uint8_t rs:1;   // report status
167                uint8_t rsv0:1; // reserved
168                uint8_t dext:1; // descriptor extension
169                uint8_t rsv1:1; // reserved
170                uint8_t ide:1;  // interrupt delay enable
171            } tucmd;
172        };
173        union {
174            uint8_t status:4;
175            struct {
176                uint8_t dd:1;
177                uint8_t rsvd:3;
178            } sta;
179        };
180        uint8_t reserved:4;
181        uint8_t hdrlen;
182        uint16_t mss;
183    } t0;
184
185    // Type 0001 descriptor
186    struct {
187        Addr buf;
188        uint32_t dtalen:20;
189        uint8_t dtype:4;
190        union {
191            uint8_t dcommand;
192            struct {
193                uint8_t eop:1;  // end of packet
194                uint8_t ifcs:1; // insert crc
195                uint8_t tse:1;  // segmentation enable
196                uint8_t rs:1;   // report status
197                uint8_t rps:1;  // report packet sent
198                uint8_t dext:1; // extension
199                uint8_t vle:1;  // vlan enable
200                uint8_t ide:1;  // interrupt delay enable
201            } dcmd;
202        };
203        union {
204            uint8_t status:4;
205            struct {
206                uint8_t dd:1; // descriptor done
207                uint8_t ec:1; // excess collisions
208                uint8_t lc:1; // late collision
209                uint8_t tu:1; // transmit underrun
210            } sta;
211        };
212        union {
213            uint8_t pktopts;
214            struct {
215                uint8_t ixsm:1; // insert ip checksum
216                uint8_t txsm:1; // insert tcp checksum
217            };
218        };
219        union {
220            uint16_t special;
221            struct {
222                uint16_t vlan:12; //vlan id
223                uint16_t cfi:1;   // canocial form id
224                uint16_t pri:3;   // user priority
225            } sp;
226        };
227    } t1;
228
229    // Junk to test descriptor type!
230    struct {
231        uint64_t junk;
232        uint32_t junk1:20;
233        uint8_t dtype;
234        uint8_t junk2:5;
235        uint8_t dext:1;
236        uint8_t junk3:2;
237        uint8_t junk4:4;
238        uint32_t junk5;
239    } type;
240};
241
242}; // iGbReg namespace
243