i8254xGBe_defs.hh revision 7811
12292SN/A/* 22727Sktlim@umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Ali Saidi 292292SN/A */ 302292SN/A 312329SN/A/* @file 322980Sgblack@eecs.umich.edu * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers. 332329SN/A */ 342329SN/A#include "base/bitfield.hh" 352292SN/A 362292SN/Anamespace iGbReg { 374192Sktlim@umich.edu 384192Sktlim@umich.edu 394192Sktlim@umich.edu// Registers used by the Intel GbE NIC 404192Sktlim@umich.educonst uint32_t REG_CTRL = 0x00000; 414192Sktlim@umich.educonst uint32_t REG_STATUS = 0x00008; 424192Sktlim@umich.educonst uint32_t REG_EECD = 0x00010; 434192Sktlim@umich.educonst uint32_t REG_EERD = 0x00014; 444192Sktlim@umich.educonst uint32_t REG_CTRL_EXT = 0x00018; 454192Sktlim@umich.educonst uint32_t REG_MDIC = 0x00020; 464192Sktlim@umich.educonst uint32_t REG_FCAL = 0x00028; 474192Sktlim@umich.educonst uint32_t REG_FCAH = 0x0002C; 484192Sktlim@umich.educonst uint32_t REG_FCT = 0x00030; 494192Sktlim@umich.educonst uint32_t REG_VET = 0x00038; 502292SN/Aconst uint32_t REG_PBA = 0x01000; 512907Sktlim@umich.educonst uint32_t REG_ICR = 0x000C0; 522907Sktlim@umich.educonst uint32_t REG_ITR = 0x000C4; 532907Sktlim@umich.educonst uint32_t REG_ICS = 0x000C8; 542907Sktlim@umich.educonst uint32_t REG_IMS = 0x000D0; 552907Sktlim@umich.educonst uint32_t REG_IMC = 0x000D8; 562907Sktlim@umich.educonst uint32_t REG_IAM = 0x000E0; 572907Sktlim@umich.educonst uint32_t REG_RCTL = 0x00100; 582907Sktlim@umich.educonst uint32_t REG_FCTTV = 0x00170; 592907Sktlim@umich.educonst uint32_t REG_TIPG = 0x00410; 602907Sktlim@umich.educonst uint32_t REG_AIFS = 0x00458; 612907Sktlim@umich.educonst uint32_t REG_LEDCTL = 0x00e00; 623639Sktlim@umich.educonst uint32_t REG_EICR = 0x01580; 632907Sktlim@umich.educonst uint32_t REG_IVAR0 = 0x01700; 642907Sktlim@umich.educonst uint32_t REG_FCRTL = 0x02160; 652907Sktlim@umich.educonst uint32_t REG_FCRTH = 0x02168; 662907Sktlim@umich.educonst uint32_t REG_RDBAL = 0x02800; 672907Sktlim@umich.educonst uint32_t REG_RDBAH = 0x02804; 682907Sktlim@umich.educonst uint32_t REG_RDLEN = 0x02808; 693647Srdreslin@umich.educonst uint32_t REG_SRRCTL = 0x0280C; 703647Srdreslin@umich.educonst uint32_t REG_RDH = 0x02810; 713647Srdreslin@umich.educonst uint32_t REG_RDT = 0x02818; 723647Srdreslin@umich.educonst uint32_t REG_RDTR = 0x02820; 733647Srdreslin@umich.educonst uint32_t REG_RXDCTL = 0x02828; 742907Sktlim@umich.educonst uint32_t REG_RADV = 0x0282C; 753647Srdreslin@umich.educonst uint32_t REG_TCTL = 0x00400; 762907Sktlim@umich.educonst uint32_t REG_TDBAL = 0x03800; 772907Sktlim@umich.educonst uint32_t REG_TDBAH = 0x03804; 782907Sktlim@umich.educonst uint32_t REG_TDLEN = 0x03808; 792907Sktlim@umich.educonst uint32_t REG_TDH = 0x03810; 802907Sktlim@umich.educonst uint32_t REG_TXDCA_CTL = 0x03814; 812907Sktlim@umich.educonst uint32_t REG_TDT = 0x03818; 822907Sktlim@umich.educonst uint32_t REG_TIDV = 0x03820; 833310Srdreslin@umich.educonst uint32_t REG_TXDCTL = 0x03828; 843310Srdreslin@umich.educonst uint32_t REG_TADV = 0x0382C; 853310Srdreslin@umich.educonst uint32_t REG_TDWBAL = 0x03838; 863310Srdreslin@umich.educonst uint32_t REG_TDWBAH = 0x0383C; 873310Srdreslin@umich.educonst uint32_t REG_CRCERRS = 0x04000; 883339Srdreslin@umich.educonst uint32_t REG_RXCSUM = 0x05000; 893310Srdreslin@umich.educonst uint32_t REG_RLPML = 0x05004; 903310Srdreslin@umich.educonst uint32_t REG_RFCTL = 0x05008; 912907Sktlim@umich.educonst uint32_t REG_MTA = 0x05200; 922907Sktlim@umich.educonst uint32_t REG_RAL = 0x05400; 932907Sktlim@umich.educonst uint32_t REG_RAH = 0x05404; 942907Sktlim@umich.educonst uint32_t REG_VFTA = 0x05600; 952907Sktlim@umich.edu 962907Sktlim@umich.educonst uint32_t REG_WUC = 0x05800; 972907Sktlim@umich.educonst uint32_t REG_MANC = 0x05820; 983014Srdreslin@umich.educonst uint32_t REG_SWSM = 0x05B50; 993014Srdreslin@umich.educonst uint32_t REG_FWSM = 0x05B54; 1003014Srdreslin@umich.educonst uint32_t REG_SWFWSYNC = 0x05B5C; 1013014Srdreslin@umich.edu 1023014Srdreslin@umich.educonst uint8_t EEPROM_READ_OPCODE_SPI = 0x03; 1032907Sktlim@umich.educonst uint8_t EEPROM_RDSR_OPCODE_SPI = 0x05; 1042907Sktlim@umich.educonst uint8_t EEPROM_SIZE = 64; 1052907Sktlim@umich.educonst uint16_t EEPROM_CSUM = 0xBABA; 1062907Sktlim@umich.edu 1072907Sktlim@umich.educonst uint8_t VLAN_FILTER_TABLE_SIZE = 128; 1082907Sktlim@umich.educonst uint8_t RCV_ADDRESS_TABLE_SIZE = 24; 1092907Sktlim@umich.educonst uint8_t MULTICAST_TABLE_SIZE = 128; 1104329Sktlim@umich.educonst uint32_t STATS_REGS_SIZE = 0x228; 1114329Sktlim@umich.edu 1124329Sktlim@umich.edu 1134329Sktlim@umich.edu// Registers in that are accessed in the PHY 1144329Sktlim@umich.educonst uint8_t PHY_PSTATUS = 0x1; 1152907Sktlim@umich.educonst uint8_t PHY_PID = 0x2; 1162292SN/Aconst uint8_t PHY_EPID = 0x3; 1173647Srdreslin@umich.educonst uint8_t PHY_GSTATUS = 10; 1183647Srdreslin@umich.educonst uint8_t PHY_EPSTATUS = 15; 1192292SN/Aconst uint8_t PHY_AGC = 18; 1202292SN/A 1212292SN/A// Receive Descriptor Status Flags 1222980Sgblack@eecs.umich.educonst uint16_t RXDS_DYNINT = 0x800; 1232292SN/Aconst uint16_t RXDS_UDPV = 0x400; 1242292SN/Aconst uint16_t RXDS_CRCV = 0x100; 1252292SN/Aconst uint16_t RXDS_PIF = 0x080; 1262292SN/Aconst uint16_t RXDS_IPCS = 0x040; 1272292SN/Aconst uint16_t RXDS_TCPCS = 0x020; 1282292SN/Aconst uint16_t RXDS_UDPCS = 0x010; 1292292SN/Aconst uint16_t RXDS_VP = 0x008; 1302292SN/Aconst uint16_t RXDS_IXSM = 0x004; 1312292SN/Aconst uint16_t RXDS_EOP = 0x002; 1322292SN/Aconst uint16_t RXDS_DD = 0x001; 1332292SN/A 1344329Sktlim@umich.edu// Receive Descriptor Error Flags 1352292SN/Aconst uint8_t RXDE_RXE = 0x80; 1362292SN/Aconst uint8_t RXDE_IPE = 0x40; 1372292SN/Aconst uint8_t RXDE_TCPE = 0x20; 1382292SN/Aconst uint8_t RXDE_SEQ = 0x04; 1392292SN/Aconst uint8_t RXDE_SE = 0x02; 1402292SN/Aconst uint8_t RXDE_CE = 0x01; 1412292SN/A 1424329Sktlim@umich.edu// Receive Descriptor Extended Error Flags 1432292SN/Aconst uint16_t RXDEE_HBO = 0x008; 1442292SN/Aconst uint16_t RXDEE_CE = 0x010; 1452292SN/Aconst uint16_t RXDEE_LE = 0x020; 1462292SN/Aconst uint16_t RXDEE_PE = 0x080; 1472292SN/Aconst uint16_t RXDEE_OSE = 0x100; 1482292SN/Aconst uint16_t RXDEE_USE = 0x200; 1492292SN/Aconst uint16_t RXDEE_TCPE = 0x400; 1502292SN/Aconst uint16_t RXDEE_IPE = 0x800; 1512292SN/A 1522292SN/A 1532292SN/A// Receive Descriptor Types 1542292SN/Aconst uint8_t RXDT_LEGACY = 0x00; 1552292SN/Aconst uint8_t RXDT_ADV_ONEBUF = 0x01; 1562292SN/Aconst uint8_t RXDT_ADV_SPLIT_A = 0x05; 1574329Sktlim@umich.edu 1582292SN/A// Receive Descriptor Packet Types 1592292SN/Aconst uint16_t RXDP_IPV4 = 0x001; 1602292SN/Aconst uint16_t RXDP_IPV4E = 0x002; 1612292SN/Aconst uint16_t RXDP_IPV6 = 0x004; 1622292SN/Aconst uint16_t RXDP_IPV6E = 0x008; 1632292SN/Aconst uint16_t RXDP_TCP = 0x010; 1642292SN/Aconst uint16_t RXDP_UDP = 0x020; 1652292SN/Aconst uint16_t RXDP_SCTP = 0x040; 1662292SN/Aconst uint16_t RXDP_NFS = 0x080; 1672292SN/A 1684329Sktlim@umich.edu// Interrupt types 1694329Sktlim@umich.eduenum IntTypes 1702907Sktlim@umich.edu{ 1712292SN/A IT_NONE = 0x00000, //dummy value 1722292SN/A IT_TXDW = 0x00001, 1732292SN/A IT_TXQE = 0x00002, 1742292SN/A IT_LSC = 0x00004, 1752292SN/A IT_RXSEQ = 0x00008, 1762292SN/A IT_RXDMT = 0x00010, 1772292SN/A IT_RXO = 0x00040, 1782292SN/A IT_RXT = 0x00080, 1792292SN/A IT_MADC = 0x00200, 1802292SN/A IT_RXCFG = 0x00400, 1812292SN/A IT_GPI0 = 0x02000, 1822292SN/A IT_GPI1 = 0x04000, 1832292SN/A IT_TXDLOW = 0x08000, 1842727Sktlim@umich.edu IT_SRPD = 0x10000, 1852727Sktlim@umich.edu IT_ACK = 0x20000 1862727Sktlim@umich.edu}; 1872727Sktlim@umich.edu 1882727Sktlim@umich.edu// Receive Descriptor struct 1892727Sktlim@umich.edustruct RxDesc { 1902727Sktlim@umich.edu union { 1912727Sktlim@umich.edu struct { 1922727Sktlim@umich.edu Addr buf; 1932727Sktlim@umich.edu uint16_t len; 1942980Sgblack@eecs.umich.edu uint16_t csum; 1952292SN/A uint8_t status; 1962292SN/A uint8_t errors; 1972292SN/A uint16_t vlan; 1982292SN/A } legacy; 1992292SN/A struct { 2002292SN/A Addr pkt; 2012307SN/A Addr hdr; 2022307SN/A } adv_read; 2032307SN/A struct { 2042307SN/A uint16_t rss_type:4; 2052307SN/A uint16_t pkt_type:12; 2062307SN/A uint16_t __reserved1:5; 2072307SN/A uint16_t header_len:10; 2082307SN/A uint16_t sph:1; 2092307SN/A union { 2102307SN/A struct { 2112307SN/A uint16_t id; 2122307SN/A uint16_t csum; 2132307SN/A }; 2142307SN/A uint32_t rss_hash; 2152307SN/A }; 2162307SN/A uint32_t status:20; 2172307SN/A uint32_t errors:12; 2182307SN/A uint16_t pkt_len; 2192292SN/A uint16_t vlan_tag; 2202292SN/A } adv_wb ; 2212292SN/A }; 2222292SN/A}; 2232292SN/A 2242292SN/Astruct TxDesc { 2252292SN/A uint64_t d1; 2262292SN/A uint64_t d2; 2272292SN/A}; 2282292SN/A 2292292SN/Anamespace TxdOp { 2302292SN/Aconst uint8_t TXD_CNXT = 0x0; 2312292SN/Aconst uint8_t TXD_DATA = 0x1; 2322292SN/Aconst uint8_t TXD_ADVCNXT = 0x2; 2332292SN/Aconst uint8_t TXD_ADVDATA = 0x3; 2343867Sbinkertn@umich.edu 2352292SN/Abool isLegacy(TxDesc *d) { return !bits(d->d2,29,29); } 2362292SN/Auint8_t getType(TxDesc *d) { return bits(d->d2, 23,20); } 2372292SN/Abool isType(TxDesc *d, uint8_t type) { return getType(d) == type; } 2382292SN/Abool isTypes(TxDesc *d, uint8_t t1, uint8_t t2) { return isType(d, t1) || isType(d, t2); } 2392292SN/Abool isAdvDesc(TxDesc *d) { return !isLegacy(d) && isTypes(d, TXD_ADVDATA,TXD_ADVCNXT); } 2402292SN/Abool isContext(TxDesc *d) { return !isLegacy(d) && isTypes(d,TXD_CNXT, TXD_ADVCNXT); } 2412292SN/Abool isData(TxDesc *d) { return !isLegacy(d) && isTypes(d, TXD_DATA, TXD_ADVDATA); } 2422292SN/A 2432292SN/AAddr getBuf(TxDesc *d) { assert(isLegacy(d) || isData(d)); return d->d1; } 2442292SN/AAddr getLen(TxDesc *d) { if (isLegacy(d)) return bits(d->d2,15,0); else return bits(d->d2, 19,0); } 2452292SN/Avoid setDd(TxDesc *d) { replaceBits(d->d2, 35, 32, ULL(1)); } 2463867Sbinkertn@umich.edu 2473867Sbinkertn@umich.edubool ide(TxDesc *d) { return bits(d->d2, 31,31) && (getType(d) == TXD_DATA || isLegacy(d)); } 2483867Sbinkertn@umich.edubool vle(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 30,30); } 2493867Sbinkertn@umich.edubool rs(TxDesc *d) { return bits(d->d2, 27,27); } 2503867Sbinkertn@umich.edubool ic(TxDesc *d) { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); } 2513867Sbinkertn@umich.edubool tse(TxDesc *d) { 2523867Sbinkertn@umich.edu if (isTypes(d, TXD_CNXT, TXD_DATA)) 2532292SN/A return bits(d->d2, 26,26); 2542292SN/A if (isType(d, TXD_ADVDATA)) 2552292SN/A return bits(d->d2, 31, 31); 2562292SN/A return false; 2572292SN/A} 2582292SN/A 2592292SN/Abool ifcs(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 25,25); } 2602292SN/Abool eop(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 24,24); } 2612292SN/Abool ip(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 25,25); } 2622292SN/Abool tcp(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 24,24); } 2632292SN/A 2642292SN/Auint8_t getCso(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 23,16); } 2652292SN/Auint8_t getCss(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 47,40); } 2662292SN/A 2672292SN/Abool ixsm(TxDesc *d) { return isData(d) && bits(d->d2, 40,40); } 2682292SN/Abool txsm(TxDesc *d) { return isData(d) && bits(d->d2, 41,41); } 2692292SN/A 2702292SN/Aint tucse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,63,48); } 2712292SN/Aint tucso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,47,40); } 2722292SN/Aint tucss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,39,32); } 2732292SN/Aint ipcse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,31,16); } 2742292SN/Aint ipcso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,15,8); } 2752292SN/Aint ipcss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,7,0); } 2762292SN/Aint mss(TxDesc *d) { assert(isContext(d)); return bits(d->d2,63,48); } 2773867Sbinkertn@umich.eduint hdrlen(TxDesc *d) { 2783867Sbinkertn@umich.edu assert(isContext(d)); 2792292SN/A if (!isAdvDesc(d)) 2803867Sbinkertn@umich.edu return bits(d->d2,47,40); 2813867Sbinkertn@umich.edu return bits(d->d2, 47,40) + bits(d->d1, 8,0) + bits(d->d1, 15, 9); 2822292SN/A} 2832292SN/A 2842292SN/Aint getTsoLen(TxDesc *d) { assert(isType(d, TXD_ADVDATA)); return bits(d->d2, 63,46); } 2852292SN/Aint utcmd(TxDesc *d) { assert(isContext(d)); return bits(d->d2,24,31); } 2862292SN/A} // namespace TxdOp 2872292SN/A 2882292SN/A 2892292SN/A#define ADD_FIELD32(NAME, OFFSET, BITS) \ 2902292SN/A inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 2912292SN/A inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 2922292SN/A 2932292SN/A#define ADD_FIELD64(NAME, OFFSET, BITS) \ 2942292SN/A inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 2952292SN/A inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 2962292SN/A 2972292SN/Astruct Regs { 2982292SN/A template<class T> 2992292SN/A struct Reg { 3002292SN/A T _data; 3012292SN/A T operator()() { return _data; } 3022292SN/A const Reg<T> &operator=(T d) { _data = d; return *this;} 3032292SN/A bool operator==(T d) { return d == _data; } 3042292SN/A void operator()(T d) { _data = d; } 3052292SN/A Reg() { _data = 0; } 3062292SN/A void serialize(std::ostream &os) 3072292SN/A { 3082292SN/A SERIALIZE_SCALAR(_data); 3092292SN/A } 3102292SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3112292SN/A { 3122292SN/A UNSERIALIZE_SCALAR(_data); 3132292SN/A } 3142292SN/A }; 3152292SN/A 3162292SN/A struct CTRL : public Reg<uint32_t> { // 0x0000 CTRL Register 3172292SN/A using Reg<uint32_t>::operator=; 3182292SN/A ADD_FIELD32(fd,0,1); // full duplex 3192292SN/A ADD_FIELD32(bem,1,1); // big endian mode 3202292SN/A ADD_FIELD32(pcipr,2,1); // PCI priority 3212292SN/A ADD_FIELD32(lrst,3,1); // link reset 3222292SN/A ADD_FIELD32(tme,4,1); // test mode enable 3232292SN/A ADD_FIELD32(asde,5,1); // Auto-speed detection 3242292SN/A ADD_FIELD32(slu,6,1); // Set link up 3252292SN/A ADD_FIELD32(ilos,7,1); // invert los-of-signal 3262292SN/A ADD_FIELD32(speed,8,2); // speed selection bits 3273867Sbinkertn@umich.edu ADD_FIELD32(be32,10,1); // big endian mode 32 3283867Sbinkertn@umich.edu ADD_FIELD32(frcspd,11,1); // force speed 3292292SN/A ADD_FIELD32(frcdpx,12,1); // force duplex 3303867Sbinkertn@umich.edu ADD_FIELD32(duden,13,1); // dock/undock enable 3313867Sbinkertn@umich.edu ADD_FIELD32(dudpol,14,1); // dock/undock polarity 3322292SN/A ADD_FIELD32(fphyrst,15,1); // force phy reset 3332292SN/A ADD_FIELD32(extlen,16,1); // external link status enable 3342329SN/A ADD_FIELD32(rsvd,17,1); // reserved 3352329SN/A ADD_FIELD32(sdp0d,18,1); // software controlled pin data 3362292SN/A ADD_FIELD32(sdp1d,19,1); // software controlled pin data 3372292SN/A ADD_FIELD32(sdp2d,20,1); // software controlled pin data 3382292SN/A ADD_FIELD32(sdp3d,21,1); // software controlled pin data 3392292SN/A ADD_FIELD32(sdp0i,22,1); // software controlled pin dir 3402292SN/A ADD_FIELD32(sdp1i,23,1); // software controlled pin dir 3412292SN/A ADD_FIELD32(sdp2i,24,1); // software controlled pin dir 3422292SN/A ADD_FIELD32(sdp3i,25,1); // software controlled pin dir 3432292SN/A ADD_FIELD32(rst,26,1); // reset 3442292SN/A ADD_FIELD32(rfce,27,1); // receive flow control enable 3452292SN/A ADD_FIELD32(tfce,28,1); // transmit flow control enable 3462292SN/A ADD_FIELD32(rte,29,1); // routing tag enable 3473867Sbinkertn@umich.edu ADD_FIELD32(vme,30,1); // vlan enable 3483867Sbinkertn@umich.edu ADD_FIELD32(phyrst,31,1); // phy reset 3492292SN/A }; 3503867Sbinkertn@umich.edu CTRL ctrl; 3513867Sbinkertn@umich.edu 3523867Sbinkertn@umich.edu struct STATUS : public Reg<uint32_t> { // 0x0008 STATUS Register 3532292SN/A using Reg<uint32_t>::operator=; 3542292SN/A ADD_FIELD32(fd,0,1); // full duplex 3552292SN/A ADD_FIELD32(lu,1,1); // link up 3562292SN/A ADD_FIELD32(func,2,2); // function id 3572292SN/A ADD_FIELD32(txoff,4,1); // transmission paused 3582292SN/A ADD_FIELD32(tbimode,5,1); // tbi mode 3592292SN/A ADD_FIELD32(speed,6,2); // link speed 3602292SN/A ADD_FIELD32(asdv,8,2); // auto speed detection value 3612292SN/A ADD_FIELD32(mtxckok,10,1); // mtx clock running ok 3622292SN/A ADD_FIELD32(pci66,11,1); // In 66Mhz pci slot 3632292SN/A ADD_FIELD32(bus64,12,1); // in 64 bit slot 3642292SN/A ADD_FIELD32(pcix,13,1); // Pci mode 3652292SN/A ADD_FIELD32(pcixspd,14,2); // pci x speed 3663867Sbinkertn@umich.edu }; 3673867Sbinkertn@umich.edu STATUS sts; 3682292SN/A 3693867Sbinkertn@umich.edu struct EECD : public Reg<uint32_t> { // 0x0010 EECD Register 3703867Sbinkertn@umich.edu using Reg<uint32_t>::operator=; 3713867Sbinkertn@umich.edu ADD_FIELD32(sk,0,1); // clack input to the eeprom 3722292SN/A ADD_FIELD32(cs,1,1); // chip select to eeprom 3732292SN/A ADD_FIELD32(din,2,1); // data input to eeprom 3742292SN/A ADD_FIELD32(dout,3,1); // data output bit 3752292SN/A ADD_FIELD32(fwe,4,2); // flash write enable 3762292SN/A ADD_FIELD32(ee_req,6,1); // request eeprom access 3772292SN/A ADD_FIELD32(ee_gnt,7,1); // grant eeprom access 3782292SN/A ADD_FIELD32(ee_pres,8,1); // eeprom present 3792292SN/A ADD_FIELD32(ee_size,9,1); // eeprom size 3802292SN/A ADD_FIELD32(ee_sz1,10,1); // eeprom size 3812292SN/A ADD_FIELD32(rsvd,11,2); // reserved 3822292SN/A ADD_FIELD32(ee_type,13,1); // type of eeprom 3832292SN/A } ; 3843867Sbinkertn@umich.edu EECD eecd; 3853867Sbinkertn@umich.edu 3862292SN/A struct EERD : public Reg<uint32_t> { // 0x0014 EERD Register 3873867Sbinkertn@umich.edu using Reg<uint32_t>::operator=; 3883867Sbinkertn@umich.edu ADD_FIELD32(start,0,1); // start read 3893867Sbinkertn@umich.edu ADD_FIELD32(done,1,1); // done read 3902292SN/A ADD_FIELD32(addr,2,14); // address 3912292SN/A ADD_FIELD32(data,16,16); // data 3922292SN/A }; 3932292SN/A EERD eerd; 3942292SN/A 3952292SN/A struct CTRL_EXT : public Reg<uint32_t> { // 0x0018 CTRL_EXT Register 3962292SN/A using Reg<uint32_t>::operator=; 3972292SN/A ADD_FIELD32(gpi_en,0,4); // enable interrupts from gpio 3982292SN/A ADD_FIELD32(phyint,5,1); // reads the phy internal int status 3992292SN/A ADD_FIELD32(sdp2_data,6,1); // data from gpio sdp 4002292SN/A ADD_FIELD32(spd3_data,7,1); // data frmo gpio sdp 4012292SN/A ADD_FIELD32(spd2_iodir,10,1); // direction of sdp2 4023867Sbinkertn@umich.edu ADD_FIELD32(spd3_iodir,11,1); // direction of sdp2 4033867Sbinkertn@umich.edu ADD_FIELD32(asdchk,12,1); // initiate auto-speed-detection 4042292SN/A ADD_FIELD32(eerst,13,1); // reset the eeprom 4053867Sbinkertn@umich.edu ADD_FIELD32(spd_byps,15,1); // bypass speed select 4063867Sbinkertn@umich.edu ADD_FIELD32(ro_dis,17,1); // disable relaxed memory ordering 4073867Sbinkertn@umich.edu ADD_FIELD32(vreg,21,1); // power down the voltage regulator 4082292SN/A ADD_FIELD32(link_mode,22,2); // interface to talk to the link 4092292SN/A ADD_FIELD32(iame, 27,1); // interrupt acknowledge auto-mask ?? 4102292SN/A ADD_FIELD32(drv_loaded, 28,1);// driver is loaded and incharge of device 4112292SN/A ADD_FIELD32(timer_clr, 29,1); // clear interrupt timers after IMS clear ?? 4122292SN/A }; 4132292SN/A CTRL_EXT ctrl_ext; 4142292SN/A 4152292SN/A struct MDIC : public Reg<uint32_t> { // 0x0020 MDIC Register 4162292SN/A using Reg<uint32_t>::operator=; 4172292SN/A ADD_FIELD32(data,0,16); // data 4182292SN/A ADD_FIELD32(regadd,16,5); // register address 4192292SN/A ADD_FIELD32(phyadd,21,5); // phy addresses 4203867Sbinkertn@umich.edu ADD_FIELD32(op,26,2); // opcode 4213867Sbinkertn@umich.edu ADD_FIELD32(r,28,1); // ready 4222292SN/A ADD_FIELD32(i,29,1); // interrupt 4233867Sbinkertn@umich.edu ADD_FIELD32(e,30,1); // error 4243867Sbinkertn@umich.edu }; 4253867Sbinkertn@umich.edu MDIC mdic; 4262292SN/A 4272292SN/A struct ICR : public Reg<uint32_t> { // 0x00C0 ICR Register 4282292SN/A using Reg<uint32_t>::operator=; 4292292SN/A ADD_FIELD32(txdw,0,1) // tx descr witten back 4302292SN/A ADD_FIELD32(txqe,1,1) // tx queue empty 4312292SN/A ADD_FIELD32(lsc,2,1) // link status change 4322292SN/A ADD_FIELD32(rxseq,3,1) // rcv sequence error 4332292SN/A ADD_FIELD32(rxdmt0,4,1) // rcv descriptor min thresh 4342292SN/A ADD_FIELD32(rsvd1,5,1) // reserved 4352292SN/A ADD_FIELD32(rxo,6,1) // receive overrunn 4362292SN/A ADD_FIELD32(rxt0,7,1) // receiver timer interrupt 4372292SN/A ADD_FIELD32(mdac,9,1) // mdi/o access complete 4383867Sbinkertn@umich.edu ADD_FIELD32(rxcfg,10,1) // recv /c/ ordered sets 4393867Sbinkertn@umich.edu ADD_FIELD32(phyint,12,1) // phy interrupt 4402292SN/A ADD_FIELD32(gpi1,13,1) // gpi int 1 4413867Sbinkertn@umich.edu ADD_FIELD32(gpi2,14,1) // gpi int 2 4423867Sbinkertn@umich.edu ADD_FIELD32(txdlow,15,1) // transmit desc low thresh 4433867Sbinkertn@umich.edu ADD_FIELD32(srpd,16,1) // small receive packet detected 4442292SN/A ADD_FIELD32(ack,17,1); // receive ack frame 4452292SN/A ADD_FIELD32(int_assert, 31,1); // interrupt caused a system interrupt 4462292SN/A }; 4472292SN/A ICR icr; 4482292SN/A 4492292SN/A uint32_t imr; // register that contains the current interrupt mask 4502292SN/A 4512292SN/A struct ITR : public Reg<uint32_t> { // 0x00C4 ITR Register 4522292SN/A using Reg<uint32_t>::operator=; 4532292SN/A ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval 4543870Sbinkertn@umich.edu // specified in 256ns interrupts 4552292SN/A }; 4562292SN/A ITR itr; 4572292SN/A 4582292SN/A // When CTRL_EXT.IAME and the ICR.INT_ASSERT is 1 an ICR read or write 4592292SN/A // causes the IAM register contents to be written into the IMC 4602292SN/A // automatically clearing all interrupts that have a bit in the IAM set 4612292SN/A uint32_t iam; 4622292SN/A 4632292SN/A struct RCTL : public Reg<uint32_t> { // 0x0100 RCTL Register 4643867Sbinkertn@umich.edu using Reg<uint32_t>::operator=; 4653867Sbinkertn@umich.edu ADD_FIELD32(rst,0,1); // Reset 4662292SN/A ADD_FIELD32(en,1,1); // Enable 4673867Sbinkertn@umich.edu ADD_FIELD32(sbp,2,1); // Store bad packets 4683867Sbinkertn@umich.edu ADD_FIELD32(upe,3,1); // Unicast Promiscuous enabled 4693867Sbinkertn@umich.edu ADD_FIELD32(mpe,4,1); // Multicast promiscuous enabled 4703867Sbinkertn@umich.edu ADD_FIELD32(lpe,5,1); // long packet reception enabled 4712292SN/A ADD_FIELD32(lbm,6,2); // 4722292SN/A ADD_FIELD32(rdmts,8,2); // 4732292SN/A ADD_FIELD32(mo,12,2); // 4742292SN/A ADD_FIELD32(mdr,14,1); // 4752292SN/A ADD_FIELD32(bam,15,1); // 4762292SN/A ADD_FIELD32(bsize,16,2); // 4772292SN/A ADD_FIELD32(vfe,18,1); // 4782292SN/A ADD_FIELD32(cfien,19,1); // 4792292SN/A ADD_FIELD32(cfi,20,1); // 4802292SN/A ADD_FIELD32(dpf,22,1); // discard pause frames 4812292SN/A ADD_FIELD32(pmcf,23,1); // pass mac control frames 4822292SN/A ADD_FIELD32(bsex,25,1); // buffer size extension 4833867Sbinkertn@umich.edu ADD_FIELD32(secrc,26,1); // strip ethernet crc from incoming packet 4842292SN/A unsigned descSize() 4852292SN/A { 4862292SN/A switch(bsize()) { 4872292SN/A case 0: return bsex() == 0 ? 2048 : 0; 4882292SN/A case 1: return bsex() == 0 ? 1024 : 16384; 4892292SN/A case 2: return bsex() == 0 ? 512 : 8192; 4902292SN/A case 3: return bsex() == 0 ? 256 : 4096; 4912292SN/A default: 4922292SN/A return 0; 4933867Sbinkertn@umich.edu } 4943867Sbinkertn@umich.edu } 4952292SN/A }; 4963867Sbinkertn@umich.edu RCTL rctl; 4973867Sbinkertn@umich.edu 4983867Sbinkertn@umich.edu struct FCTTV : public Reg<uint32_t> { // 0x0170 FCTTV 4992292SN/A using Reg<uint32_t>::operator=; 5002292SN/A ADD_FIELD32(ttv,0,16); // Transmit Timer Value 5012292SN/A }; 5022292SN/A FCTTV fcttv; 5032292SN/A 5042292SN/A struct TCTL : public Reg<uint32_t> { // 0x0400 TCTL Register 5052292SN/A using Reg<uint32_t>::operator=; 5062292SN/A ADD_FIELD32(rst,0,1); // Reset 5072292SN/A ADD_FIELD32(en,1,1); // Enable 5082292SN/A ADD_FIELD32(bce,2,1); // busy check enable 5092292SN/A ADD_FIELD32(psp,3,1); // pad short packets 5102292SN/A ADD_FIELD32(ct,4,8); // collision threshold 5112292SN/A ADD_FIELD32(cold,12,10); // collision distance 5123870Sbinkertn@umich.edu ADD_FIELD32(swxoff,22,1); // software xoff transmission 5132292SN/A ADD_FIELD32(pbe,23,1); // packet burst enable 5142292SN/A ADD_FIELD32(rtlc,24,1); // retransmit late collisions 5152292SN/A ADD_FIELD32(nrtu,25,1); // on underrun no TX 5162292SN/A ADD_FIELD32(mulr,26,1); // multiple request 5172292SN/A }; 5182292SN/A TCTL tctl; 5192292SN/A 5202292SN/A struct PBA : public Reg<uint32_t> { // 0x1000 PBA Register 5212292SN/A using Reg<uint32_t>::operator=; 5223867Sbinkertn@umich.edu ADD_FIELD32(rxa,0,16); 5233867Sbinkertn@umich.edu ADD_FIELD32(txa,16,16); 5242292SN/A }; 5253867Sbinkertn@umich.edu PBA pba; 5263867Sbinkertn@umich.edu 5273867Sbinkertn@umich.edu struct FCRTL : public Reg<uint32_t> { // 0x2160 FCRTL Register 5282292SN/A using Reg<uint32_t>::operator=; 5292292SN/A ADD_FIELD32(rtl,3,28); // make this bigger than the spec so we can have 5302292SN/A // a larger buffer 5312292SN/A ADD_FIELD32(xone, 31,1); 5322292SN/A }; 5332292SN/A FCRTL fcrtl; 5342292SN/A 5352292SN/A struct FCRTH : public Reg<uint32_t> { // 0x2168 FCRTL Register 5362292SN/A using Reg<uint32_t>::operator=; 5372292SN/A ADD_FIELD32(rth,3,13); // make this bigger than the spec so we can have 5382292SN/A //a larger buffer 5392292SN/A ADD_FIELD32(xfce, 31,1); 5402292SN/A }; 5413870Sbinkertn@umich.edu FCRTH fcrth; 5422292SN/A 5432292SN/A struct RDBA : public Reg<uint64_t> { // 0x2800 RDBA Register 5442292SN/A using Reg<uint64_t>::operator=; 5452292SN/A ADD_FIELD64(rdbal,0,32); // base address of rx descriptor ring 5462292SN/A ADD_FIELD64(rdbah,32,32); // base address of rx descriptor ring 5472292SN/A }; 5482292SN/A RDBA rdba; 5492292SN/A 5502292SN/A struct RDLEN : public Reg<uint32_t> { // 0x2808 RDLEN Register 5513867Sbinkertn@umich.edu using Reg<uint32_t>::operator=; 5523867Sbinkertn@umich.edu ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer 5532292SN/A }; 5543867Sbinkertn@umich.edu RDLEN rdlen; 5553867Sbinkertn@umich.edu 5563867Sbinkertn@umich.edu struct SRRCTL : public Reg<uint32_t> { // 0x280C SRRCTL Register 5572292SN/A using Reg<uint32_t>::operator=; 5582292SN/A ADD_FIELD32(pktlen, 0, 8); 5592292SN/A ADD_FIELD32(hdrlen, 8, 8); // guess based on header, not documented 5602292SN/A ADD_FIELD32(desctype, 25,3); // type of descriptor 000 legacy, 001 adv, 5612292SN/A //101 hdr split 5622292SN/A unsigned bufLen() { return pktlen() << 10; } 5632292SN/A unsigned hdrLen() { return hdrlen() << 6; } 5642292SN/A }; 5652292SN/A SRRCTL srrctl; 5662292SN/A 5672292SN/A struct RDH : public Reg<uint32_t> { // 0x2810 RDH Register 5683870Sbinkertn@umich.edu using Reg<uint32_t>::operator=; 5692292SN/A ADD_FIELD32(rdh,0,16); // head of the descriptor ring 5702292SN/A }; 5712292SN/A RDH rdh; 5722292SN/A 5732292SN/A struct RDT : public Reg<uint32_t> { // 0x2818 RDT Register 5742292SN/A using Reg<uint32_t>::operator=; 5752292SN/A ADD_FIELD32(rdt,0,16); // tail of the descriptor ring 5762292SN/A }; 5772292SN/A RDT rdt; 5783867Sbinkertn@umich.edu 5793867Sbinkertn@umich.edu struct RDTR : public Reg<uint32_t> { // 0x2820 RDTR Register 5802292SN/A using Reg<uint32_t>::operator=; 5813867Sbinkertn@umich.edu ADD_FIELD32(delay,0,16); // receive delay timer 5822864Sktlim@umich.edu ADD_FIELD32(fpd, 31,1); // flush partial descriptor block ?? 5832864Sktlim@umich.edu }; 5843867Sbinkertn@umich.edu RDTR rdtr; 5853867Sbinkertn@umich.edu 5863867Sbinkertn@umich.edu struct RXDCTL : public Reg<uint32_t> { // 0x2828 RXDCTL Register 5872292SN/A using Reg<uint32_t>::operator=; 5882292SN/A ADD_FIELD32(pthresh,0,6); // prefetch threshold, less that this 5892292SN/A // consider prefetch 5902292SN/A ADD_FIELD32(hthresh,8,6); // number of descriptors in host mem to 5912292SN/A // consider prefetch 5922292SN/A ADD_FIELD32(wthresh,16,6); // writeback threshold 5932292SN/A ADD_FIELD32(gran,24,1); // granularity 0 = desc, 1 = cacheline 5942292SN/A }; 5952292SN/A RXDCTL rxdctl; 5962292SN/A 5972292SN/A struct RADV : public Reg<uint32_t> { // 0x282C RADV Register 5983867Sbinkertn@umich.edu using Reg<uint32_t>::operator=; 5993867Sbinkertn@umich.edu ADD_FIELD32(idv,0,16); // absolute interrupt delay 6002292SN/A }; 6013867Sbinkertn@umich.edu RADV radv; 6023867Sbinkertn@umich.edu 6033867Sbinkertn@umich.edu struct RSRPD : public Reg<uint32_t> { // 0x2C00 RSRPD Register 6042292SN/A using Reg<uint32_t>::operator=; 6052292SN/A ADD_FIELD32(idv,0,12); // size to interrutp on small packets 6062292SN/A }; 6072292SN/A RSRPD rsrpd; 6082292SN/A 6092292SN/A struct TDBA : public Reg<uint64_t> { // 0x3800 TDBAL Register 6102292SN/A using Reg<uint64_t>::operator=; 6112292SN/A ADD_FIELD64(tdbal,0,32); // base address of transmit descriptor ring 6122292SN/A ADD_FIELD64(tdbah,32,32); // base address of transmit descriptor ring 6132292SN/A }; 6142292SN/A TDBA tdba; 6153867Sbinkertn@umich.edu 6163867Sbinkertn@umich.edu struct TDLEN : public Reg<uint32_t> { // 0x3808 TDLEN Register 6172292SN/A using Reg<uint32_t>::operator=; 6183867Sbinkertn@umich.edu ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer 6193867Sbinkertn@umich.edu }; 6203867Sbinkertn@umich.edu TDLEN tdlen; 6212292SN/A 6222292SN/A struct TDH : public Reg<uint32_t> { // 0x3810 TDH Register 6232292SN/A using Reg<uint32_t>::operator=; 624 ADD_FIELD32(tdh,0,16); // head of the descriptor ring 625 }; 626 TDH tdh; 627 628 struct TXDCA_CTL : public Reg<uint32_t> { // 0x3814 TXDCA_CTL Register 629 using Reg<uint32_t>::operator=; 630 ADD_FIELD32(cpu_mask, 0, 5); 631 ADD_FIELD32(enabled, 5,1); 632 ADD_FIELD32(relax_ordering, 6, 1); 633 }; 634 TXDCA_CTL txdca_ctl; 635 636 struct TDT : public Reg<uint32_t> { // 0x3818 TDT Register 637 using Reg<uint32_t>::operator=; 638 ADD_FIELD32(tdt,0,16); // tail of the descriptor ring 639 }; 640 TDT tdt; 641 642 struct TIDV : public Reg<uint32_t> { // 0x3820 TIDV Register 643 using Reg<uint32_t>::operator=; 644 ADD_FIELD32(idv,0,16); // interrupt delay 645 }; 646 TIDV tidv; 647 648 struct TXDCTL : public Reg<uint32_t> { // 0x3828 TXDCTL Register 649 using Reg<uint32_t>::operator=; 650 ADD_FIELD32(pthresh, 0,6); // if number of descriptors control has is 651 // below this number, a prefetch is considered 652 ADD_FIELD32(hthresh,8,8); // number of valid descriptors is host memory 653 // before a prefetch is considered 654 ADD_FIELD32(wthresh,16,6); // number of descriptors to keep until 655 // writeback is considered 656 ADD_FIELD32(gran, 24,1); // granulatiry of above values (0 = cacheline, 657 // 1 == desscriptor) 658 ADD_FIELD32(lwthresh,25,7); // xmit descriptor low thresh, interrupt 659 // below this level 660 }; 661 TXDCTL txdctl; 662 663 struct TADV : public Reg<uint32_t> { // 0x382C TADV Register 664 using Reg<uint32_t>::operator=; 665 ADD_FIELD32(idv,0,16); // absolute interrupt delay 666 }; 667 TADV tadv; 668/* 669 struct TDWBA : public Reg<uint64_t> { // 0x3838 TDWBA Register 670 using Reg<uint64_t>::operator=; 671 ADD_FIELD64(en,0,1); // enable transmit description ring address writeback 672 ADD_FIELD64(tdwbal,2,32); // base address of transmit descriptor ring address writeback 673 ADD_FIELD64(tdwbah,32,32); // base address of transmit descriptor ring 674 }; 675 TDWBA tdwba;*/ 676 uint64_t tdwba; 677 678 struct RXCSUM : public Reg<uint32_t> { // 0x5000 RXCSUM Register 679 using Reg<uint32_t>::operator=; 680 ADD_FIELD32(pcss,0,8); 681 ADD_FIELD32(ipofld,8,1); 682 ADD_FIELD32(tuofld,9,1); 683 ADD_FIELD32(pcsd, 13,1); 684 }; 685 RXCSUM rxcsum; 686 687 uint32_t rlpml; // 0x5004 RLPML probably maximum accepted packet size 688 689 struct RFCTL : public Reg<uint32_t> { // 0x5008 RFCTL Register 690 using Reg<uint32_t>::operator=; 691 ADD_FIELD32(iscsi_dis,0,1); 692 ADD_FIELD32(iscsi_dwc,1,5); 693 ADD_FIELD32(nfsw_dis,6,1); 694 ADD_FIELD32(nfsr_dis,7,1); 695 ADD_FIELD32(nfs_ver,8,2); 696 ADD_FIELD32(ipv6_dis,10,1); 697 ADD_FIELD32(ipv6xsum_dis,11,1); 698 ADD_FIELD32(ackdis,13,1); 699 ADD_FIELD32(ipfrsp_dis,14,1); 700 ADD_FIELD32(exsten,15,1); 701 }; 702 RFCTL rfctl; 703 704 struct MANC : public Reg<uint32_t> { // 0x5820 MANC Register 705 using Reg<uint32_t>::operator=; 706 ADD_FIELD32(smbus,0,1); // SMBus enabled ##### 707 ADD_FIELD32(asf,1,1); // ASF enabled ##### 708 ADD_FIELD32(ronforce,2,1); // reset of force 709 ADD_FIELD32(rsvd,3,5); // reserved 710 ADD_FIELD32(rmcp1,8,1); // rcmp1 filtering 711 ADD_FIELD32(rmcp2,9,1); // rcmp2 filtering 712 ADD_FIELD32(ipv4,10,1); // enable ipv4 713 ADD_FIELD32(ipv6,11,1); // enable ipv6 714 ADD_FIELD32(snap,12,1); // accept snap 715 ADD_FIELD32(arp,13,1); // filter arp ##### 716 ADD_FIELD32(neighbor,14,1); // neighbor discovery 717 ADD_FIELD32(arp_resp,15,1); // arp response 718 ADD_FIELD32(tcorst,16,1); // tco reset happened 719 ADD_FIELD32(rcvtco,17,1); // receive tco enabled ###### 720 ADD_FIELD32(blkphyrst,18,1);// block phy resets ######## 721 ADD_FIELD32(rcvall,19,1); // receive all 722 ADD_FIELD32(macaddrfltr,20,1); // mac address filtering ###### 723 ADD_FIELD32(mng2host,21,1); // mng2 host packets ####### 724 ADD_FIELD32(ipaddrfltr,22,1); // ip address filtering 725 ADD_FIELD32(xsumfilter,23,1); // checksum filtering 726 ADD_FIELD32(brfilter,24,1); // broadcast filtering 727 ADD_FIELD32(smbreq,25,1); // smb request 728 ADD_FIELD32(smbgnt,26,1); // smb grant 729 ADD_FIELD32(smbclkin,27,1); // smbclkin 730 ADD_FIELD32(smbdatain,28,1); // smbdatain 731 ADD_FIELD32(smbdataout,29,1); // smb data out 732 ADD_FIELD32(smbclkout,30,1); // smb clock out 733 }; 734 MANC manc; 735 736 struct SWSM : public Reg<uint32_t> { // 0x5B50 SWSM register 737 using Reg<uint32_t>::operator=; 738 ADD_FIELD32(smbi,0,1); // Semaphone bit 739 ADD_FIELD32(swesmbi, 1,1); // Software eeporm semaphore 740 ADD_FIELD32(wmng, 2,1); // Wake MNG clock 741 ADD_FIELD32(reserved, 3, 29); 742 }; 743 SWSM swsm; 744 745 struct FWSM : public Reg<uint32_t> { // 0x5B54 FWSM register 746 using Reg<uint32_t>::operator=; 747 ADD_FIELD32(eep_fw_semaphore,0,1); 748 ADD_FIELD32(fw_mode, 1,3); 749 ADD_FIELD32(ide, 4,1); 750 ADD_FIELD32(sol, 5,1); 751 ADD_FIELD32(eep_roload, 6,1); 752 ADD_FIELD32(reserved, 7,8); 753 ADD_FIELD32(fw_val_bit, 15, 1); 754 ADD_FIELD32(reset_cnt, 16, 3); 755 ADD_FIELD32(ext_err_ind, 19, 6); 756 ADD_FIELD32(reserved2, 25, 7); 757 }; 758 FWSM fwsm; 759 760 uint32_t sw_fw_sync; 761 762 void serialize(std::ostream &os) 763 { 764 paramOut(os, "ctrl", ctrl._data); 765 paramOut(os, "sts", sts._data); 766 paramOut(os, "eecd", eecd._data); 767 paramOut(os, "eerd", eerd._data); 768 paramOut(os, "ctrl_ext", ctrl_ext._data); 769 paramOut(os, "mdic", mdic._data); 770 paramOut(os, "icr", icr._data); 771 SERIALIZE_SCALAR(imr); 772 paramOut(os, "itr", itr._data); 773 SERIALIZE_SCALAR(iam); 774 paramOut(os, "rctl", rctl._data); 775 paramOut(os, "fcttv", fcttv._data); 776 paramOut(os, "tctl", tctl._data); 777 paramOut(os, "pba", pba._data); 778 paramOut(os, "fcrtl", fcrtl._data); 779 paramOut(os, "fcrth", fcrth._data); 780 paramOut(os, "rdba", rdba._data); 781 paramOut(os, "rdlen", rdlen._data); 782 paramOut(os, "srrctl", srrctl._data); 783 paramOut(os, "rdh", rdh._data); 784 paramOut(os, "rdt", rdt._data); 785 paramOut(os, "rdtr", rdtr._data); 786 paramOut(os, "rxdctl", rxdctl._data); 787 paramOut(os, "radv", radv._data); 788 paramOut(os, "rsrpd", rsrpd._data); 789 paramOut(os, "tdba", tdba._data); 790 paramOut(os, "tdlen", tdlen._data); 791 paramOut(os, "tdh", tdh._data); 792 paramOut(os, "txdca_ctl", txdca_ctl._data); 793 paramOut(os, "tdt", tdt._data); 794 paramOut(os, "tidv", tidv._data); 795 paramOut(os, "txdctl", txdctl._data); 796 paramOut(os, "tadv", tadv._data); 797 //paramOut(os, "tdwba", tdwba._data); 798 SERIALIZE_SCALAR(tdwba); 799 paramOut(os, "rxcsum", rxcsum._data); 800 SERIALIZE_SCALAR(rlpml); 801 paramOut(os, "rfctl", rfctl._data); 802 paramOut(os, "manc", manc._data); 803 paramOut(os, "swsm", swsm._data); 804 paramOut(os, "fwsm", fwsm._data); 805 SERIALIZE_SCALAR(sw_fw_sync); 806 } 807 808 void unserialize(Checkpoint *cp, const std::string §ion) 809 { 810 paramIn(cp, section, "ctrl", ctrl._data); 811 paramIn(cp, section, "sts", sts._data); 812 paramIn(cp, section, "eecd", eecd._data); 813 paramIn(cp, section, "eerd", eerd._data); 814 paramIn(cp, section, "ctrl_ext", ctrl_ext._data); 815 paramIn(cp, section, "mdic", mdic._data); 816 paramIn(cp, section, "icr", icr._data); 817 UNSERIALIZE_SCALAR(imr); 818 paramIn(cp, section, "itr", itr._data); 819 UNSERIALIZE_SCALAR(iam); 820 paramIn(cp, section, "rctl", rctl._data); 821 paramIn(cp, section, "fcttv", fcttv._data); 822 paramIn(cp, section, "tctl", tctl._data); 823 paramIn(cp, section, "pba", pba._data); 824 paramIn(cp, section, "fcrtl", fcrtl._data); 825 paramIn(cp, section, "fcrth", fcrth._data); 826 paramIn(cp, section, "rdba", rdba._data); 827 paramIn(cp, section, "rdlen", rdlen._data); 828 paramIn(cp, section, "srrctl", srrctl._data); 829 paramIn(cp, section, "rdh", rdh._data); 830 paramIn(cp, section, "rdt", rdt._data); 831 paramIn(cp, section, "rdtr", rdtr._data); 832 paramIn(cp, section, "rxdctl", rxdctl._data); 833 paramIn(cp, section, "radv", radv._data); 834 paramIn(cp, section, "rsrpd", rsrpd._data); 835 paramIn(cp, section, "tdba", tdba._data); 836 paramIn(cp, section, "tdlen", tdlen._data); 837 paramIn(cp, section, "tdh", tdh._data); 838 paramIn(cp, section, "txdca_ctl", txdca_ctl._data); 839 paramIn(cp, section, "tdt", tdt._data); 840 paramIn(cp, section, "tidv", tidv._data); 841 paramIn(cp, section, "txdctl", txdctl._data); 842 paramIn(cp, section, "tadv", tadv._data); 843 UNSERIALIZE_SCALAR(tdwba); 844 //paramIn(cp, section, "tdwba", tdwba._data); 845 paramIn(cp, section, "rxcsum", rxcsum._data); 846 UNSERIALIZE_SCALAR(rlpml); 847 paramIn(cp, section, "rfctl", rfctl._data); 848 paramIn(cp, section, "manc", manc._data); 849 paramIn(cp, section, "swsm", swsm._data); 850 paramIn(cp, section, "fwsm", fwsm._data); 851 UNSERIALIZE_SCALAR(sw_fw_sync); 852 } 853}; 854} // namespace iGbReg 855