i8254xGBe_defs.hh revision 4218
16145SN/A/* 26386SN/A * Copyright (c) 2006 The Regents of The University of Michigan 36386SN/A * All rights reserved. 46386SN/A * 56386SN/A * Redistribution and use in source and binary forms, with or without 66386SN/A * modification, are permitted provided that the following conditions are 76386SN/A * met: redistributions of source code must retain the above copyright 86386SN/A * notice, this list of conditions and the following disclaimer; 96386SN/A * redistributions in binary form must reproduce the above copyright 106386SN/A * notice, this list of conditions and the following disclaimer in the 116386SN/A * documentation and/or other materials provided with the distribution; 126386SN/A * neither the name of the copyright holders nor the names of its 136386SN/A * contributors may be used to endorse or promote products derived from 146386SN/A * this software without specific prior written permission. 156386SN/A * 166386SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176386SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186386SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196386SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206386SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216386SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226386SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236386SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246386SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256386SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266386SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276386SN/A * 286145SN/A * Authors: Ali Saidi 297553SN/A */ 3011320Ssteve.reinhardt@amd.com 317553SN/A/* @file 327553SN/A * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers. 337553SN/A */ 346145SN/A#include "base/bitfield.hh" 357553SN/A 367553SN/Anamespace iGbReg { 376145SN/A 388229Snate@binkert.orgconst uint32_t REG_CTRL = 0x00000; //* 397632SBrad.Beckmann@amd.comconst uint32_t REG_STATUS = 0x00008; //* 4014184Sgabeblack@google.comconst uint32_t REG_EECD = 0x00010; //* 417553SN/Aconst uint32_t REG_EERD = 0x00014; //* 426145SN/Aconst uint32_t REG_CTRL_EXT = 0x00018; //*- 4311320Ssteve.reinhardt@amd.comconst uint32_t REG_MDIC = 0x00020; //* 447553SN/Aconst uint32_t REG_FCAL = 0x00028; //* 457553SN/Aconst uint32_t REG_FCAH = 0x0002C; //* 467553SN/Aconst uint32_t REG_FCT = 0x00030; //* 477553SN/Aconst uint32_t REG_VET = 0x00038; //* 4811320Ssteve.reinhardt@amd.comconst uint32_t REG_PBA = 0x01000; //* 497553SN/Aconst uint32_t REG_ICR = 0x000C0; //* 5011320Ssteve.reinhardt@amd.comconst uint32_t REG_ITR = 0x000C4; //* 517553SN/Aconst uint32_t REG_ICS = 0x000C8; //* 528655Sandreas.hansson@arm.comconst uint32_t REG_IMS = 0x000D0; //* 5311320Ssteve.reinhardt@amd.comconst uint32_t REG_IMC = 0x000D8; //* 547553SN/Aconst uint32_t REG_IAM = 0x000E0; //* 557553SN/Aconst uint32_t REG_RCTL = 0x00100; //* 567553SN/Aconst uint32_t REG_FCTTV = 0x00170; //* 578655Sandreas.hansson@arm.comconst uint32_t REG_TIPG = 0x00410; //* 588655Sandreas.hansson@arm.comconst uint32_t REG_AIFS = 0x00458; //* 598655Sandreas.hansson@arm.comconst uint32_t REG_LEDCTL = 0x00e00; //* 606145SN/Aconst uint32_t REG_FCRTL = 0x02160; //* 616145SN/Aconst uint32_t REG_FCRTH = 0x02168; //* 627553SN/Aconst uint32_t REG_RDBAL = 0x02800; //*- 636145SN/Aconst uint32_t REG_RDBAH = 0x02804; //*- 64const uint32_t REG_RDLEN = 0x02808; //*- 65const uint32_t REG_RDH = 0x02810; //*- 66const uint32_t REG_RDT = 0x02818; //*- 67const uint32_t REG_RDTR = 0x02820; //*- 68const uint32_t REG_RXDCTL = 0x02828; //* 69const uint32_t REG_RADV = 0x0282C; //*- 70const uint32_t REG_RSRPD = 0x02C00; 71const uint32_t REG_TCTL = 0x00400; //* 72const uint32_t REG_TDBAL = 0x03800; //* 73const uint32_t REG_TDBAH = 0x03804; //* 74const uint32_t REG_TDLEN = 0x03808; //* 75const uint32_t REG_TDH = 0x03810; //* 76const uint32_t REG_TDT = 0x03818; //* 77const uint32_t REG_TIDV = 0x03820; //* 78const uint32_t REG_TXDMAC = 0x03000; 79const uint32_t REG_TXDCTL = 0x03828; //* 80const uint32_t REG_TADV = 0x0382C; //* 81const uint32_t REG_TSPMT = 0x03830; 82const uint32_t REG_CRCERRS = 0x04000; 83const uint32_t REG_RXCSUM = 0x05000; //*- 84const uint32_t REG_MTA = 0x05200; 85const uint32_t REG_RAL = 0x05400; 86const uint32_t REG_RAH = 0x05404; 87const uint32_t REG_VFTA = 0x05600; 88 89const uint32_t REG_WUC = 0x05800;//* 90const uint32_t REG_MANC = 0x05820;//* 91 92const uint8_t EEPROM_READ_OPCODE_SPI = 0x03; 93const uint8_t EEPROM_RDSR_OPCODE_SPI = 0x05; 94const uint8_t EEPROM_SIZE = 64; 95const uint16_t EEPROM_CSUM = 0xBABA; 96 97const uint8_t VLAN_FILTER_TABLE_SIZE = 128; 98const uint8_t RCV_ADDRESS_TABLE_SIZE = 16; 99const uint8_t MULTICAST_TABLE_SIZE = 128; 100const uint32_t STATS_REGS_SIZE = 0x124; 101 102const uint8_t PHY_PSTATUS = 0x1; 103const uint8_t PHY_PID = 0x2; 104const uint8_t PHY_EPID = 0x3; 105const uint8_t PHY_GSTATUS = 10; 106const uint8_t PHY_EPSTATUS = 15; 107const uint8_t PHY_AGC = 18; 108 109 110struct RxDesc { 111 Addr buf; 112 uint16_t len; 113 uint16_t csum; 114 union { 115 uint8_t status; 116 struct { // these may be in the worng order 117 uint8_t dd:1; // descriptor done (hw is done when 1) 118 uint8_t eop:1; // end of packet 119 uint8_t xism:1; // ignore checksum 120 uint8_t vp:1; // packet is vlan packet 121 uint8_t rsv:1; // reserved 122 uint8_t tcpcs:1; // TCP checksum done 123 uint8_t ipcs:1; // IP checksum done 124 uint8_t pif:1; // passed in-exact filter 125 } st; 126 }; 127 union { 128 uint8_t errors; 129 struct { 130 uint8_t ce:1; // crc error or alignment error 131 uint8_t se:1; // symbol error 132 uint8_t seq:1; // sequence error 133 uint8_t rsv:1; // reserved 134 uint8_t cxe:1; // carrier extension error 135 uint8_t tcpe:1; // tcp checksum error 136 uint8_t ipe:1; // ip checksum error 137 uint8_t rxe:1; // PX data error 138 } er; 139 }; 140 union { 141 uint16_t special; 142 struct { 143 uint16_t vlan:12; //vlan id 144 uint16_t cfi:1; // canocial form id 145 uint16_t pri:3; // user priority 146 } sp; 147 }; 148}; 149 150union TxDesc { 151 uint8_t data[16]; 152 struct { 153 Addr buf; 154 uint16_t len; 155 uint8_t cso; 156 union { 157 uint8_t command; 158 struct { 159 uint8_t eop:1; // end of packet 160 uint8_t ifcs:1; // insert crc 161 uint8_t ic:1; // insert checksum 162 uint8_t rs:1; // report status 163 uint8_t rps:1; // report packet sent 164 uint8_t dext:1; // extension 165 uint8_t vle:1; // vlan enable 166 uint8_t ide:1; // interrupt delay enable 167 } cmd; 168 }; 169 union { 170 uint8_t status:4; 171 struct { 172 uint8_t dd:1; // descriptor done 173 uint8_t ec:1; // excess collisions 174 uint8_t lc:1; // late collision 175 uint8_t tu:1; // transmit underrun 176 } st; 177 }; 178 uint8_t reserved:4; 179 uint8_t css; 180 union { 181 uint16_t special; 182 struct { 183 uint16_t vlan:12; //vlan id 184 uint16_t cfi:1; // canocial form id 185 uint16_t pri:3; // user priority 186 } sp; 187 }; 188 } legacy; 189 190 // Type 0000 descriptor 191 struct { 192 uint8_t ipcss; 193 uint8_t ipcso; 194 uint16_t ipcse; 195 uint8_t tucss; 196 uint8_t tucso; 197 uint16_t tucse; 198 uint32_t paylen:20; 199 uint8_t dtype:4; 200 union { 201 uint8_t tucommand; 202 struct { 203 uint8_t tcp:1; // tcp/udp 204 uint8_t ip:1; // ip ipv4/ipv6 205 uint8_t tse:1; // tcp segment enbale 206 uint8_t rs:1; // report status 207 uint8_t rsv0:1; // reserved 208 uint8_t dext:1; // descriptor extension 209 uint8_t rsv1:1; // reserved 210 uint8_t ide:1; // interrupt delay enable 211 } tucmd; 212 }; 213 union { 214 uint8_t status:4; 215 struct { 216 uint8_t dd:1; 217 uint8_t rsvd:3; 218 } sta; 219 }; 220 uint8_t reserved:4; 221 uint8_t hdrlen; 222 uint16_t mss; 223 } t0; 224 225 // Type 0001 descriptor 226 struct { 227 Addr buf; 228 uint32_t dtalen:20; 229 uint8_t dtype:4; 230 union { 231 uint8_t dcommand; 232 struct { 233 uint8_t eop:1; // end of packet 234 uint8_t ifcs:1; // insert crc 235 uint8_t tse:1; // segmentation enable 236 uint8_t rs:1; // report status 237 uint8_t rps:1; // report packet sent 238 uint8_t dext:1; // extension 239 uint8_t vle:1; // vlan enable 240 uint8_t ide:1; // interrupt delay enable 241 } dcmd; 242 }; 243 union { 244 uint8_t status:4; 245 struct { 246 uint8_t dd:1; // descriptor done 247 uint8_t ec:1; // excess collisions 248 uint8_t lc:1; // late collision 249 uint8_t tu:1; // transmit underrun 250 } sta; 251 }; 252 union { 253 uint8_t pktopts; 254 struct { 255 uint8_t ixsm:1; // insert ip checksum 256 uint8_t txsm:1; // insert tcp checksum 257 }; 258 }; 259 union { 260 uint16_t special; 261 struct { 262 uint16_t vlan:12; //vlan id 263 uint16_t cfi:1; // canocial form id 264 uint16_t pri:3; // user priority 265 } sp; 266 }; 267 } t1; 268 269 // Junk to test descriptor type! 270 struct { 271 uint64_t junk; 272 uint32_t junk1:20; 273 uint8_t dtype; 274 uint8_t junk2:5; 275 uint8_t dext:1; 276 uint8_t junk3:2; 277 uint8_t junk4:4; 278 uint32_t junk5; 279 } type; 280}; 281 282#define ADD_FIELD32(NAME, OFFSET, BITS) \ 283 inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 284 inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 285 286#define ADD_FIELD64(NAME, OFFSET, BITS) \ 287 inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 288 inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 289 290struct Regs { 291 template<class T> 292 struct Reg { 293 T _data; 294 T operator()() { return _data; } 295 const Reg<T> &operator=(T d) { _data = d; return *this;} 296 bool operator==(T d) { return d == _data; } 297 void operator()(T d) { _data = d; } 298 }; 299 300 struct CTRL : public Reg<uint32_t> { // 0x0000 CTRL Register 301 using Reg<uint32_t>::operator=; 302 ADD_FIELD32(fd,0,1); // full duplex 303 ADD_FIELD32(bem,1,1); // big endian mode 304 ADD_FIELD32(pcipr,2,1); // PCI priority 305 ADD_FIELD32(lrst,3,1); // link reset 306 ADD_FIELD32(tme,4,1); // test mode enable 307 ADD_FIELD32(asde,5,1); // Auto-speed detection 308 ADD_FIELD32(slu,6,1); // Set link up 309 ADD_FIELD32(ilos,7,1); // invert los-of-signal 310 ADD_FIELD32(speed,8,2); // speed selection bits 311 ADD_FIELD32(be32,10,1); // big endian mode 32 312 ADD_FIELD32(frcspd,11,1); // force speed 313 ADD_FIELD32(frcdpx,12,1); // force duplex 314 ADD_FIELD32(duden,13,1); // dock/undock enable 315 ADD_FIELD32(dudpol,14,1); // dock/undock polarity 316 ADD_FIELD32(fphyrst,15,1); // force phy reset 317 ADD_FIELD32(extlen,16,1); // external link status enable 318 ADD_FIELD32(rsvd,17,1); // reserved 319 ADD_FIELD32(sdp0d,18,1); // software controlled pin data 320 ADD_FIELD32(sdp1d,19,1); // software controlled pin data 321 ADD_FIELD32(sdp2d,20,1); // software controlled pin data 322 ADD_FIELD32(sdp3d,21,1); // software controlled pin data 323 ADD_FIELD32(sdp0i,22,1); // software controlled pin dir 324 ADD_FIELD32(sdp1i,23,1); // software controlled pin dir 325 ADD_FIELD32(sdp2i,24,1); // software controlled pin dir 326 ADD_FIELD32(sdp3i,25,1); // software controlled pin dir 327 ADD_FIELD32(rst,26,1); // reset 328 ADD_FIELD32(rfce,27,1); // receive flow control enable 329 ADD_FIELD32(tfce,28,1); // transmit flow control enable 330 ADD_FIELD32(rte,29,1); // routing tag enable 331 ADD_FIELD32(vme,30,1); // vlan enable 332 ADD_FIELD32(phyrst,31,1); // phy reset 333 }; 334 CTRL ctrl; 335 336 struct STATUS : public Reg<uint32_t> { // 0x0008 STATUS Register 337 using Reg<uint32_t>::operator=; 338 ADD_FIELD32(fd,0,1); // full duplex 339 ADD_FIELD32(lu,1,1); // link up 340 ADD_FIELD32(func,2,2); // function id 341 ADD_FIELD32(txoff,4,1); // transmission paused 342 ADD_FIELD32(tbimode,5,1); // tbi mode 343 ADD_FIELD32(speed,6,2); // link speed 344 ADD_FIELD32(asdv,8,2); // auto speed detection value 345 ADD_FIELD32(mtxckok,10,1); // mtx clock running ok 346 ADD_FIELD32(pci66,11,1); // In 66Mhz pci slot 347 ADD_FIELD32(bus64,12,1); // in 64 bit slot 348 ADD_FIELD32(pcix,13,1); // Pci mode 349 ADD_FIELD32(pcixspd,14,2); // pci x speed 350 }; 351 STATUS sts; 352 353 struct EECD : public Reg<uint32_t> { // 0x0010 EECD Register 354 using Reg<uint32_t>::operator=; 355 ADD_FIELD32(sk,0,1); // clack input to the eeprom 356 ADD_FIELD32(cs,1,1); // chip select to eeprom 357 ADD_FIELD32(din,2,1); // data input to eeprom 358 ADD_FIELD32(dout,3,1); // data output bit 359 ADD_FIELD32(fwe,4,2); // flash write enable 360 ADD_FIELD32(ee_req,6,1); // request eeprom access 361 ADD_FIELD32(ee_gnt,7,1); // grant eeprom access 362 ADD_FIELD32(ee_pres,8,1); // eeprom present 363 ADD_FIELD32(ee_size,9,1); // eeprom size 364 ADD_FIELD32(ee_sz1,10,1); // eeprom size 365 ADD_FIELD32(rsvd,11,2); // reserved 366 ADD_FIELD32(ee_type,13,1); // type of eeprom 367 } ; 368 EECD eecd; 369 370 struct EERD : public Reg<uint32_t> { // 0x0014 EERD Register 371 using Reg<uint32_t>::operator=; 372 ADD_FIELD32(start,0,1); // start read 373 ADD_FIELD32(done,4,1); // done read 374 ADD_FIELD32(addr,8,8); // address 375 ADD_FIELD32(data,16,16); // data 376 }; 377 EERD eerd; 378 379 struct CTRL_EXT : public Reg<uint32_t> { // 0x0018 CTRL_EXT Register 380 using Reg<uint32_t>::operator=; 381 ADD_FIELD32(gpi_en,0,4); // enable interrupts from gpio 382 ADD_FIELD32(phyint,5,1); // reads the phy internal int status 383 ADD_FIELD32(sdp2_data,6,1); // data from gpio sdp 384 ADD_FIELD32(spd3_data,7,1); // data frmo gpio sdp 385 ADD_FIELD32(spd2_iodir,10,1); // direction of sdp2 386 ADD_FIELD32(spd3_iodir,11,1); // direction of sdp2 387 ADD_FIELD32(asdchk,12,1); // initiate auto-speed-detection 388 ADD_FIELD32(eerst,13,1); // reset the eeprom 389 ADD_FIELD32(spd_byps,15,1); // bypass speed select 390 ADD_FIELD32(ro_dis,17,1); // disable relaxed memory ordering 391 ADD_FIELD32(vreg,21,1); // power down the voltage regulator 392 ADD_FIELD32(link_mode,22,2); // interface to talk to the link 393 ADD_FIELD32(iame, 27,1); // interrupt acknowledge auto-mask ?? 394 ADD_FIELD32(drv_loaded, 28,1);// driver is loaded and incharge of device 395 ADD_FIELD32(timer_clr, 29,1); // clear interrupt timers after IMS clear ?? 396 }; 397 CTRL_EXT ctrl_ext; 398 399 struct MDIC : public Reg<uint32_t> { // 0x0020 MDIC Register 400 using Reg<uint32_t>::operator=; 401 ADD_FIELD32(data,0,16); // data 402 ADD_FIELD32(regadd,16,5); // register address 403 ADD_FIELD32(phyadd,21,5); // phy addresses 404 ADD_FIELD32(op,26,2); // opcode 405 ADD_FIELD32(r,28,1); // ready 406 ADD_FIELD32(i,29,1); // interrupt 407 ADD_FIELD32(e,30,1); // error 408 }; 409 MDIC mdic; 410 411 struct ICR : public Reg<uint32_t> { // 0x00C0 ICR Register 412 using Reg<uint32_t>::operator=; 413 ADD_FIELD32(txdw,0,1) // tx descr witten back 414 ADD_FIELD32(txqe,1,1) // tx queue empty 415 ADD_FIELD32(lsc,2,1) // link status change 416 ADD_FIELD32(rxseq,3,1) // rcv sequence error 417 ADD_FIELD32(rxdmt0,4,1) // rcv descriptor min thresh 418 ADD_FIELD32(rsvd1,5,1) // reserved 419 ADD_FIELD32(rxo,6,1) // receive overrunn 420 ADD_FIELD32(rxt0,7,1) // receiver timer interrupt 421 ADD_FIELD32(mdac,9,1) // mdi/o access complete 422 ADD_FIELD32(rxcfg,10,1) // recv /c/ ordered sets 423 ADD_FIELD32(phyint,12,1) // phy interrupt 424 ADD_FIELD32(gpi1,13,1) // gpi int 1 425 ADD_FIELD32(gpi2,14,1) // gpi int 2 426 ADD_FIELD32(txdlow,15,1) // transmit desc low thresh 427 ADD_FIELD32(srpd,16,1) // small receive packet detected 428 ADD_FIELD32(ack,17,1); // receive ack frame 429 ADD_FIELD32(int_assert, 31,0); // interrupt caused a system interrupt 430 }; 431 ICR icr; 432 433 uint32_t imr; // register that contains the current interrupt mask 434 435 struct ITR : public Reg<uint32_t> { // 0x00C4 ITR Register 436 using Reg<uint32_t>::operator=; 437 ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval 438 // specified in 256ns interrupts 439 }; 440 ITR itr; 441 442 // When CTRL_EXT.IAME and the ICR.INT_ASSERT is 1 an ICR read or write 443 // causes the IAM register contents to be written into the IMC 444 // automatically clearing all interrupts that have a bit in the IAM set 445 uint32_t iam; 446 447 struct RCTL : public Reg<uint32_t> { // 0x0100 RCTL Register 448 using Reg<uint32_t>::operator=; 449 ADD_FIELD32(rst,0,1); // Reset 450 ADD_FIELD32(en,1,1); // Enable 451 ADD_FIELD32(sbp,2,1); // Store bad packets 452 ADD_FIELD32(upe,3,1); // Unicast Promiscuous enabled 453 ADD_FIELD32(mpe,4,1); // Multicast promiscuous enabled 454 ADD_FIELD32(lpe,5,1); // long packet reception enabled 455 ADD_FIELD32(lbm,6,2); // 456 ADD_FIELD32(rdmts,8,2); // 457 ADD_FIELD32(rsvd,10,2); // 458 ADD_FIELD32(mo,12,2); // 459 ADD_FIELD32(mdr,14,1); // 460 ADD_FIELD32(bam,15,1); // 461 ADD_FIELD32(bsize,16,2); // 462 ADD_FIELD32(vfe,18,1); // 463 ADD_FIELD32(cfien,19,1); // 464 ADD_FIELD32(cfi,20,1); // 465 ADD_FIELD32(rsvd2,21,1); // 466 ADD_FIELD32(dpf,22,1); // discard pause frames 467 ADD_FIELD32(pmcf,23,1); // pass mac control frames 468 ADD_FIELD32(bsex,25,1); // buffer size extension 469 ADD_FIELD32(secrc,26,1); // strip ethernet crc from incoming packet 470 }; 471 RCTL rctl; 472 473 struct FCTTV : public Reg<uint32_t> { // 0x0170 FCTTV 474 using Reg<uint32_t>::operator=; 475 ADD_FIELD32(ttv,0,16); // Transmit Timer Value 476 }; 477 FCTTV fcttv; 478 479 struct TCTL : public Reg<uint32_t> { // 0x0400 TCTL Register 480 using Reg<uint32_t>::operator=; 481 ADD_FIELD32(rst,0,1); // Reset 482 ADD_FIELD32(en,1,1); // Enable 483 ADD_FIELD32(bce,2,1); // busy check enable 484 ADD_FIELD32(psp,3,1); // pad short packets 485 ADD_FIELD32(ct,4,8); // collision threshold 486 ADD_FIELD32(cold,12,10); // collision distance 487 ADD_FIELD32(swxoff,22,1); // software xoff transmission 488 ADD_FIELD32(pbe,23,1); // packet burst enable 489 ADD_FIELD32(rtlc,24,1); // retransmit late collisions 490 ADD_FIELD32(nrtu,25,1); // on underrun no TX 491 ADD_FIELD32(mulr,26,1); // multiple request 492 }; 493 TCTL tctl; 494 495 struct PBA : public Reg<uint32_t> { // 0x1000 PBA Register 496 using Reg<uint32_t>::operator=; 497 ADD_FIELD32(rxa,0,16); 498 ADD_FIELD32(txa,16,16); 499 }; 500 PBA pba; 501 502 struct FCRTL : public Reg<uint32_t> { // 0x2160 FCRTL Register 503 using Reg<uint32_t>::operator=; 504 ADD_FIELD32(rtl,3,28); // make this bigger than the spec so we can have 505 // a larger buffer 506 ADD_FIELD32(xone, 31,1); 507 }; 508 FCRTL fcrtl; 509 510 struct FCRTH : public Reg<uint32_t> { // 0x2168 FCRTL Register 511 using Reg<uint32_t>::operator=; 512 ADD_FIELD32(rth,3,13); // make this bigger than the spec so we can have 513 //a larger buffer 514 ADD_FIELD32(xfce, 31,1); 515 }; 516 FCRTH fcrth; 517 518 struct RDBA : public Reg<uint64_t> { // 0x2800 RDBA Register 519 using Reg<uint64_t>::operator=; 520 ADD_FIELD64(rdbal,4,28); // base address of rx descriptor ring 521 ADD_FIELD64(rdbah,32,32); // base address of rx descriptor ring 522 }; 523 RDBA rdba; 524 525 struct RDLEN : public Reg<uint32_t> { // 0x2808 RDLEN Register 526 using Reg<uint32_t>::operator=; 527 ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer 528 }; 529 RDLEN rdlen; 530 531 struct RDH : public Reg<uint32_t> { // 0x2810 RDH Register 532 using Reg<uint32_t>::operator=; 533 ADD_FIELD32(rdh,0,16); // head of the descriptor ring 534 }; 535 RDH rdh; 536 537 struct RDT : public Reg<uint32_t> { // 0x2818 RDT Register 538 using Reg<uint32_t>::operator=; 539 ADD_FIELD32(rdt,0,16); // tail of the descriptor ring 540 }; 541 RDT rdt; 542 543 struct RDTR : public Reg<uint32_t> { // 0x2820 RDTR Register 544 using Reg<uint32_t>::operator=; 545 ADD_FIELD32(delay,0,16); // receive delay timer 546 ADD_FIELD32(fpd, 31,); // flush partial descriptor block ?? 547 }; 548 RDTR rdtr; 549 550 struct RADV : public Reg<uint32_t> { // 0x282C RADV Register 551 using Reg<uint32_t>::operator=; 552 ADD_FIELD32(idv,0,16); // absolute interrupt delay 553 }; 554 RADV radv; 555 556 struct RSRPD : public Reg<uint32_t> { // 0x2C00 RSRPD Register 557 using Reg<uint32_t>::operator=; 558 ADD_FIELD32(idv,0,12); // size to interrutp on small packets 559 }; 560 RSRPD rsrpd; 561 562 struct TDBA : public Reg<uint64_t> { // 0x3800 TDBAL Register 563 using Reg<uint64_t>::operator=; 564 ADD_FIELD64(tdbal,4,28); // base address of transmit descriptor ring 565 ADD_FIELD64(tdbah,32,32); // base address of transmit descriptor ring 566 }; 567 TDBA tdba; 568 569 struct TDLEN : public Reg<uint32_t> { // 0x3808 TDLEN Register 570 using Reg<uint32_t>::operator=; 571 ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer 572 }; 573 TDLEN tdlen; 574 575 struct TDH : public Reg<uint32_t> { // 0x3810 TDH Register 576 using Reg<uint32_t>::operator=; 577 ADD_FIELD32(tdh,0,16); // head of the descriptor ring 578 }; 579 TDH tdh; 580 581 struct TDT : public Reg<uint32_t> { // 0x3818 TDT Register 582 using Reg<uint32_t>::operator=; 583 ADD_FIELD32(tdt,0,16); // tail of the descriptor ring 584 }; 585 TDT tdt; 586 587 struct TIDV : public Reg<uint32_t> { // 0x3820 TIDV Register 588 using Reg<uint32_t>::operator=; 589 ADD_FIELD32(idv,0,16); // interrupt delay 590 }; 591 TIDV tidv; 592 593 struct TXDCTL : public Reg<uint32_t> { // 0x3828 TXDCTL Register 594 using Reg<uint32_t>::operator=; 595 ADD_FIELD32(pthresh, 0,6); // if number of descriptors control has is 596 // below this number, a prefetch is considered 597 ADD_FIELD32(hthresh,8,8); // number of valid descriptors is host memory 598 // before a prefetch is considered 599 ADD_FIELD32(wthresh,16,6); // number of descriptors to keep until 600 // writeback is considered 601 ADD_FIELD32(gran, 24,1); // granulatiry of above values (0 = cacheline, 602 // 1 == desscriptor) 603 ADD_FIELD32(lwthresh,25,7); // xmit descriptor low thresh, interrupt 604 // below this level 605 }; 606 TXDCTL txdctl; 607 608 struct TADV : public Reg<uint32_t> { // 0x382C TADV Register 609 using Reg<uint32_t>::operator=; 610 ADD_FIELD32(idv,0,16); // absolute interrupt delay 611 }; 612 TADV tadv; 613 614 struct RXCSUM : public Reg<uint32_t> { // 0x5000 RXCSUM Register 615 using Reg<uint32_t>::operator=; 616 ADD_FIELD32(pcss,0,8); 617 ADD_FIELD32(ipofld,8,1); 618 ADD_FIELD32(tuofld,9,1); 619 }; 620 RXCSUM rxcsum; 621 622 struct MANC : public Reg<uint32_t> { // 0x5820 MANC Register 623 using Reg<uint32_t>::operator=; 624 ADD_FIELD32(smbus,0,1); // SMBus enabled ##### 625 ADD_FIELD32(asf,1,1); // ASF enabled ##### 626 ADD_FIELD32(ronforce,2,1); // reset of force 627 ADD_FIELD32(rsvd,3,5); // reserved 628 ADD_FIELD32(rmcp1,8,1); // rcmp1 filtering 629 ADD_FIELD32(rmcp2,9,1); // rcmp2 filtering 630 ADD_FIELD32(ipv4,10,1); // enable ipv4 631 ADD_FIELD32(ipv6,11,1); // enable ipv6 632 ADD_FIELD32(snap,12,1); // accept snap 633 ADD_FIELD32(arp,13,1); // filter arp ##### 634 ADD_FIELD32(neighbor,14,1); // neighbor discovery 635 ADD_FIELD32(arp_resp,15,1); // arp response 636 ADD_FIELD32(tcorst,16,1); // tco reset happened 637 ADD_FIELD32(rcvtco,17,1); // receive tco enabled ###### 638 ADD_FIELD32(blkphyrst,18,1);// block phy resets ######## 639 ADD_FIELD32(rcvall,19,1); // receive all 640 ADD_FIELD32(macaddrfltr,20,1); // mac address filtering ###### 641 ADD_FIELD32(mng2host,21,1); // mng2 host packets ####### 642 ADD_FIELD32(ipaddrfltr,22,1); // ip address filtering 643 ADD_FIELD32(xsumfilter,23,1); // checksum filtering 644 ADD_FIELD32(brfilter,24,1); // broadcast filtering 645 ADD_FIELD32(smbreq,25,1); // smb request 646 ADD_FIELD32(smbgnt,26,1); // smb grant 647 ADD_FIELD32(smbclkin,27,1); // smbclkin 648 ADD_FIELD32(smbdatain,28,1); // smbdatain 649 ADD_FIELD32(smbdataout,29,1); // smb data out 650 ADD_FIELD32(smbclkout,30,1); // smb clock out 651 }; 652 MANC manc; 653}; 654 655}; // iGbReg namespace 656