i8254xGBe_defs.hh revision 3318
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31/* @file 32 * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers. 33 */ 34 35namespace iGbReg { 36 37const uint32_t CTRL = 0x00000; //* 38const uint32_t STATUS = 0x00008; //* 39const uint32_t EECD = 0x00010; //* 40const uint32_t EERD = 0x00014; //* 41const uint32_t CTRL_EXT = 0x00018; 42const uint32_t PBA = 0x01000; 43const uint32_t ICR = 0x000C0; //* 44const uint32_t ITR = 0x000C4; 45const uint32_t ICS = 0x000C8; 46const uint32_t IMS = 0x000D0; 47const uint32_t IMC = 0x000D8; //* 48const uint32_t RCTL = 0x00100; //* 49const uint32_t RDBAL = 0x02800; 50const uint32_t RDBAH = 0x02804; 51const uint32_t RDLEN = 0x02808; 52const uint32_t RDH = 0x02810; 53const uint32_t RDT = 0x02818; 54const uint32_t RDTR = 0x02820; 55const uint32_t RADV = 0x0282C; 56const uint32_t RSRPD = 0x02C00; 57const uint32_t TCTL = 0x00400; //* 58const uint32_t TDBAL = 0x03800; 59const uint32_t TDBAH = 0x03804; 60const uint32_t TDLEN = 0x03808; 61const uint32_t TDH = 0x03810; 62const uint32_t THT = 0x03818; 63const uint32_t TIDV = 0x03820; 64const uint32_t TXDMAC = 0x03000; 65const uint32_t TXDCTL = 0x03828; 66const uint32_t TADV = 0x0282C; 67const uint32_t TSPMT = 0x03830; 68const uint32_t RXDCTL = 0x02828; 69const uint32_t RXCSUM = 0x05000; 70const uint32_t MANC = 0x05820;//* 71 72const uint8_t EEPROM_READ_OPCODE_SPI = 0x03; 73const uint8_t EEPROM_RDSR_OPCODE_SPI = 0x05; 74const uint8_t EEPROM_SIZE = 64; 75 76struct RxDesc { 77 Addr buf; 78 uint16_t len; 79 uint16_t csum; 80 union { 81 uint8_t status; 82 struct { // these may be in the worng order 83 uint8_t dd:1; // descriptor done (hw is done when 1) 84 uint8_t eop:1; // end of packet 85 uint8_t xism:1; // ignore checksum 86 uint8_t vp:1; // packet is vlan packet 87 uint8_t rsv:1; // reserved 88 uint8_t tcpcs:1; // TCP checksum done 89 uint8_t ipcs:1; // IP checksum done 90 uint8_t pif:1; // passed in-exact filter 91 } st; 92 }; 93 union { 94 uint8_t errors; 95 struct { 96 uint8_t ce:1; // crc error or alignment error 97 uint8_t se:1; // symbol error 98 uint8_t seq:1; // sequence error 99 uint8_t rsv:1; // reserved 100 uint8_t cxe:1; // carrier extension error 101 uint8_t tcpe:1; // tcp checksum error 102 uint8_t ipe:1; // ip checksum error 103 uint8_t rxe:1; // PX data error 104 } er; 105 }; 106 union { 107 uint16_t special; 108 struct { 109 uint16_t vlan:12; //vlan id 110 uint16_t cfi:1; // canocial form id 111 uint16_t pri:3; // user priority 112 } sp; 113 }; 114}; 115 116union TxDesc { 117 uint8_t data[16]; 118 struct { 119 Addr buf; 120 uint16_t len; 121 uint8_t cso; 122 union { 123 uint8_t command; 124 struct { 125 uint8_t eop:1; // end of packet 126 uint8_t ifcs:1; // insert crc 127 uint8_t ic:1; // insert checksum 128 uint8_t rs:1; // report status 129 uint8_t rps:1; // report packet sent 130 uint8_t dext:1; // extension 131 uint8_t vle:1; // vlan enable 132 uint8_t ide:1; // interrupt delay enable 133 } cmd; 134 }; 135 union { 136 uint8_t status:4; 137 struct { 138 uint8_t dd:1; // descriptor done 139 uint8_t ec:1; // excess collisions 140 uint8_t lc:1; // late collision 141 uint8_t tu:1; // transmit underrun 142 } st; 143 }; 144 uint8_t reserved:4; 145 uint8_t css; 146 union { 147 uint16_t special; 148 struct { 149 uint16_t vlan:12; //vlan id 150 uint16_t cfi:1; // canocial form id 151 uint16_t pri:3; // user priority 152 } sp; 153 }; 154 } legacy; 155 156 // Type 0000 descriptor 157 struct { 158 uint8_t ipcss; 159 uint8_t ipcso; 160 uint16_t ipcse; 161 uint8_t tucss; 162 uint8_t tucso; 163 uint16_t tucse; 164 uint32_t paylen:20; 165 uint8_t dtype:4; 166 union { 167 uint8_t tucommand; 168 struct { 169 uint8_t tcp:1; // tcp/udp 170 uint8_t ip:1; // ip ipv4/ipv6 171 uint8_t tse:1; // tcp segment enbale 172 uint8_t rs:1; // report status 173 uint8_t rsv0:1; // reserved 174 uint8_t dext:1; // descriptor extension 175 uint8_t rsv1:1; // reserved 176 uint8_t ide:1; // interrupt delay enable 177 } tucmd; 178 }; 179 union { 180 uint8_t status:4; 181 struct { 182 uint8_t dd:1; 183 uint8_t rsvd:3; 184 } sta; 185 }; 186 uint8_t reserved:4; 187 uint8_t hdrlen; 188 uint16_t mss; 189 } t0; 190 191 // Type 0001 descriptor 192 struct { 193 Addr buf; 194 uint32_t dtalen:20; 195 uint8_t dtype:4; 196 union { 197 uint8_t dcommand; 198 struct { 199 uint8_t eop:1; // end of packet 200 uint8_t ifcs:1; // insert crc 201 uint8_t tse:1; // segmentation enable 202 uint8_t rs:1; // report status 203 uint8_t rps:1; // report packet sent 204 uint8_t dext:1; // extension 205 uint8_t vle:1; // vlan enable 206 uint8_t ide:1; // interrupt delay enable 207 } dcmd; 208 }; 209 union { 210 uint8_t status:4; 211 struct { 212 uint8_t dd:1; // descriptor done 213 uint8_t ec:1; // excess collisions 214 uint8_t lc:1; // late collision 215 uint8_t tu:1; // transmit underrun 216 } sta; 217 }; 218 union { 219 uint8_t pktopts; 220 struct { 221 uint8_t ixsm:1; // insert ip checksum 222 uint8_t txsm:1; // insert tcp checksum 223 }; 224 }; 225 union { 226 uint16_t special; 227 struct { 228 uint16_t vlan:12; //vlan id 229 uint16_t cfi:1; // canocial form id 230 uint16_t pri:3; // user priority 231 } sp; 232 }; 233 } t1; 234 235 // Junk to test descriptor type! 236 struct { 237 uint64_t junk; 238 uint32_t junk1:20; 239 uint8_t dtype; 240 uint8_t junk2:5; 241 uint8_t dext:1; 242 uint8_t junk3:2; 243 uint8_t junk4:4; 244 uint32_t junk5; 245 } type; 246}; 247 248struct Regs { 249 union { // 0x0000 CTRL Register 250 uint32_t reg; 251 struct { 252 uint8_t fd:1; // full duplex 253 uint8_t bem:1; // big endian mode 254 uint8_t pcipr:1; // PCI priority 255 uint8_t lrst:1; // link reset 256 uint8_t tme:1; // test mode enable 257 uint8_t asde:1; // Auto-speed detection 258 uint8_t slu:1; // Set link up 259 uint8_t ilos:1; // invert los-of-signal 260 uint8_t speed:2; // speed selection bits 261 uint8_t be32:1; // big endian mode 32 262 uint8_t frcspd:1; // force speed 263 uint8_t frcdpx:1; // force duplex 264 uint8_t duden:1; // dock/undock enable 265 uint8_t dudpol:1; // dock/undock polarity 266 uint8_t fphyrst:1; // force phy reset 267 uint8_t extlen:1; // external link status enable 268 uint8_t rsvd:1; // reserved 269 uint8_t sdp0d:1; // software controlled pin data 270 uint8_t sdp1d:1; // software controlled pin data 271 uint8_t sdp2d:1; // software controlled pin data 272 uint8_t sdp3d:1; // software controlled pin data 273 uint8_t sdp0i:1; // software controlled pin dir 274 uint8_t sdp1i:1; // software controlled pin dir 275 uint8_t sdp2i:1; // software controlled pin dir 276 uint8_t sdp3i:1; // software controlled pin dir 277 uint8_t rst:1; // reset 278 uint8_t rfce:1; // receive flow control enable 279 uint8_t tfce:1; // transmit flow control enable 280 uint8_t rte:1; // routing tag enable 281 uint8_t vme:1; // vlan enable 282 uint8_t phyrst:1; // phy reset 283 } ; 284 } ctrl; 285 286 union { // 0x0008 STATUS 287 uint32_t reg; 288 struct { 289 uint8_t fd:1; // full duplex 290 uint8_t lu:1; // link up 291 uint8_t func:2; // function id 292 uint8_t txoff:1; // transmission paused 293 uint8_t tbimode:1; // tbi mode 294 uint8_t speed:2; // link speed 295 uint8_t asdv:2; // auto speed detection value 296 uint8_t mtxckok:1; // mtx clock running ok 297 uint8_t pci66:1; // In 66Mhz pci slot 298 uint8_t bus64:1; // in 64 bit slot 299 uint8_t pcix:1; // Pci mode 300 uint8_t pcixspd:1; // pci x speed 301 uint8_t reserved; // reserved 302 } ; 303 } sts; 304 305 union { // 0x0010 EECD 306 uint32_t reg; 307 struct { 308 uint8_t sk:1; // clack input to the eeprom 309 uint8_t cs:1; // chip select to eeprom 310 uint8_t din:1; // data input to eeprom 311 uint8_t dout:1; // data output bit 312 uint8_t fwe:2; // flash write enable 313 uint8_t ee_req:1; // request eeprom access 314 uint8_t ee_gnt:1; // grant eeprom access 315 uint8_t ee_pres:1; // eeprom present 316 uint8_t ee_size:1; // eeprom size 317 uint8_t ee_sz1:1; // eeprom size 318 uint8_t rsvd:2; // reserved 319 uint8_t ee_type:1; // type of eeprom 320 } ; 321 } eecd; 322 323 union { // 0x0014 EERD 324 uint32_t reg; 325 struct { 326 uint8_t start:1; // start read 327 uint8_t done:1; // done read 328 uint16_t addr:14; // address 329 uint16_t data; // data 330 }; 331 } eerd; 332 333 union { // 0x00C0 ICR 334 uint32_t reg; 335 struct { 336 uint8_t txdw:1; // tx descr witten back 337 uint8_t txqe:1; // tx queue empty 338 uint8_t lsc:1; // link status change 339 uint8_t rxseq:1; // rcv sequence error 340 uint8_t rxdmt0:1; // rcv descriptor min thresh 341 uint8_t rsvd1:1; // reserved 342 uint8_t rxo:1; // receive overrunn 343 uint8_t rxt0:1; // receiver timer interrupt 344 uint8_t rsvd2:1; // reserved 345 uint8_t mdac:1; // mdi/o access complete 346 uint8_t rxcfg:1; // recv /c/ ordered sets 347 uint8_t rsvd3:1; // reserved 348 uint8_t phyint:1; // phy interrupt 349 uint8_t gpi1:1; // gpi int 1 350 uint8_t gpi2:1; // gpi int 2 351 uint8_t txdlow:1; // transmit desc low thresh 352 uint8_t srpd:1; // small receive packet detected 353 uint16_t rsvd4:15; // reserved 354 } ; 355 } icd; 356 357 union { // 0x00C0 IMC 358 uint32_t reg; 359 struct { 360 uint8_t txdw:1; // tx descr witten back 361 uint8_t txqe:1; // tx queue empty 362 uint8_t lsc:1; // link status change 363 uint8_t rxseq:1; // rcv sequence error 364 uint8_t rxdmt0:1; // rcv descriptor min thresh 365 uint8_t rsvd1:1; // reserved 366 uint8_t rxo:1; // receive overrunn 367 uint8_t rxt0:1; // receiver timer interrupt 368 uint8_t rsvd2:1; // reserved 369 uint8_t mdac:1; // mdi/o access complete 370 uint8_t rxcfg:1; // recv /c/ ordered sets 371 uint8_t rsvd3:1; // reserved 372 uint8_t phyint:1; // phy interrupt 373 uint8_t gpi1:1; // gpi int 1 374 uint8_t gpi2:1; // gpi int 2 375 uint8_t txdlow:1; // transmit desc low thresh 376 uint8_t srpd:1; // small receive packet detected 377 uint16_t rsvd4:15; // reserved 378 } ; 379 } imc; 380 381 union { // 0x0100 RCTL 382 uint32_t reg; 383 struct { 384 uint8_t rst:1; // Reset 385 uint8_t en:1; // Enable 386 uint8_t sbp:1; // Store bad packets 387 uint8_t upe:1; // Unicast Promiscuous enabled 388 uint8_t mpe:1; // Multicast promiscuous enabled 389 uint8_t lpe:1; // long packet reception enabled 390 uint8_t lbm:2; // 391 uint8_t rdmts:2; // 392 uint8_t rsvd:2; // 393 uint8_t mo:2; // 394 uint8_t mdr:1; // 395 uint8_t bam:1; // 396 uint8_t bsize:2; // 397 uint8_t vpe:1; // 398 uint8_t cfien:1; // 399 uint8_t cfi:1; // 400 uint8_t rsvd2:1; // 401 uint8_t dpf:1; // discard pause frames 402 uint8_t pmcf:1; // pass mac control frames 403 uint8_t rsvd3:1; // reserved 404 uint8_t bsex:1; // buffer size extension 405 uint8_t secrc:1; // strip ethernet crc from incoming packet 406 uint8_t rsvd1:5; // reserved 407 } ; 408 } rctl; 409 410 union { // 0x0400 TCTL 411 uint32_t reg; 412 struct { 413 uint8_t rst:1; // Reset 414 uint8_t en:1; // Enable 415 uint8_t bce:1; // busy check enable 416 uint8_t psp:1; // pad short packets 417 uint8_t ct:8; // collision threshold 418 uint16_t cold:10; // collision distance 419 uint8_t swxoff:1; // software xoff transmission 420 uint8_t pbe:1; // packet burst enable 421 uint8_t rtlc:1; // retransmit late collisions 422 uint8_t nrtu:1; // on underrun no TX 423 uint8_t mulr:1; // multiple request 424 uint8_t rsvd:5; // reserved 425 } ; 426 } tctl; 427 428 union { // 0x5820 MANC 429 uint32_t reg; 430 struct { 431 uint8_t smbus:1; // SMBus enabled ##### 432 uint8_t asf:1; // ASF enabled ##### 433 uint8_t ronforce:1; // reset of force 434 uint8_t rsvd:5; // reserved 435 uint8_t rmcp1:1; // rcmp1 filtering 436 uint8_t rmcp2:1; // rcmp2 filtering 437 uint8_t ipv4:1; // enable ipv4 438 uint8_t ipv6:1; // enable ipv6 439 uint8_t snap:1; // accept snap 440 uint8_t arp:1; // filter arp ##### 441 uint8_t neighbor:1; // neighbor discovery 442 uint8_t arp_resp:1; // arp response 443 uint8_t tcorst:1; // tco reset happened 444 uint8_t rcvtco:1; // receive tco enabled ###### 445 uint8_t blkphyrst:1;// block phy resets ######## 446 uint8_t rcvall:1; // receive all 447 uint8_t macaddrfltr:1; // mac address filtering ###### 448 uint8_t mng2host:1; // mng2 host packets ####### 449 uint8_t ipaddrfltr:1; // ip address filtering 450 uint8_t xsumfilter:1; // checksum filtering 451 uint8_t brfilter:1; // broadcast filtering 452 uint8_t smbreq:1; // smb request 453 uint8_t smbgnt:1; // smb grant 454 uint8_t smbclkin:1; // smbclkin 455 uint8_t smbdatain:1; // smbdatain 456 uint8_t smbdataout:1; // smb data out 457 uint8_t smbclkout:1; // smb clock out 458 uint8_t rsvd2:2; 459 }; 460 } manc; 461}; 462 463}; // iGbReg namespace 464