i8254xGBe.hh revision 9342
15245Sgblack@eecs.umich.edu/* 25245Sgblack@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 35245Sgblack@eecs.umich.edu * All rights reserved. 45245Sgblack@eecs.umich.edu * 57087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 67087Snate@binkert.org * modification, are permitted provided that the following conditions are 77087Snate@binkert.org * met: redistributions of source code must retain the above copyright 87087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 97087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 107087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 117087Snate@binkert.org * documentation and/or other materials provided with the distribution; 127087Snate@binkert.org * neither the name of the copyright holders nor the names of its 135245Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147087Snate@binkert.org * this software without specific prior written permission. 157087Snate@binkert.org * 167087Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177087Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187087Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197087Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207087Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217087Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225245Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237087Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245245Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255245Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265245Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275245Sgblack@eecs.umich.edu * 285245Sgblack@eecs.umich.edu * Authors: Ali Saidi 295245Sgblack@eecs.umich.edu */ 305245Sgblack@eecs.umich.edu 315245Sgblack@eecs.umich.edu/* @file 325245Sgblack@eecs.umich.edu * Device model for Intel's 8254x line of gigabit ethernet controllers. 335245Sgblack@eecs.umich.edu */ 345245Sgblack@eecs.umich.edu 355245Sgblack@eecs.umich.edu#ifndef __DEV_I8254XGBE_HH__ 365245Sgblack@eecs.umich.edu#define __DEV_I8254XGBE_HH__ 375245Sgblack@eecs.umich.edu 385245Sgblack@eecs.umich.edu#include <deque> 395245Sgblack@eecs.umich.edu#include <string> 405245Sgblack@eecs.umich.edu 415245Sgblack@eecs.umich.edu#include "base/cp_annotate.hh" 425245Sgblack@eecs.umich.edu#include "base/inet.hh" 435245Sgblack@eecs.umich.edu#include "debug/EthernetDesc.hh" 445245Sgblack@eecs.umich.edu#include "debug/EthernetIntr.hh" 455245Sgblack@eecs.umich.edu#include "dev/etherdevice.hh" 465245Sgblack@eecs.umich.edu#include "dev/etherint.hh" 478229Snate@binkert.org#include "dev/etherpkt.hh" 486216Snate@binkert.org#include "dev/i8254xGBe_defs.hh" 495245Sgblack@eecs.umich.edu#include "dev/pcidev.hh" 505245Sgblack@eecs.umich.edu#include "dev/pktfifo.hh" 515245Sgblack@eecs.umich.edu#include "params/IGbE.hh" 527901Shestness@cs.utexas.edu#include "sim/eventq.hh" 538832SAli.Saidi@ARM.com 545245Sgblack@eecs.umich.educlass IGbEInt; 555245Sgblack@eecs.umich.edu 565245Sgblack@eecs.umich.educlass IGbE : public EtherDevice 575245Sgblack@eecs.umich.edu{ 585245Sgblack@eecs.umich.edu private: 595245Sgblack@eecs.umich.edu IGbEInt *etherInt; 605245Sgblack@eecs.umich.edu CPA *cpa; 615245Sgblack@eecs.umich.edu 627912Shestness@cs.utexas.edu // device registers 635245Sgblack@eecs.umich.edu iGbReg::Regs regs; 645245Sgblack@eecs.umich.edu 655245Sgblack@eecs.umich.edu // eeprom data, status and control bits 665245Sgblack@eecs.umich.edu int eeOpBits, eeAddrBits, eeDataBits; 678711Sandreas.hansson@arm.com uint8_t eeOpcode, eeAddr; 685245Sgblack@eecs.umich.edu uint16_t flash[iGbReg::EEPROM_SIZE]; 695245Sgblack@eecs.umich.edu 705245Sgblack@eecs.umich.edu // The drain event if we have one 718832SAli.Saidi@ARM.com DrainManager *drainManager; 725245Sgblack@eecs.umich.edu 735245Sgblack@eecs.umich.edu // cached parameters from params struct 745245Sgblack@eecs.umich.edu bool useFlowControl; 755245Sgblack@eecs.umich.edu 768711Sandreas.hansson@arm.com // packet fifos 775245Sgblack@eecs.umich.edu PacketFifo rxFifo; 788711Sandreas.hansson@arm.com PacketFifo txFifo; 795245Sgblack@eecs.umich.edu 805245Sgblack@eecs.umich.edu // Packet that we are currently putting into the txFifo 817912Shestness@cs.utexas.edu EthPacketPtr txPacket; 827912Shestness@cs.utexas.edu 835245Sgblack@eecs.umich.edu // Should to Rx/Tx State machine tick? 845245Sgblack@eecs.umich.edu bool rxTick; 857912Shestness@cs.utexas.edu bool txTick; 867912Shestness@cs.utexas.edu bool txFifoTick; 877912Shestness@cs.utexas.edu 887912Shestness@cs.utexas.edu bool rxDmaPacket; 897912Shestness@cs.utexas.edu 907912Shestness@cs.utexas.edu // Number of bytes copied from current RX packet 917912Shestness@cs.utexas.edu unsigned pktOffset; 927912Shestness@cs.utexas.edu 937912Shestness@cs.utexas.edu // Delays in managaging descriptors 947912Shestness@cs.utexas.edu Tick fetchDelay, wbDelay; 957912Shestness@cs.utexas.edu Tick fetchCompDelay, wbCompDelay; 967912Shestness@cs.utexas.edu Tick rxWriteDelay, txReadDelay; 977912Shestness@cs.utexas.edu 987912Shestness@cs.utexas.edu // Event and function to deal with RDTR timer expiring 995245Sgblack@eecs.umich.edu void rdtrProcess() { 1007912Shestness@cs.utexas.edu rxDescCache.writeback(0); 1018832SAli.Saidi@ARM.com DPRINTF(EthernetIntr, 1027912Shestness@cs.utexas.edu "Posting RXT interrupt because RDTR timer expired\n"); 1037912Shestness@cs.utexas.edu postInterrupt(iGbReg::IT_RXT); 1047912Shestness@cs.utexas.edu } 1057912Shestness@cs.utexas.edu 1067912Shestness@cs.utexas.edu //friend class EventWrapper<IGbE, &IGbE::rdtrProcess>; 1077912Shestness@cs.utexas.edu EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent; 1087912Shestness@cs.utexas.edu 1097912Shestness@cs.utexas.edu // Event and function to deal with RADV timer expiring 1107912Shestness@cs.utexas.edu void radvProcess() { 1117912Shestness@cs.utexas.edu rxDescCache.writeback(0); 1127912Shestness@cs.utexas.edu DPRINTF(EthernetIntr, 1137912Shestness@cs.utexas.edu "Posting RXT interrupt because RADV timer expired\n"); 1147912Shestness@cs.utexas.edu postInterrupt(iGbReg::IT_RXT); 1157912Shestness@cs.utexas.edu } 1167912Shestness@cs.utexas.edu 1177912Shestness@cs.utexas.edu //friend class EventWrapper<IGbE, &IGbE::radvProcess>; 1187912Shestness@cs.utexas.edu EventWrapper<IGbE, &IGbE::radvProcess> radvEvent; 1197912Shestness@cs.utexas.edu 1207912Shestness@cs.utexas.edu // Event and function to deal with TADV timer expiring 1217912Shestness@cs.utexas.edu void tadvProcess() { 1227912Shestness@cs.utexas.edu txDescCache.writeback(0); 1237912Shestness@cs.utexas.edu DPRINTF(EthernetIntr, 1247912Shestness@cs.utexas.edu "Posting TXDW interrupt because TADV timer expired\n"); 1257912Shestness@cs.utexas.edu postInterrupt(iGbReg::IT_TXDW); 1267912Shestness@cs.utexas.edu } 1277912Shestness@cs.utexas.edu 1287912Shestness@cs.utexas.edu //friend class EventWrapper<IGbE, &IGbE::tadvProcess>; 1297912Shestness@cs.utexas.edu EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent; 1307912Shestness@cs.utexas.edu 1317912Shestness@cs.utexas.edu // Event and function to deal with TIDV timer expiring 1327912Shestness@cs.utexas.edu void tidvProcess() { 1337912Shestness@cs.utexas.edu txDescCache.writeback(0); 1347912Shestness@cs.utexas.edu DPRINTF(EthernetIntr, 1357912Shestness@cs.utexas.edu "Posting TXDW interrupt because TIDV timer expired\n"); 1367912Shestness@cs.utexas.edu postInterrupt(iGbReg::IT_TXDW); 1377912Shestness@cs.utexas.edu } 1387912Shestness@cs.utexas.edu //friend class EventWrapper<IGbE, &IGbE::tidvProcess>; 1397912Shestness@cs.utexas.edu EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent; 1407912Shestness@cs.utexas.edu 1417912Shestness@cs.utexas.edu // Main event to tick the device 1427912Shestness@cs.utexas.edu void tick(); 1437912Shestness@cs.utexas.edu //friend class EventWrapper<IGbE, &IGbE::tick>; 1447912Shestness@cs.utexas.edu EventWrapper<IGbE, &IGbE::tick> tickEvent; 1457912Shestness@cs.utexas.edu 1467912Shestness@cs.utexas.edu 1477912Shestness@cs.utexas.edu uint64_t macAddr; 1487912Shestness@cs.utexas.edu 1497912Shestness@cs.utexas.edu void rxStateMachine(); 1507912Shestness@cs.utexas.edu void txStateMachine(); 1517912Shestness@cs.utexas.edu void txWire(); 1527912Shestness@cs.utexas.edu 1537912Shestness@cs.utexas.edu /** Write an interrupt into the interrupt pending register and check mask 1547912Shestness@cs.utexas.edu * and interrupt limit timer before sending interrupt to CPU 1557912Shestness@cs.utexas.edu * @param t the type of interrupt we are posting 1567912Shestness@cs.utexas.edu * @param now should we ignore the interrupt limiting timer 1577912Shestness@cs.utexas.edu */ 1587912Shestness@cs.utexas.edu void postInterrupt(iGbReg::IntTypes t, bool now = false); 1597912Shestness@cs.utexas.edu 1607912Shestness@cs.utexas.edu /** Check and see if changes to the mask register have caused an interrupt 1617912Shestness@cs.utexas.edu * to need to be sent or perhaps removed an interrupt cause. 1627912Shestness@cs.utexas.edu */ 1637912Shestness@cs.utexas.edu void chkInterrupt(); 1647912Shestness@cs.utexas.edu 1657912Shestness@cs.utexas.edu /** Send an interrupt to the cpu 1667912Shestness@cs.utexas.edu */ 1677912Shestness@cs.utexas.edu void delayIntEvent(); 1687912Shestness@cs.utexas.edu void cpuPostInt(); 1697912Shestness@cs.utexas.edu // Event to moderate interrupts 1707912Shestness@cs.utexas.edu EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent; 1717912Shestness@cs.utexas.edu 1725245Sgblack@eecs.umich.edu /** Clear the interupt line to the cpu 1735245Sgblack@eecs.umich.edu */ 1745245Sgblack@eecs.umich.edu void cpuClearInt(); 1758832SAli.Saidi@ARM.com 1765245Sgblack@eecs.umich.edu Tick intClock() { return SimClock::Int::ns * 1024; } 1777912Shestness@cs.utexas.edu 1787912Shestness@cs.utexas.edu /** This function is used to restart the clock so it can handle things like 1797912Shestness@cs.utexas.edu * draining and resume in one place. */ 1807912Shestness@cs.utexas.edu void restartClock(); 1815245Sgblack@eecs.umich.edu 1825245Sgblack@eecs.umich.edu /** Check if all the draining things that need to occur have occured and 1835245Sgblack@eecs.umich.edu * handle the drain event if so. 1845245Sgblack@eecs.umich.edu */ 1855245Sgblack@eecs.umich.edu void checkDrain(); 1865245Sgblack@eecs.umich.edu 1875245Sgblack@eecs.umich.edu void anBegin(std::string sm, std::string st, int flags = CPA::FL_NONE) { 1885245Sgblack@eecs.umich.edu cpa->hwBegin((CPA::flags)flags, sys, macAddr, sm, st); 1895245Sgblack@eecs.umich.edu } 1905245Sgblack@eecs.umich.edu 1918832SAli.Saidi@ARM.com void anQ(std::string sm, std::string q) { 1928832SAli.Saidi@ARM.com cpa->hwQ(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 1938832SAli.Saidi@ARM.com } 1948832SAli.Saidi@ARM.com 1958832SAli.Saidi@ARM.com void anDq(std::string sm, std::string q) { 1968832SAli.Saidi@ARM.com cpa->hwDq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 1975245Sgblack@eecs.umich.edu } 1987912Shestness@cs.utexas.edu 1998832SAli.Saidi@ARM.com void anPq(std::string sm, std::string q, int num = 1) { 2008832SAli.Saidi@ARM.com cpa->hwPq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num); 2015245Sgblack@eecs.umich.edu } 2025245Sgblack@eecs.umich.edu 2035245Sgblack@eecs.umich.edu void anRq(std::string sm, std::string q, int num = 1) { 2045245Sgblack@eecs.umich.edu cpa->hwRq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num); 2055245Sgblack@eecs.umich.edu } 206 207 void anWe(std::string sm, std::string q) { 208 cpa->hwWe(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 209 } 210 211 void anWf(std::string sm, std::string q) { 212 cpa->hwWf(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 213 } 214 215 216 template<class T> 217 class DescCache 218 { 219 protected: 220 virtual Addr descBase() const = 0; 221 virtual long descHead() const = 0; 222 virtual long descTail() const = 0; 223 virtual long descLen() const = 0; 224 virtual void updateHead(long h) = 0; 225 virtual void enableSm() = 0; 226 virtual void actionAfterWb() {} 227 virtual void fetchAfterWb() = 0; 228 229 typedef std::deque<T *> CacheType; 230 CacheType usedCache; 231 CacheType unusedCache; 232 233 T *fetchBuf; 234 T *wbBuf; 235 236 // Pointer to the device we cache for 237 IGbE *igbe; 238 239 // Name of this descriptor cache 240 std::string _name; 241 242 // How far we've cached 243 int cachePnt; 244 245 // The size of the descriptor cache 246 int size; 247 248 // How many descriptors we are currently fetching 249 int curFetching; 250 251 // How many descriptors we are currently writing back 252 int wbOut; 253 254 // if the we wrote back to the end of the descriptor ring and are going 255 // to have to wrap and write more 256 bool moreToWb; 257 258 // What the alignment is of the next descriptor writeback 259 Addr wbAlignment; 260 261 /** The packet that is currently being dmad to memory if any */ 262 EthPacketPtr pktPtr; 263 264 /** Shortcut for DMA address translation */ 265 Addr pciToDma(Addr a) { return igbe->platform->pciToDma(a); } 266 267 public: 268 /** Annotate sm*/ 269 std::string annSmFetch, annSmWb, annUnusedDescQ, annUsedCacheQ, 270 annUsedDescQ, annUnusedCacheQ, annDescQ; 271 272 DescCache(IGbE *i, const std::string n, int s); 273 virtual ~DescCache(); 274 275 std::string name() { return _name; } 276 277 /** If the address/len/head change when we've got descriptors that are 278 * dirty that is very bad. This function checks that we don't and if we 279 * do panics. 280 */ 281 void areaChanged(); 282 283 void writeback(Addr aMask); 284 void writeback1(); 285 EventWrapper<DescCache, &DescCache::writeback1> wbDelayEvent; 286 287 /** Fetch a chunk of descriptors into the descriptor cache. 288 * Calls fetchComplete when the memory system returns the data 289 */ 290 void fetchDescriptors(); 291 void fetchDescriptors1(); 292 EventWrapper<DescCache, &DescCache::fetchDescriptors1> fetchDelayEvent; 293 294 /** Called by event when dma to read descriptors is completed 295 */ 296 void fetchComplete(); 297 EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent; 298 299 /** Called by event when dma to writeback descriptors is completed 300 */ 301 void wbComplete(); 302 EventWrapper<DescCache, &DescCache::wbComplete> wbEvent; 303 304 /* Return the number of descriptors left in the ring, so the device has 305 * a way to figure out if it needs to interrupt. 306 */ 307 unsigned 308 descLeft() const 309 { 310 unsigned left = unusedCache.size(); 311 if (cachePnt > descTail()) 312 left += (descLen() - cachePnt + descTail()); 313 else 314 left += (descTail() - cachePnt); 315 316 return left; 317 } 318 319 /* Return the number of descriptors used and not written back. 320 */ 321 unsigned descUsed() const { return usedCache.size(); } 322 323 /* Return the number of cache unused descriptors we have. */ 324 unsigned descUnused() const { return unusedCache.size(); } 325 326 /* Get into a state where the descriptor address/head/etc colud be 327 * changed */ 328 void reset(); 329 330 virtual void serialize(std::ostream &os); 331 virtual void unserialize(Checkpoint *cp, const std::string §ion); 332 333 virtual bool hasOutstandingEvents() { 334 return wbEvent.scheduled() || fetchEvent.scheduled(); 335 } 336 337 }; 338 339 340 class RxDescCache : public DescCache<iGbReg::RxDesc> 341 { 342 protected: 343 virtual Addr descBase() const { return igbe->regs.rdba(); } 344 virtual long descHead() const { return igbe->regs.rdh(); } 345 virtual long descLen() const { return igbe->regs.rdlen() >> 4; } 346 virtual long descTail() const { return igbe->regs.rdt(); } 347 virtual void updateHead(long h) { igbe->regs.rdh(h); } 348 virtual void enableSm(); 349 virtual void fetchAfterWb() { 350 if (!igbe->rxTick && igbe->getDrainState() == Drainable::Running) 351 fetchDescriptors(); 352 } 353 354 bool pktDone; 355 356 /** Variable to head with header/data completion events */ 357 int splitCount; 358 359 /** Bytes of packet that have been copied, so we know when to 360 set EOP */ 361 unsigned bytesCopied; 362 363 public: 364 RxDescCache(IGbE *i, std::string n, int s); 365 366 /** Write the given packet into the buffer(s) pointed to by the 367 * descriptor and update the book keeping. Should only be called when 368 * there are no dma's pending. 369 * @param packet ethernet packet to write 370 * @param pkt_offset bytes already copied from the packet to memory 371 * @return pkt_offset + number of bytes copied during this call 372 */ 373 int writePacket(EthPacketPtr packet, int pkt_offset); 374 375 /** Called by event when dma to write packet is completed 376 */ 377 void pktComplete(); 378 379 /** Check if the dma on the packet has completed and RX state machine 380 * can continue 381 */ 382 bool packetDone(); 383 384 EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent; 385 386 // Event to handle issuing header and data write at the same time 387 // and only callking pktComplete() when both are completed 388 void pktSplitDone(); 389 EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent; 390 EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent; 391 392 virtual bool hasOutstandingEvents(); 393 394 virtual void serialize(std::ostream &os); 395 virtual void unserialize(Checkpoint *cp, const std::string §ion); 396 }; 397 friend class RxDescCache; 398 399 RxDescCache rxDescCache; 400 401 class TxDescCache : public DescCache<iGbReg::TxDesc> 402 { 403 protected: 404 virtual Addr descBase() const { return igbe->regs.tdba(); } 405 virtual long descHead() const { return igbe->regs.tdh(); } 406 virtual long descTail() const { return igbe->regs.tdt(); } 407 virtual long descLen() const { return igbe->regs.tdlen() >> 4; } 408 virtual void updateHead(long h) { igbe->regs.tdh(h); } 409 virtual void enableSm(); 410 virtual void actionAfterWb(); 411 virtual void fetchAfterWb() { 412 if (!igbe->txTick && igbe->getDrainState() == Drainable::Running) 413 fetchDescriptors(); 414 } 415 416 417 418 bool pktDone; 419 bool isTcp; 420 bool pktWaiting; 421 bool pktMultiDesc; 422 Addr completionAddress; 423 bool completionEnabled; 424 uint32_t descEnd; 425 426 427 // tso variables 428 bool useTso; 429 Addr tsoHeaderLen; 430 Addr tsoMss; 431 Addr tsoTotalLen; 432 Addr tsoUsedLen; 433 Addr tsoPrevSeq; 434 Addr tsoPktPayloadBytes; 435 bool tsoLoadedHeader; 436 bool tsoPktHasHeader; 437 uint8_t tsoHeader[256]; 438 Addr tsoDescBytesUsed; 439 Addr tsoCopyBytes; 440 int tsoPkts; 441 442 public: 443 TxDescCache(IGbE *i, std::string n, int s); 444 445 /** Tell the cache to DMA a packet from main memory into its buffer and 446 * return the size the of the packet to reserve space in tx fifo. 447 * @return size of the packet 448 */ 449 unsigned getPacketSize(EthPacketPtr p); 450 void getPacketData(EthPacketPtr p); 451 void processContextDesc(); 452 453 /** Return the number of dsecriptors in a cache block for threshold 454 * operations. 455 */ 456 unsigned 457 descInBlock(unsigned num_desc) 458 { 459 return num_desc / igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc); 460 } 461 462 /** Ask if the packet has been transfered so the state machine can give 463 * it to the fifo. 464 * @return packet available in descriptor cache 465 */ 466 bool packetAvailable(); 467 468 /** Ask if we are still waiting for the packet to be transfered. 469 * @return packet still in transit. 470 */ 471 bool packetWaiting() { return pktWaiting; } 472 473 /** Ask if this packet is composed of multiple descriptors 474 * so even if we've got data, we need to wait for more before 475 * we can send it out. 476 * @return packet can't be sent out because it's a multi-descriptor 477 * packet 478 */ 479 bool packetMultiDesc() { return pktMultiDesc;} 480 481 /** Called by event when dma to write packet is completed 482 */ 483 void pktComplete(); 484 EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent; 485 486 void headerComplete(); 487 EventWrapper<TxDescCache, &TxDescCache::headerComplete> headerEvent; 488 489 490 void completionWriteback(Addr a, bool enabled) { 491 DPRINTF(EthernetDesc, 492 "Completion writeback Addr: %#x enabled: %d\n", 493 a, enabled); 494 completionAddress = a; 495 completionEnabled = enabled; 496 } 497 498 virtual bool hasOutstandingEvents(); 499 500 void nullCallback() { 501 DPRINTF(EthernetDesc, "Completion writeback complete\n"); 502 } 503 EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent; 504 505 virtual void serialize(std::ostream &os); 506 virtual void unserialize(Checkpoint *cp, const std::string §ion); 507 508 }; 509 friend class TxDescCache; 510 511 TxDescCache txDescCache; 512 513 public: 514 typedef IGbEParams Params; 515 const Params * 516 params() const { 517 return dynamic_cast<const Params *>(_params); 518 } 519 520 IGbE(const Params *params); 521 ~IGbE(); 522 virtual void init(); 523 524 virtual EtherInt *getEthPort(const std::string &if_name, int idx); 525 526 Tick lastInterrupt; 527 528 virtual Tick read(PacketPtr pkt); 529 virtual Tick write(PacketPtr pkt); 530 531 virtual Tick writeConfig(PacketPtr pkt); 532 533 bool ethRxPkt(EthPacketPtr packet); 534 void ethTxDone(); 535 536 virtual void serialize(std::ostream &os); 537 virtual void unserialize(Checkpoint *cp, const std::string §ion); 538 539 unsigned int drain(DrainManager *dm); 540 void drainResume(); 541 542}; 543 544class IGbEInt : public EtherInt 545{ 546 private: 547 IGbE *dev; 548 549 public: 550 IGbEInt(const std::string &name, IGbE *d) 551 : EtherInt(name), dev(d) 552 { } 553 554 virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); } 555 virtual void sendDone() { dev->ethTxDone(); } 556}; 557 558#endif //__DEV_I8254XGBE_HH__ 559