i8254xGBe.hh revision 7064
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31/* @file 32 * Device model for Intel's 8254x line of gigabit ethernet controllers. 33 */ 34 35#ifndef __DEV_I8254XGBE_HH__ 36#define __DEV_I8254XGBE_HH__ 37 38#include <deque> 39#include <string> 40 41#include "base/cp_annotate.hh" 42#include "base/inet.hh" 43#include "dev/etherdevice.hh" 44#include "dev/etherint.hh" 45#include "dev/etherpkt.hh" 46#include "dev/i8254xGBe_defs.hh" 47#include "dev/pcidev.hh" 48#include "dev/pktfifo.hh" 49#include "params/IGbE.hh" 50#include "sim/eventq.hh" 51 52class IGbEInt; 53 54class IGbE : public EtherDevice 55{ 56 private: 57 IGbEInt *etherInt; 58 CPA *cpa; 59 60 // device registers 61 iGbReg::Regs regs; 62 63 // eeprom data, status and control bits 64 int eeOpBits, eeAddrBits, eeDataBits; 65 uint8_t eeOpcode, eeAddr; 66 uint16_t flash[iGbReg::EEPROM_SIZE]; 67 68 // The drain event if we have one 69 Event *drainEvent; 70 71 // cached parameters from params struct 72 bool useFlowControl; 73 74 // packet fifos 75 PacketFifo rxFifo; 76 PacketFifo txFifo; 77 78 // Packet that we are currently putting into the txFifo 79 EthPacketPtr txPacket; 80 81 // Should to Rx/Tx State machine tick? 82 bool rxTick; 83 bool txTick; 84 bool txFifoTick; 85 86 bool rxDmaPacket; 87 88 // Number of bytes copied from current RX packet 89 unsigned pktOffset; 90 91 // Delays in managaging descriptors 92 Tick fetchDelay, wbDelay; 93 Tick fetchCompDelay, wbCompDelay; 94 Tick rxWriteDelay, txReadDelay; 95 96 // Event and function to deal with RDTR timer expiring 97 void rdtrProcess() { 98 rxDescCache.writeback(0); 99 DPRINTF(EthernetIntr, 100 "Posting RXT interrupt because RDTR timer expired\n"); 101 postInterrupt(iGbReg::IT_RXT); 102 } 103 104 //friend class EventWrapper<IGbE, &IGbE::rdtrProcess>; 105 EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent; 106 107 // Event and function to deal with RADV timer expiring 108 void radvProcess() { 109 rxDescCache.writeback(0); 110 DPRINTF(EthernetIntr, 111 "Posting RXT interrupt because RADV timer expired\n"); 112 postInterrupt(iGbReg::IT_RXT); 113 } 114 115 //friend class EventWrapper<IGbE, &IGbE::radvProcess>; 116 EventWrapper<IGbE, &IGbE::radvProcess> radvEvent; 117 118 // Event and function to deal with TADV timer expiring 119 void tadvProcess() { 120 txDescCache.writeback(0); 121 DPRINTF(EthernetIntr, 122 "Posting TXDW interrupt because TADV timer expired\n"); 123 postInterrupt(iGbReg::IT_TXDW); 124 } 125 126 //friend class EventWrapper<IGbE, &IGbE::tadvProcess>; 127 EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent; 128 129 // Event and function to deal with TIDV timer expiring 130 void tidvProcess() { 131 txDescCache.writeback(0); 132 DPRINTF(EthernetIntr, 133 "Posting TXDW interrupt because TIDV timer expired\n"); 134 postInterrupt(iGbReg::IT_TXDW); 135 } 136 //friend class EventWrapper<IGbE, &IGbE::tidvProcess>; 137 EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent; 138 139 // Main event to tick the device 140 void tick(); 141 //friend class EventWrapper<IGbE, &IGbE::tick>; 142 EventWrapper<IGbE, &IGbE::tick> tickEvent; 143 144 145 uint64_t macAddr; 146 147 void rxStateMachine(); 148 void txStateMachine(); 149 void txWire(); 150 151 /** Write an interrupt into the interrupt pending register and check mask 152 * and interrupt limit timer before sending interrupt to CPU 153 * @param t the type of interrupt we are posting 154 * @param now should we ignore the interrupt limiting timer 155 */ 156 void postInterrupt(iGbReg::IntTypes t, bool now = false); 157 158 /** Check and see if changes to the mask register have caused an interrupt 159 * to need to be sent or perhaps removed an interrupt cause. 160 */ 161 void chkInterrupt(); 162 163 /** Send an interrupt to the cpu 164 */ 165 void delayIntEvent(); 166 void cpuPostInt(); 167 // Event to moderate interrupts 168 EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent; 169 170 /** Clear the interupt line to the cpu 171 */ 172 void cpuClearInt(); 173 174 Tick intClock() { return SimClock::Int::ns * 1024; } 175 176 /** This function is used to restart the clock so it can handle things like 177 * draining and resume in one place. */ 178 void restartClock(); 179 180 /** Check if all the draining things that need to occur have occured and 181 * handle the drain event if so. 182 */ 183 void checkDrain(); 184 185 void anBegin(std::string sm, std::string st, int flags = CPA::FL_NONE) { 186 cpa->hwBegin((CPA::flags)flags, sys, macAddr, sm, st); 187 } 188 189 void anQ(std::string sm, std::string q) { 190 cpa->hwQ(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 191 } 192 193 void anDq(std::string sm, std::string q) { 194 cpa->hwDq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 195 } 196 197 void anPq(std::string sm, std::string q, int num = 1) { 198 cpa->hwPq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num); 199 } 200 201 void anRq(std::string sm, std::string q, int num = 1) { 202 cpa->hwRq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num); 203 } 204 205 void anWe(std::string sm, std::string q) { 206 cpa->hwWe(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 207 } 208 209 void anWf(std::string sm, std::string q) { 210 cpa->hwWf(CPA::FL_NONE, sys, macAddr, sm, q, macAddr); 211 } 212 213 214 template<class T> 215 class DescCache 216 { 217 protected: 218 virtual Addr descBase() const = 0; 219 virtual long descHead() const = 0; 220 virtual long descTail() const = 0; 221 virtual long descLen() const = 0; 222 virtual void updateHead(long h) = 0; 223 virtual void enableSm() = 0; 224 virtual void actionAfterWb() {} 225 virtual void fetchAfterWb() = 0; 226 227 typedef std::deque<T *> CacheType; 228 CacheType usedCache; 229 CacheType unusedCache; 230 231 T *fetchBuf; 232 T *wbBuf; 233 234 // Pointer to the device we cache for 235 IGbE *igbe; 236 237 // Name of this descriptor cache 238 std::string _name; 239 240 // How far we've cached 241 int cachePnt; 242 243 // The size of the descriptor cache 244 int size; 245 246 // How many descriptors we are currently fetching 247 int curFetching; 248 249 // How many descriptors we are currently writing back 250 int wbOut; 251 252 // if the we wrote back to the end of the descriptor ring and are going 253 // to have to wrap and write more 254 bool moreToWb; 255 256 // What the alignment is of the next descriptor writeback 257 Addr wbAlignment; 258 259 /** The packet that is currently being dmad to memory if any */ 260 EthPacketPtr pktPtr; 261 262 /** Shortcut for DMA address translation */ 263 Addr pciToDma(Addr a) { return igbe->platform->pciToDma(a); } 264 265 public: 266 /** Annotate sm*/ 267 std::string annSmFetch, annSmWb, annUnusedDescQ, annUsedCacheQ, 268 annUsedDescQ, annUnusedCacheQ, annDescQ; 269 270 DescCache(IGbE *i, const std::string n, int s); 271 virtual ~DescCache(); 272 273 std::string name() { return _name; } 274 275 /** If the address/len/head change when we've got descriptors that are 276 * dirty that is very bad. This function checks that we don't and if we 277 * do panics. 278 */ 279 void areaChanged(); 280 281 void writeback(Addr aMask); 282 void writeback1(); 283 EventWrapper<DescCache, &DescCache::writeback1> wbDelayEvent; 284 285 /** Fetch a chunk of descriptors into the descriptor cache. 286 * Calls fetchComplete when the memory system returns the data 287 */ 288 void fetchDescriptors(); 289 void fetchDescriptors1(); 290 EventWrapper<DescCache, &DescCache::fetchDescriptors1> fetchDelayEvent; 291 292 /** Called by event when dma to read descriptors is completed 293 */ 294 void fetchComplete(); 295 EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent; 296 297 /** Called by event when dma to writeback descriptors is completed 298 */ 299 void wbComplete(); 300 EventWrapper<DescCache, &DescCache::wbComplete> wbEvent; 301 302 /* Return the number of descriptors left in the ring, so the device has 303 * a way to figure out if it needs to interrupt. 304 */ 305 unsigned 306 descLeft() const 307 { 308 unsigned left = unusedCache.size(); 309 if (cachePnt > descTail()) 310 left += (descLen() - cachePnt + descTail()); 311 else 312 left += (descTail() - cachePnt); 313 314 return left; 315 } 316 317 /* Return the number of descriptors used and not written back. 318 */ 319 unsigned descUsed() const { return usedCache.size(); } 320 321 /* Return the number of cache unused descriptors we have. */ 322 unsigned descUnused() const { return unusedCache.size(); } 323 324 /* Get into a state where the descriptor address/head/etc colud be 325 * changed */ 326 void reset(); 327 328 virtual void serialize(std::ostream &os); 329 virtual void unserialize(Checkpoint *cp, const std::string §ion); 330 331 virtual bool hasOutstandingEvents() { 332 return wbEvent.scheduled() || fetchEvent.scheduled(); 333 } 334 335 }; 336 337 338 class RxDescCache : public DescCache<iGbReg::RxDesc> 339 { 340 protected: 341 virtual Addr descBase() const { return igbe->regs.rdba(); } 342 virtual long descHead() const { return igbe->regs.rdh(); } 343 virtual long descLen() const { return igbe->regs.rdlen() >> 4; } 344 virtual long descTail() const { return igbe->regs.rdt(); } 345 virtual void updateHead(long h) { igbe->regs.rdh(h); } 346 virtual void enableSm(); 347 virtual void fetchAfterWb() { 348 if (!igbe->rxTick && igbe->getState() == SimObject::Running) 349 fetchDescriptors(); 350 } 351 352 bool pktDone; 353 354 /** Variable to head with header/data completion events */ 355 int splitCount; 356 357 /** Bytes of packet that have been copied, so we know when to 358 set EOP */ 359 unsigned bytesCopied; 360 361 public: 362 RxDescCache(IGbE *i, std::string n, int s); 363 364 /** Write the given packet into the buffer(s) pointed to by the 365 * descriptor and update the book keeping. Should only be called when 366 * there are no dma's pending. 367 * @param packet ethernet packet to write 368 * @param pkt_offset bytes already copied from the packet to memory 369 * @return pkt_offset + number of bytes copied during this call 370 */ 371 int writePacket(EthPacketPtr packet, int pkt_offset); 372 373 /** Called by event when dma to write packet is completed 374 */ 375 void pktComplete(); 376 377 /** Check if the dma on the packet has completed and RX state machine 378 * can continue 379 */ 380 bool packetDone(); 381 382 EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent; 383 384 // Event to handle issuing header and data write at the same time 385 // and only callking pktComplete() when both are completed 386 void pktSplitDone(); 387 EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent; 388 EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent; 389 390 virtual bool hasOutstandingEvents(); 391 392 virtual void serialize(std::ostream &os); 393 virtual void unserialize(Checkpoint *cp, const std::string §ion); 394 }; 395 friend class RxDescCache; 396 397 RxDescCache rxDescCache; 398 399 class TxDescCache : public DescCache<iGbReg::TxDesc> 400 { 401 protected: 402 virtual Addr descBase() const { return igbe->regs.tdba(); } 403 virtual long descHead() const { return igbe->regs.tdh(); } 404 virtual long descTail() const { return igbe->regs.tdt(); } 405 virtual long descLen() const { return igbe->regs.tdlen() >> 4; } 406 virtual void updateHead(long h) { igbe->regs.tdh(h); } 407 virtual void enableSm(); 408 virtual void actionAfterWb(); 409 virtual void fetchAfterWb() { 410 if (!igbe->txTick && igbe->getState() == SimObject::Running) 411 fetchDescriptors(); 412 } 413 414 415 416 bool pktDone; 417 bool isTcp; 418 bool pktWaiting; 419 bool pktMultiDesc; 420 Addr completionAddress; 421 bool completionEnabled; 422 uint32_t descEnd; 423 424 425 // tso variables 426 bool useTso; 427 Addr tsoHeaderLen; 428 Addr tsoMss; 429 Addr tsoTotalLen; 430 Addr tsoUsedLen; 431 Addr tsoPrevSeq;; 432 Addr tsoPktPayloadBytes; 433 bool tsoLoadedHeader; 434 bool tsoPktHasHeader; 435 uint8_t tsoHeader[256]; 436 Addr tsoDescBytesUsed; 437 Addr tsoCopyBytes; 438 int tsoPkts; 439 440 public: 441 TxDescCache(IGbE *i, std::string n, int s); 442 443 /** Tell the cache to DMA a packet from main memory into its buffer and 444 * return the size the of the packet to reserve space in tx fifo. 445 * @return size of the packet 446 */ 447 unsigned getPacketSize(EthPacketPtr p); 448 void getPacketData(EthPacketPtr p); 449 void processContextDesc(); 450 451 /** Return the number of dsecriptors in a cache block for threshold 452 * operations. 453 */ 454 unsigned 455 descInBlock(unsigned num_desc) 456 { 457 return num_desc / igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc); 458 } 459 460 /** Ask if the packet has been transfered so the state machine can give 461 * it to the fifo. 462 * @return packet available in descriptor cache 463 */ 464 bool packetAvailable(); 465 466 /** Ask if we are still waiting for the packet to be transfered. 467 * @return packet still in transit. 468 */ 469 bool packetWaiting() { return pktWaiting; } 470 471 /** Ask if this packet is composed of multiple descriptors 472 * so even if we've got data, we need to wait for more before 473 * we can send it out. 474 * @return packet can't be sent out because it's a multi-descriptor 475 * packet 476 */ 477 bool packetMultiDesc() { return pktMultiDesc;} 478 479 /** Called by event when dma to write packet is completed 480 */ 481 void pktComplete(); 482 EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent; 483 484 void headerComplete(); 485 EventWrapper<TxDescCache, &TxDescCache::headerComplete> headerEvent; 486 487 488 void completionWriteback(Addr a, bool enabled) { 489 DPRINTF(EthernetDesc, 490 "Completion writeback Addr: %#x enabled: %d\n", 491 a, enabled); 492 completionAddress = a; 493 completionEnabled = enabled; 494 } 495 496 virtual bool hasOutstandingEvents(); 497 498 void nullCallback() { 499 DPRINTF(EthernetDesc, "Completion writeback complete\n"); 500 } 501 EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent; 502 503 virtual void serialize(std::ostream &os); 504 virtual void unserialize(Checkpoint *cp, const std::string §ion); 505 506 }; 507 friend class TxDescCache; 508 509 TxDescCache txDescCache; 510 511 public: 512 typedef IGbEParams Params; 513 const Params * 514 params() const { 515 return dynamic_cast<const Params *>(_params); 516 } 517 518 IGbE(const Params *params); 519 ~IGbE() {} 520 virtual void init(); 521 522 virtual EtherInt *getEthPort(const std::string &if_name, int idx); 523 524 Tick clock; 525 Tick lastInterrupt; 526 inline Tick ticks(int numCycles) const { return numCycles * clock; } 527 528 virtual Tick read(PacketPtr pkt); 529 virtual Tick write(PacketPtr pkt); 530 531 virtual Tick writeConfig(PacketPtr pkt); 532 533 bool ethRxPkt(EthPacketPtr packet); 534 void ethTxDone(); 535 536 virtual void serialize(std::ostream &os); 537 virtual void unserialize(Checkpoint *cp, const std::string §ion); 538 virtual unsigned int drain(Event *de); 539 virtual void resume(); 540 541}; 542 543class IGbEInt : public EtherInt 544{ 545 private: 546 IGbE *dev; 547 548 public: 549 IGbEInt(const std::string &name, IGbE *d) 550 : EtherInt(name), dev(d) 551 { } 552 553 virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); } 554 virtual void sendDone() { dev->ethTxDone(); } 555}; 556 557#endif //__DEV_I8254XGBE_HH__ 558